JP2980966B2 - Device and manufacturing method thereof - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for manufacturing an integrated circuit, particularly a high-speed integrated circuit.

[Prior Art] Various proposals have been made in research on improving the operation speed of a semiconductor integrated circuit. One particularly promising proposal is a method of forming an active device such as a field effect transistor on a semiconductor substrate such as silicon on an insulating region. This insulating region insulates the active device regions from most of the substrate, and insulates the active device regions from each other. This insulating region reduces stray capacitance, increases packaging density, and increases device speed.

Many methods have been proposed for producing regions of semiconductor material, such as silicon, which are separated from the bulk of the substrate by insulating regions and, as a result, are more adapted to the isolation between device regions. (The insulating region is a region having an electrical resistivity of 10 ⁸ ohm-cm or more.) As such a method, KE Bean (Bean) and WR Lanyan (Runyan) 's J. Electrochem. .) 124,5C (19
77)) and U.S. Pat.
There is the formation of an insulated silicon region manufactured from recrystallization of silicon and a dielectric region by ion implantation as disclosed in U.S. Pat. No. 0,086 (June 2, 1987). Recent methods include implanting oxygen below the surface of the silicon substrate to form a high concentration oxygen buried region. The high oxygen implanted region, disclosed in U.S. Pat. No. 4,676,841 dated June 30, 1987,
The method of annealing at a higher temperature forms a silicon dioxide buried region having relatively few defects on the silicon region.

In device fabrication studies, various device geometries have been used for such dielectric insulating substrates. In one such shape (shown in FIG. 1), impurities are implanted into the junction region between the silicon source region 4 and the silicon drain region 4 of the field effect transistor in order to increase its conductivity. As a result, the electrical contact resistance between the source and the drain is greatly reduced. After the impurity is implanted into the source / drain regions, the damage caused by the implantation is annealed to diffuse the implanted impurity in the impurity implanted region 15 of FIG.
The device is typically heated to a temperature between 900 and 1100 degrees to complete the electrical contact. This annealing method does in fact perfect the electrical contact between the source and the drain and substantially eliminates the damage caused by the implantation, but has the disadvantage of causing the diffusion of impurities into the region 6 under the gate 8. The dielectric region 10 below the region 15 prevents vertical diffusion of impurities, and since the region 6 under the gate 8 and the impurity implanted region 4 are silicon, the diffusion is relatively rapid and the source And drain conductivity (for example, 10-
In this case, an electrical short-circuit between the source and the drain may be caused in the worst case.

Similarly, source and drain contacts, including silicide contacts, cause the same problem in dielectric isolation devices. Even in high-speed devices, impurities are implanted into the silicon in the source and drain regions, usually from 900 ° C to 110 ° C.
Annealed at 0 ° C. Thereafter, a metal is deposited on the implanted silicon, and the metal / silicon bonding region is typically used to react the metal with silicon so that a conductive silicide (silicide) is formed. Heated from 400 ° C to 900 ° C (depending on metal). For the device configurations shown above, during the initial annealing process, a large amount of impurity diffusion occurs in the silicon region under the gate, and consequently the electrical properties are degraded. Thus, it has been difficult to achieve an increase in device speed while maintaining electrical properties.

[Summary of the Invention] In a high-speed device having low leakage characteristics, silicon is formed on an insulating substrate, silicide (silicide) is first formed in a region to be a source region and a drain region,
Impurities are implanted into the silicide regions (that is, the source and drain regions), and annealing is performed. As a specific example, there is a method of forming silicon on an insulating substrate by an oxygen implantation method.
"Materials Research Society Symp. Proceedings" by PLF Hemment, "Materials Research Society Symp. Proceedings" 5
3, pages 207 to 221 (1986). After that, the formation of the apparent junction device involves first depositing a metal on the silicon source region and the silicon drain region to form silicide, implanting impurities into the silicide region, and finally heating the implantation device. Done in The apparent junction device comprises 2000 Angstroms (hereinafter referred to as A) between (1) the surface of the source and drain regions and (2) the interface between the underlying p and n heavily doped impurities. (Substitute) A device with an area of the following thickness: Subsequent processing comprising implanting and heating the silicide region is specifically disclosed in U.S. patent application Ser. No. 07 / 209,149 (August 15, 1988). Since the properties between the silicon region under the gate and the source / drain regions made of silicide are greatly different, diffusion of impurities is limited, and excellent device characteristics are formed.

EXAMPLES The present invention is described below in terms of forming active devices on a dielectrically insulated silicon active region formed by implanting oxygen into a bulk silicon wafer. However, the present invention includes forming a high-speed device on a dielectrically insulated silicon region irrespective of the manufacturing method of this region. Appropriate methods of making the dielectric insulating region are known and described in GK Cellar's "UL
SI Science and Technology (ULSI Science
and Technology) (1987), Electrochemical Society Proceedings (Electrochemica)
l Society Proc.), Vol. 87, Chapter 11, pp. 696 to 711 (1987)
Year) and “MRS Symposium Proceedings (M
RS Symp. Proc.) ", Volume 53 (1986), Volume 107 (1988)
Year).

According to the present invention, the diffusion of impurities from the source / drain regions into the silicon region under the gate is limited by the separation of impurities between the silicon region under the gate and the silicide source / drain region. As a measure of this separation, a separation factor is used which is defined as the percentage of the concentration of impurities in two regions of 100 A width on each side of the boundary between silicide and silicon. For example, as in cobalt silicide and silicon, the separation factor between silicide and silicon is at least 5, so the difference in impurity concentration in silicide with respect to silicon is at least 5 to 1. Thus, the diffusion of impurities from the silicide 21 in FIG. 2 to the undoped region 22 under the gate 23 can be greatly reduced. (Because arsenic, unlike other impurities such as boron and phosphorus, moves along the grain boundaries of silicide, there is no advantage in isolation development.) This excellent effect is due to the implantation in the source / drain regions. Obtained only when silicide is formed before the temperature of the impurity reaches 900 ° C. or higher. For example, if the implanted impurity is already present during silicide formation,
Impurities diffuse from the region mainly composed of silicon to the silicon region below the gate. Since silicide is not formed when diffusion occurs, there is no effect of separation between silicide and silicon, and diffusion of impurities cannot be limited. In many cases, diffusion in a direction perpendicular to the substrate surface is not possible due to the presence of the dielectric region 25, so lateral diffusion into the silicon under the gate is not possible before the temperature reaches 900 ° C. If not formed, it will proceed further.

In general, the present invention improves the operation speed regardless of the device design method, but it is preferable to use the present invention when manufacturing a device having a design reel of 1 μm or less in which impurity diffusion under a gate becomes more critical. Such devices generally exhibit higher speed performance as the distance between the source and drain is reduced. However, such devices are also susceptible to leakage current between the source and drain due to impurity diffusion. Methods for manufacturing such devices include those described in U.S. patent application Ser. No. 07 / 209,149 (19).
(August 15, 1988) discloses that by forming silicide before heating to 900 ° C. or higher where diffusion occurs, the source-drain contact of an apparent junction device having a design rule of 1 μm or less is manufactured. Have been.

Essentially, the method, the silicide contacts is preformed in order to impurity concentration in the range from 10 ¹⁸ to 10 ²⁰ atmos / cm ^3, boron as p-type impurity, arsenic or phosphorus as N-type impurity inject. These silicide regions are
It has a design rule of 0.7 μm and generally has a depth of 2000 A or less, and is formed by depositing a metal such as cobalt in a thickness of 200 to 400 A on silicon in the source / drain regions. Prior to ion implantation, silicide formation generally ranges from 400 ° C. to 9 ° C. depending on the type of silicide.
This is achieved by heating to a temperature in the range of 00 ° C. For example, when cobalt is used, it is heated to a temperature in the range of 400 ° C to 600 ° C. Ion implantation with an ion acceleration voltage in the range of 10 to 50 keV and a dose in the range of 10 ¹⁴ to 10 ¹⁶ atoms / cm ² can achieve the impurity concentration and profile necessary to obtain the desired electrical characteristics as a high-speed device. To form Subsequent heating of the silicide region in the range of 750 ° C. to 900 ° C. provides an electrical source-drain contact without diffusing into the silicon region under the gate.

Although not essential, n-type and p-type wells, and symmetric CMOS technology (ie, n-channels that generate essentially equivalent (except for the opposite sign) threshold voltages in the n- and p-channels) CMOS devices with similar impurity concentrations in both devices and p-channel devices)
It is desirable to use technology. Such a symmetrical shape and its manufacture are described by SJ Hillenius et al.
"VLSI Science and Technology (VLSI Sci
ence and Technology), (CS Osburn)
Edited by JM and Andrews, Electrochemical Society (Electrochemical Societ)
y), New Jersey, Pennington (P
ennington) (1989)).
The use of a symmetrical shape is not essential, but its use can simultaneously improve the threshold voltage and avoid short channel effects.

 The following examples are illustrative of the processes involved in the present invention.

Example 1 A silicon wafer 4 inches in diameter and most of the surface was a (100) crystallographic plane was mounted on a sample holder of an Eaton Nova 100 mA oxygen injector. The substrate was preheated to 615 ° C. by radiant heating. The radiation source was then turned off and the temperature was maintained by the energy provided by the electron beam. Oxygen was implanted into the wafer using an acceleration voltage of 200 keV and a dose of 1.7 × 10 ¹⁸ cm ⁻² .

After the injection, the wafer was placed in a 1000 ml
10% solution containing 12.24 kg concentrated sulfuric acid in 0% hydrogen peroxide
Soak for another minute, then soak in deionized water heated to 70 ° C,
After spin-drying, washing was performed by immersing in a 100: 1 aqueous HF buffer solution for 1 minute. Clean the wafer
Inserted into a low-pressure chemical vapor deposition apparatus, 5500A silicon oxide was grown on the main surfaces on both sides of the wafer using 4ethylorthosilicate precursor gas under the conditions of 580 mTorr pressure and substrate temperature of 730 ° C. . Then, by rotating at 2000 rpm, the front side of the wafer is novolak (novola).
c) Covered with a 1 μm thick layer of photoresist. 7: 1
The oxide on the back side of the wafer was removed by immersing the wafer in a HF buffer solution (BOE) (buffered oxide etching). Thereafter, the photoresist was removed. Next, the wafer was placed in the sample holder of the low pressure chemical vapor deposition apparatus. Polysilicon, approximately 1 μm thick, was grown on both sides of the wafer by low pressure chemical vapor deposition under conditions where the substrate temperature was 630 ° C. and the pressure of the silane with the hydrogen carrier gas was 300 mTorr. The back side of the wafer was covered with a 24000 A thick layer of silicon oxide formed by plasma enhanced chemical vapor deposition. Thereafter, the polysilicon on the front side of the wafer was removed by immersing the wafer in an ethylenediamine / pyrocatechol solution for 5 minutes. As a result, a 0.5 μm thick oxide protective film was obtained on the injection front surface together with the backside polysilicon layer.

The wafer was inserted into a radiation furnace equipped with a tungsten halogen lamp. The wafer was adjusted so that heat radiation was likely to occur only on the back side. Set the temperature on the front side of the board to 20
The temperature was raised at a rate of ° C / sec and maintained at 1405 ° C for 30 minutes. Thereafter, the wafer was cooled at room temperature for 2 minutes. (This heating method is described in U.S. Pat. No. 4,676,841 (June 30, 1987).
Date). The front side oxide was removed by brushing, p-clean (filtered sulfuric acid) and etching at room temperature with 7: 1 BOE for 7 minutes. The completeness of the oxide removal was confirmed by a hydrophobicity test.

To thin the silicon film, a 1000 A thick oxide layer was grown at 1000 ° C. for 100 minutes in a mixture of 98% O ₂ and 2% HCl. The oxide thickness was measured at 1068A. Oxide was removed with 7: 1 BOE for 2 minutes.

The wafer was cleaned with brushing followed by p-clean. After inspecting the wafer in bright light, 100:
It was immersed in 1HF for 2 minutes for washing. The oxide was grown at 950 ° C. for 24 minutes in a mixture of O ₂ and HCl. An oxide having a thickness of 360 A was obtained.

The wafer was cleaned by etching at 100: 1 HF for 1 minute. Using a mixture of dichlorosilane and an ammonia precursor, the substrate temperature was set to about 750 ° C., and nitrogen silicon of about 1200 A was grown by low pressure chemical vapor deposition (LPCVD). The thickness of this nitride on two monitor wafers
It was measured as 1216A and 1223A. The wafer was cleaned again by brushing and etching in 100: 1 HF for 2 minutes. Then, in a tubular heating furnace at 900 ° C, 98
The nitride was oxidized by exposure to a mixture of% O ₂ and 2% HCl for 30 minutes.

Initially, a three-level resist was used to produce a given nitride. A 2.5 μm thick layer of Shipley 1822 resist was spun at 4000 rpm and baked at 250 ° C. for 600 seconds using a conveyor belt oven unit. Nitrogen carrier gas (150) sccm, SiH ₄ (66) s
ccm, using N ₂ O (1575 sccm) precursor, about 1200 A SiO 2
₂ was plasma grown. The plasma was injected into the precursor at a power of 475 watts under a gas pressure of 25 mTorr and a substrate temperature of about 200 ° C. The final thickness of the two layers is 1.7μ
m. An adhesion enhancer (hexamethyldisilizane gas) was used for the wafer. Then, a shiplay 1805 with a thickness of about 7000A was rotated at 4000 rpm and baked at 115 ° C. The resist is applied to the GCA optical exposure device, gate area, source area,
Exposure was performed for 0.7 second using a mask having a pattern for delineating the drain region. Thereafter, the resist was removed, and the line width was measured for lifting and inspected. The oxide was etched by a plasma etching method (HEX) for 5 minutes. The process was performed in a hexagonal etcher using a three-step reactive ion etching process. The first stage is 60mTorr of 80% CHF ₄ and 20% CO ₂
For about 5 minutes at a 450 V bias voltage in a mixture of The second stage is in the O _2, it was carried out for about 5 minutes at 600V bias. The third stage is 30-4 at 450V bias voltage in CO ₂
Performed for 0 minutes. The wafer was inspected and the sidewalls were removed by etching for 2 minutes in 30: 1 BOE.

The wafer was washed with 100: 1 HF for 30 seconds. High pressure oxidation, 8
At 50 ° C., 5000 A oxide was grown. After measuring the thickness of the oxide, it was immersed for 2 minutes in a BOE etching solution (etching rate: 250 A / min) diluted 10: 1 to reduce the thickness by 500 A.

Subsequently, the underlying nitride was etched in hot phosphoric acid for 30 minutes and then p-cleaned. A bird's beak is diluted 10: 1 with BOE (etching rate 250A / mi
Etching was performed by immersion in n) for 3 minutes. Then, 1
The oxides that are damaged 50A thick, grown 98% O ₂ and 38 minutes at 900 ° C. dry oxidation with a mixture of 2% HCl. Further oxidation / etchback was performed to further reduce the thickness of the silicon film to be compatible with device fabrication. First, 10
Perform an oxide etch for 10 minutes at 0: 1 BOE, followed by 98%
By dry oxidation at 900 ° C. using O ₂ and 2% HCl for 24 minutes,
A 150 A thick oxide layer was grown.

The wafer was exposed to hexamethyldisilane (HMDS) gas. A ship lay 1813 having a thickness of 1.2 μm was used at 5000 rpm. Exposure was performed through a mask to form a predetermined n-tub region using a GCA stepper. The resist was developed using a commercial developer.

P injection, 1 × 10 ¹² c with 55 keV, Extrion injector
A dose of m- ² was followed by an oxygen etch in an MTI plasma etcher using a power of 400 watts for 75 minutes. The resist was further removed using a p-strip (aqueous ammonium persulfate solution) for 20 minutes, inspected, and further p-cleaned.

Then, the wafer is exposed to HMDS gas, and then 1.2 μm
Shipley 1813 at 500 rpm. After baking at 115 ° C. for 45 minutes, optical lithography was performed on a GCA stepper with a mask to define the p-tub region. afterwards,
The resist was developed for 2.5 minutes, the line width was measured, inspected and baked at 120 ° C. Then, as a B implantation, an Extrion implanter was used at 30 keV energy at a dose of 1 × 10 ¹² cm ⁻² , and the process described for the p implantation was performed. The resist was etched in the p-strip for 20 minutes. The removal of the resist was inspected, and a p-clean was performed.

Thereafter, the implant was activated and injected by first washing for 7 minutes in 100: 1 BOE, followed by dry oxidation at 900 ° C. for 35 minutes in 100% O ₂ . The measured oxide was 175A.

The total thickness of the Si film consumed in the various oxidation steps was 1050A. This figure matched exactly with the final thickness measured by TEM. The rest of the process is equivalent to the bulk symmetric CMOS process disclosed by Hillenius et al. Above.

[Brief description of the drawings]

FIG. 1 is a diagram showing a dielectric insulating device having no silicide source and silicide drain, and FIG. 2 is a diagram showing a device including the present invention.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Stephen James Hillenias United States, 07901 New Jersey Summit, Colt Road 97 (72) Inventor Evit Kamgar United States, 07924 New Jersey Burnersville, Post Kanhat Road 200 (56) References JP-A-61-248476 (JP, A) JP-A-53-31983 (JP, A) JP-A-58-46633 (JP, A)

Claims (13)

(57) [Claims] (A) forming a gate region, a source region, and a drain region in an active region insulated by an insulating material on a substrate containing silicon; and (B) forming the source region and the drain region. Forming a silicide region therein; (C) implanting an impurity into the silicide region; and (D) diffusing the implanted impurity into the source region and the drain region, and in the silicon under the gate region. Heating the substrate having the source region and the drain region to a temperature that does not diffuse into the device. 2. The method according to claim 1, wherein said silicide region comprises cobalt silicide. 3. The method according to claim 2, wherein said insulating material is silicon dioxide. 4. The method according to claim 1, wherein said insulating material is silicon dioxide. 5. The method of claim 1, wherein said active region includes both an N-type region and a P-type region. 6. The method of claim 5, wherein said P-type region and said N-type region are implanted with impurities of opposite conductivity types at substantially equal concentrations. 7. The method of claim 1, wherein said substrate is formed by implanting oxygen into a silicon substrate and annealing said silicon substrate. 8. The conductive region having at least two active regions on a silicon substrate insulated from the substrate by an insulating region, wherein the active region includes a source region and a drain region separated by a conductive region. Wherein the source region and the drain region include a silicide region containing an impurity, and the conductive region is substantially free of the impurity. 9. The device according to claim 8, wherein said silicide region is cobalt silicide. 10. The device of claim 9, wherein said insulating region comprises silicon dioxide. 11. The device of claim 8, wherein said insulating region comprises silicon dioxide. 12. The device according to claim 8, comprising at least one N-type region and one P-type region. 13. The device of claim 12, wherein said p-type region and said n-type region are implanted with impurities of opposite conductivity types at substantially equal concentrations.