JPH0529240A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0529240A
JPH0529240A JP18284691A JP18284691A JPH0529240A JP H0529240 A JPH0529240 A JP H0529240A JP 18284691 A JP18284691 A JP 18284691A JP 18284691 A JP18284691 A JP 18284691A JP H0529240 A JPH0529240 A JP H0529240A
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
silicon substrate
semiconductor device
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18284691A
Other languages
Japanese (ja)
Inventor
Yasushi Torii
康司 鳥井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18284691A priority Critical patent/JPH0529240A/en
Publication of JPH0529240A publication Critical patent/JPH0529240A/en
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid the deterioration in electrical characteristics by a method wherein the direct thermal oxidation of a silicon substrate surface is avoided after finishing the ion implantation step for restraining the development of oxidation induced defect. CONSTITUTION:Boron ions are implanted in a silicon substrate 1 using a photoresist film 3 and a silicon oxide film 2 so as to form a P<+> region 4. Next, after the removal of the photoresist film 3, a silicon oxide film 2A is formed using ozone or oxygen plasma. Later, the whole body is annealed in an inert gas atmosphere so as to form a P well region 4A at specific depth.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にイオン注入に伴う結晶欠陥の低減方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of reducing crystal defects caused by ion implantation.

【0002】[0002]

【従来の技術】従来の半導体装置の製造方法の一例とし
て、CMOS構造のPウェル形成工程を図3を用いて説
明する。
2. Description of the Related Art As an example of a conventional method for manufacturing a semiconductor device, a P well forming step of a CMOS structure will be described with reference to FIG.

【0003】まず図3(a)に示すように、シリコン基
板1上に熱酸化法により厚さ500nm程度のシリコン
酸化膜2を形成する。次にこのシリコン酸化膜2上にフ
ォトレジスト膜3を塗布し、フォトリソグラフィー法に
よりPウェル形成領域のフォトレジスト膜3に開口部を
形成する。次でこのフォトレジスト膜3をマスクにして
Pウェル形成領域のシリコン酸化膜2をエッチング除去
し開口部を形成する。
First, as shown in FIG. 3A, a silicon oxide film 2 having a thickness of about 500 nm is formed on a silicon substrate 1 by a thermal oxidation method. Next, a photoresist film 3 is applied on this silicon oxide film 2, and an opening is formed in the photoresist film 3 in the P well forming region by photolithography. Next, using the photoresist film 3 as a mask, the silicon oxide film 2 in the P well forming region is removed by etching to form an opening.

【0004】次に図3(b)に示すように、Pウェルを
形成するためにボロンイオンを、フォトレジスト膜3及
びシリコン酸化膜2をマスクにしてイオン注入しP+
域4を形成する。
Next, as shown in FIG. 3B, boron ions are implanted to form a P well by using the photoresist film 3 and the silicon oxide film 2 as a mask to form a P + region 4.

【0005】次に図3(c)に示すように、フォトレジ
スト膜3を除去した後にP+ 領域を所定の深さに拡散さ
せるために、酸素を数パーセント含む不活性ガス雰囲気
中で高温(1000℃以上)でアニールを行い、Pウェ
ル領域4Aを形成する。
Next, as shown in FIG. 3 (c), in order to diffuse the P + region to a predetermined depth after removing the photoresist film 3, a high temperature ( Annealing is performed at 1000 ° C. or higher) to form the P well region 4A.

【0006】[0006]

【発明が解決しようとする課題】近年、半導体装置の集
積度が高くなるに連れて、例えばCMOS構造の半導体
装置の場合には、耐ラッチアップ性を高くするため、ウ
ェル領域の不純物濃度を高くする必要がある。そのため
ボロン等の不純物イオンのドーズ量が高くなり、イオン
注入に起因する結晶欠陥が問題となる。
In recent years, as the degree of integration of semiconductor devices has increased, in the case of a semiconductor device having a CMOS structure, for example, in order to improve the latch-up resistance, the impurity concentration in the well region is increased. There is a need to. Therefore, the dose amount of impurity ions such as boron is increased, and a crystal defect due to ion implantation becomes a problem.

【0007】従来の半導体装置の製造方法では、シリコ
ン基板に直接不純物のイオン注入を行い、その後に高温
でアニールを行っている。この時、完全な不活性ガス雰
囲気中でアニールを行うと、シリコン基板表面が荒れる
ために、微量の酸素を添加する方法が用いられている。
そのため、アニールの過程でシリコン基板表面は雰囲気
中の酸素により直接酸化されて、シリコン酸化膜が形成
される。この時シリコン酸化膜とシリコン基板の界面の
過剰のシリコンが、イオン注入により結晶欠陥の生じた
部位からシリコン基板内部へ供給され、格子間原子型の
酸素誘起欠陥が成長してしまう。この酸素誘起欠陥は、
半導体装置製造工程中の不純物(重金属イオン)を捕獲
し、キャリアの発生中心となりうるので、拡散層の逆方
向リーク電流の増加など半導体装置の特性劣化を引き起
こすという問題点があった。
In the conventional method of manufacturing a semiconductor device, impurity ions are directly implanted into a silicon substrate, and thereafter annealing is performed at a high temperature. At this time, if annealing is performed in a complete inert gas atmosphere, the surface of the silicon substrate becomes rough, so a method of adding a small amount of oxygen is used.
Therefore, in the process of annealing, the surface of the silicon substrate is directly oxidized by oxygen in the atmosphere to form a silicon oxide film. At this time, excess silicon at the interface between the silicon oxide film and the silicon substrate is supplied to the inside of the silicon substrate from the site where the crystal defects have been generated by the ion implantation, and oxygen interstitial oxygen-induced defects grow. This oxygen-induced defect is
Impurities (heavy metal ions) in the semiconductor device manufacturing process can be trapped and become carriers generation centers, so that there is a problem that characteristics of the semiconductor device are deteriorated such as increase of reverse leakage current of the diffusion layer.

【0008】又、酸素誘起欠陥を防止するために酸化膜
を介してイオン注入する方法も考えられるが、この場合
シリコン酸化膜中の酸素がシリコン基板中にノックオン
され、アニール工程を経ても除去されずにシリコン基板
中に転位を誘起して、半導体装置の特性劣化を引き起こ
すという問題点がある。
A method of implanting ions through an oxide film in order to prevent oxygen-induced defects is also conceivable. In this case, oxygen in the silicon oxide film is knocked on into the silicon substrate and removed even after an annealing step. However, there is a problem that dislocations are induced in the silicon substrate without causing deterioration of the characteristics of the semiconductor device.

【0009】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、シリコン基板上に第1のシリコン酸化膜を形
成したのちパターニングし開口部を形成する工程と、開
口部が形成された前記第1のシリコン酸化膜をマスクと
して前記シリコン基板に不純物をイオン注入しイオン注
入領域を形成する工程と、オゾンまたは酸素プラズマに
より前記イオン注入領域上に第2のシリコン酸化膜を形
成する工程とを含むものである。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first silicon oxide film on a silicon substrate and then patterning the same to form an opening, and the step of forming the opening. A step of ion-implanting impurities into the silicon substrate using the first silicon oxide film as a mask to form an ion-implanted region; and a step of forming a second silicon oxide film on the ion-implanted region by ozone or oxygen plasma. It includes.

【0010】[0010]

【実施例】次に本発明について図面を参照して説明す
る。図1(a)〜(d)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。図
2は本実施例による効果を示すグラフである。従来例と
異なる点は、イオン注入後のアニールの前にオゾンまた
は酸素プラズマによりシリコン酸化膜を形成している点
である。
The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. FIG. 2 is a graph showing the effect of this embodiment. The difference from the conventional example is that a silicon oxide film is formed by ozone or oxygen plasma before annealing after ion implantation.

【0011】先ず、図1(a)に示すように、シリコン
基板1上に熱酸化法により500nm程度のシリコン酸
化膜2を形成し、シリコン酸化膜2上にフォトレジスト
膜3を塗布して、フォトリソグラフィー法によりPウェ
ル形成領域に開口部を有するフォトレジスト膜3を形成
する。次にこのフォトレジスト膜3をマスクにしてPウ
ェル形成領域のシリコン酸化膜をエッチングし開口部5
を形成する。
First, as shown in FIG. 1A, a silicon oxide film 2 of about 500 nm is formed on a silicon substrate 1 by a thermal oxidation method, and a photoresist film 3 is applied on the silicon oxide film 2. A photoresist film 3 having an opening in the P well formation region is formed by photolithography. Next, using the photoresist film 3 as a mask, the silicon oxide film in the P well forming region is etched to form the opening 5
To form.

【0012】次に図1(b)に示すように、ボロンをフ
ォトレジスト膜3及びシリコン酸化膜2をマスクにし
て、Pウェル形成領域にイオン注入し、P+領域4を形
成する。
Next, as shown in FIG. 1B, boron is ion-implanted into the P well forming region using the photoresist film 3 and the silicon oxide film 2 as a mask to form a P + region 4.

【0013】次に図1(c)に示すように、フォトレジ
スト膜3を除去した後に、シリコン基板1をオゾン雰囲
気中に設置することによりシリコン基板1の表面を酸化
し、シリコン酸化膜2Aを形成する。この常温でのシリ
コン酸化膜2Aの膜厚は約3nmとする。尚、オゾンの
形成は酸素雰囲気に低圧水銀灯を点灯することにより行
う。
Next, as shown in FIG. 1C, after removing the photoresist film 3, the silicon substrate 1 is placed in an ozone atmosphere to oxidize the surface of the silicon substrate 1 to form a silicon oxide film 2A. Form. The film thickness of the silicon oxide film 2A at room temperature is about 3 nm. The ozone is formed by turning on a low pressure mercury lamp in an oxygen atmosphere.

【0014】次に図1(d)に示すように、P+ 領域4
を所定の深さに広げてPウェル領域4Aを形成すると共
に、イオン注入によりシリコン基板1の表層部に生じた
結晶欠陥を回復させるために完全な不活性ガス雰囲気中
で、例えば1000℃でアニールを行なう。
Next, as shown in FIG. 1D, the P + region 4
To a predetermined depth to form a P-well region 4A, and annealing at 1000 ° C., for example, in a complete inert gas atmosphere to recover crystal defects generated in the surface layer portion of the silicon substrate 1 by ion implantation. Do.

【0015】このように本実施例によれば、シリコン基
板を露出した状態でイオン注入を行なうとともに、イオ
ン注入工程の後に常温でシリコン酸化膜を形成し、その
後に完全な不活性ガス雰囲気中にて高温でアニールを行
うので、酸素のノックオンによる結晶欠陥の発生を防
ぎ、且つ高温で酸化性雰囲気に晒された場合に生じる過
剰シリコンに起因した酸素誘起欠陥の成長を防ぐことが
できる。よって半導体装置の製造工程中の不純物、特に
重金属イオンを素子活性領域にて捕獲することがなくな
り、半導体装置の拡散層の逆方向リーク電流が増大する
などの電気的特性の劣化を防止することができる。
As described above, according to the present embodiment, ion implantation is performed with the silicon substrate exposed, and a silicon oxide film is formed at room temperature after the ion implantation process, and thereafter, a complete inert gas atmosphere is formed. Since annealing is performed at a high temperature, it is possible to prevent the generation of crystal defects due to knock-on of oxygen, and to prevent the growth of oxygen-induced defects caused by excess silicon that occurs when exposed to an oxidizing atmosphere at a high temperature. Therefore, impurities, especially heavy metal ions, in the manufacturing process of the semiconductor device are not trapped in the element active region, and deterioration of electrical characteristics such as increase of reverse leakage current in the diffusion layer of the semiconductor device can be prevented. it can.

【0016】実施例及び従来例の拡散層リーク電流を図
2に示す。本実施例によれば、結晶欠陥を抑制できるた
め、キャリアの発生中心密度が減少し、拡散層の逆方向
リーク電流が著しく減少していることが分る。
FIG. 2 shows the diffusion layer leakage currents of the example and the conventional example. According to this example, it is found that the crystal defects can be suppressed, the carrier generation center density is reduced, and the reverse leakage current of the diffusion layer is significantly reduced.

【0017】上記実施例においてはオゾンによりシリコ
ン酸化膜を形成した場合について説明したが、酸素プラ
ズマを用いてもよい。この場合は、チャンバー内にシリ
コン基板1を設置して酸素プラズマを発生させ、シリコ
ン基板にプラズマ電位以下の正方向の電位を加えて活性
な帯電状態の酸素をシリコン基板上に集めて酸化膜を形
成する。尚、シリコン基板の温度は200℃程度とし、
形成するシリコン酸化膜2Aの膜厚はオゾンの場合と同
様に3nm程度とする。
In the above embodiment, the case where the silicon oxide film is formed by ozone has been described, but oxygen plasma may be used. In this case, the silicon substrate 1 is placed in the chamber to generate oxygen plasma, and a positive potential equal to or lower than the plasma potential is applied to the silicon substrate to collect active charged oxygen on the silicon substrate to form an oxide film. Form. The temperature of the silicon substrate is about 200 ° C,
The film thickness of the silicon oxide film 2A to be formed is about 3 nm as in the case of ozone.

【0018】酸素プラズマを用いる方法は、スループッ
トが高いことや既存のプラズマ処理装置を利用できると
いう利点を有する。
The method using oxygen plasma has the advantages of high throughput and the use of existing plasma processing equipment.

【0019】[0019]

【発明の効果】以上説明したように本発明は、シリコン
基板を露出した状態でイオン注入を行なうので、酸素の
ノックオンによる結晶欠陥の発生を防止することができ
る。またイオン注入工程の後にオゾンまたは酸素プラズ
マによりシリコン酸化膜を形成し、その後にアニールを
行うので過剰シリコンに起因する酸素誘起欠陥の成長を
抑制することができる。更に完全な不活性ガス雰囲気中
での高温アニールを行った場合でもシリコン基板の表面
の荒れを防止することができる。従って半導体装置の製
造工程中の不純物(重金属イオン)の捕獲に起因する半
導体装置の電気的特性の劣化を防止することができ、半
導体装置の製造歩留り及び信頼性を向上させることがで
きるという効果を有する。
As described above, according to the present invention, since the ion implantation is performed with the silicon substrate exposed, it is possible to prevent the generation of crystal defects due to the knock-on of oxygen. In addition, since a silicon oxide film is formed by ozone or oxygen plasma after the ion implantation step and annealing is performed thereafter, the growth of oxygen-induced defects due to excess silicon can be suppressed. Further, even when high temperature annealing is performed in a complete inert gas atmosphere, the surface of the silicon substrate can be prevented from being roughened. Therefore, it is possible to prevent the deterioration of the electrical characteristics of the semiconductor device due to the capture of impurities (heavy metal ions) during the manufacturing process of the semiconductor device, and it is possible to improve the manufacturing yield and reliability of the semiconductor device. Have.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するための半導体チッ
プの断面図。
FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

【図2】実施例及び従来例のリーク電流を示す図。FIG. 2 is a diagram showing leak currents of an example and a conventional example.

【図3】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。
FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2,2A シリコン酸化膜 3 フォトレジスト膜 4 P+ 領域 4A Pウェル領域 5 開口部1 Silicon Substrate 2, 2A Silicon Oxide Film 3 Photoresist Film 4 P + Region 4A P Well Region 5 Opening

Claims (1)

【特許請求の範囲】 【請求項1】 シリコン基板上に第1のシリコン酸化膜
を形成したのちパターニングし開孔部を形成する工程
と、開口部が形成された前記第1のシリコン酸化膜をマ
スクとして前記シリコン基板に不純物をイオン注入しイ
オン注入領域を形成する工程と、オゾンまたは酸素プラ
ズマにより前記イオン注入領域上に第2のシリコン酸化
膜を形成する工程とを含むことを特徴とする半導体装置
の製造方法。
Claim: What is claimed is: 1. A step of forming a first silicon oxide film on a silicon substrate and then patterning the first silicon oxide film to form an opening, and the step of forming the opening in which the first silicon oxide film is formed. A semiconductor including a step of ion-implanting impurities into the silicon substrate as a mask to form an ion-implanted region, and a step of forming a second silicon oxide film on the ion-implanted region by ozone or oxygen plasma. Device manufacturing method.
JP18284691A 1991-07-24 1991-07-24 Manufacture of semiconductor device Pending JPH0529240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18284691A JPH0529240A (en) 1991-07-24 1991-07-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18284691A JPH0529240A (en) 1991-07-24 1991-07-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0529240A true JPH0529240A (en) 1993-02-05

Family

ID=16125485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18284691A Pending JPH0529240A (en) 1991-07-24 1991-07-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0529240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013125904A (en) * 2011-12-15 2013-06-24 Shin Etsu Handotai Co Ltd Manufacturing method of epitaxial wafer with embedding region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013125904A (en) * 2011-12-15 2013-06-24 Shin Etsu Handotai Co Ltd Manufacturing method of epitaxial wafer with embedding region

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