JPH1187258A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of secondary defects due to high-energy ion implantation. SOLUTION: After resist has been applied and subjected to PEP (photolithographic etching process), ions are implanted into a semiconductor substrate by high-energy ion implantation of 300 keV or above, using the resist as a mask. Rapid thermal annealing(RTA) is carried out as the first thermal process after ion implantation and followed by furnace anneal(FA) at least once. The ion dosage is set at 1×10<13> atoms/cm<2> or above, and each annealing is carried out at a high temperature of 900 deg.C or above.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an annealing technique for suppressing secondary defects due to high-energy ion implantation.

[0002]

2. Description of the Related Art Conventionally, when an impurity layer is formed inside a semiconductor substrate, ions are diffused into the semiconductor substrate by an impurity diffusion method of diffusing impurities from the semiconductor layer or gas phase into the semiconductor substrate, or by accelerating energy of 100 to 200 keV. For example, a low energy ion implantation method for implanting ions.

In the low energy ion implantation method, heat treatment (annealing) is usually performed at a high temperature for a long time after the ion implantation in order to recover the damage of the crystal of the semiconductor substrate due to the ion implantation.

Here, when the low energy ion implantation method is used, crystal damage (marked by x) is formed on the surface of the semiconductor substrate 11 as shown in FIG. Therefore, as shown in FIG. 10, when the annealing is performed, the recovery from the crystal damage is
Since the ions progress from the inside of the semiconductor substrate 11 toward the surface, the excess interstitial atoms due to the ion implantation disappear to the surface sink, and finally, the crystal damage of the semiconductor substrate 11 is completely recovered.

On the other hand, in recent years, a high energy ion implantation method for implanting ions into a deep position inside a semiconductor substrate with an acceleration energy of 300 keV or more has been put to practical use. The high-energy ion implantation method has an advantage that an impurity layer can be formed at a deep position inside the semiconductor substrate while suppressing lateral diffusion, because ions can be implanted into a deep position inside the semiconductor substrate.

However, when the high-energy ion implantation method is used, as shown in FIG.
It is formed at a deep position inside the semiconductor substrate 11. Therefore, as shown in FIG. 12, when annealing is performed, the recovery of crystal damage proceeds from both the inside and the surface of the semiconductor substrate 11, and excess interstitial atoms due to ion implantation become Rod-like defects and secondary defects as dislocation loops eventually remain in the semiconductor substrate 11.

[0007] It is to be noted that secondary defects are more likely to occur particularly when the ion implantation dose is 1 × 10 ¹³ atoms / cm ² or more. Further, conventionally, for annealing after high energy ion implantation, FA (Furnace Anneal) having a high temperature and a long time of several minutes to several tens minutes has been used. When FA is used, a dislocation grows for a long time through a region where dislocations grow due to excess interstitial atoms, so that the dislocations grow sufficiently and a junction leak easily occurs.

[0008]

As described above, conventionally,
When ions are implanted into a deep position inside a semiconductor substrate with an acceleration energy of 300 keV or more, even if annealing is performed after the ion implantation, damage to the crystal of the semiconductor substrate is not sufficiently recovered, and a secondary defect remains. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to manufacture a semiconductor device capable of maximally suppressing generation of secondary defects in a semiconductor substrate during annealing after high-energy ion implantation. Is to provide a way.

[0010]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of implanting ions into a semiconductor substrate by an ion implantation method, and a first heat step after the ion implantation. Performing a rapid thermal anneal (RTA) and performing a furnace anneal (FA) at least once after the rapid thermal anneal (RTA).

Further, by using a high-energy ion implantation method using an acceleration energy of 300 keV or more, an impurity layer can be formed at a deep position in the semiconductor substrate. The ion dose in the ion implantation method is 1 × 10 ¹³ a
Even if it is set to be equal to or more than toms / cm ² , occurrence of secondary defects in the semiconductor substrate can be suppressed.

The rapid thermal annealing (RT)
A) and the furnace anneal (FA)
It is performed at a high temperature of 900 ° C. or more. The rapid thermal annealing (RTA) may be performed immediately after the ion implantation, or may be performed after several steps after the ion implantation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a process of forming an impurity layer, which is a main part of a method for manufacturing a semiconductor device according to the present invention.

According to the present invention, for example, after performing high-energy ion implantation using an acceleration energy of 300 keV or more, the first heat step is performed by RTA (Rapid Thermal Anion).
neal) and performing at least one FA (Furnace Anneal) after performing the RTA (steps ST5 to ST6).

That is, in the present invention, RTA is performed as a first step after ions are implanted into a deep position in a semiconductor substrate by ion implantation. RTA is several seconds to several tens of seconds, 9
A high-temperature short-time heat treatment (annealing) of at least 00 ° C.
Since the dislocations pass through the region where the dislocations grow due to the excess interstitial atoms in a short time, the excess interstitial atoms can be eliminated by an increase in the vacancy concentration due to thermal equilibrium. Thereafter, FA is executed as a second stage. FA is several minutes to several tens minutes, 90
This is a heat treatment (annealing) at a high temperature of 0 ° C. or higher for a long time, and recovers minute secondary defects formed after the first stage RTA.

According to the present invention, the recovery of crystal defects by ion implantation is performed by RTA, which is the first thermal process after ion implantation.
And subsequently, FAs performed continuously or at intervals. Therefore, generation of secondary defects in the semiconductor substrate can be suppressed, and a high-performance semiconductor element can be formed in a short process.

FIGS. 2 to 6 show a manufacturing method according to the embodiment of the present invention. First, as shown in FIG.
A semiconductor substrate (for example, a silicon substrate) 11 is prepared.
As the semiconductor substrate 11, for example, a P-type substrate having a plane orientation (100), a boron concentration of about 2.0 × 10 ¹⁵ atoms / cm ³ , and an oxygen concentration of about 1.5 × 10 ¹⁸ atoms / cm ³ is used. Next, thermal oxidation is performed to form a thermal oxide film (for example, a silicon oxide film) 12 having a thickness of about 100 nm on the semiconductor substrate 11.
To form

Next, as shown in FIG. 3, a resist 13 is applied on the thermal oxide film 12. Thereafter, PEP (photo etching step) is performed to provide an opening at a predetermined position of the resist 13. Next, as shown in FIG. 4, ions 14 are implanted using a resist 13 as a mask by high energy ion implantation to form an excess interstitial atomic layer 15 at a deep position in the semiconductor substrate 11. Here, the ion implantation is performed at 300 ke.
An acceleration energy of V or more (for example, about 400 keV) is used, ions are boron, and a dose is about 1 ×
10 ¹⁴ atoms / cm ² , and the implantation angle is about 7 °. Thereafter, the resist 13 is stripped.

Next, as shown in FIG. 5, RTA for suppressing and activating secondary defects is performed to form an impurity activation layer 16. The condition of RTA is, for example, a temperature of about 1050.
C., the time is about 20 seconds, and the temperature is raised at a rate of about 200.degree. C./sec in a nitrogen atmosphere. In this RTA, excess interstitial atoms pass through a region where dislocations grow due to excess interstitial atoms in a short time, and excess interstitial atoms disappear due to an increase in vacancy concentration due to thermal equilibrium.

Next, as shown in FIG. 6, FA is performed continuously or at intervals with the process shown in FIG.
7 is formed. The condition of the FA is, for example, a temperature of about 950.
C., the time is about 30 minutes, and the temperature is raised at a rate of about 8 ° C./min in a nitrogen atmosphere. Executing this FA makes it possible to recover minute secondary defects formed after the RTA.

According to the above-described manufacturing method, the recovery of crystal defects by ion implantation is performed by RTA, which is the first thermal process after ion implantation, and then by F or F which is performed continuously or at intervals.
A. Therefore, generation of secondary defects in the semiconductor substrate can be suppressed, and a high-performance semiconductor element can be formed in a short process.

FIG. 7 shows a first modification of the manufacturing method of FIG. This manufacturing method is characterized in that a PEP and an ion implantation process are repeatedly performed a plurality of times, an annealing process is performed after forming a plurality of excess interstitial atomic layers in a semiconductor substrate (steps ST1 to ST6).

Each excess interstitial atomic layer may contain ions of the same conductivity type or ions of different conductivity types. In addition, the annealing process is performed by RTA (Rapid) performed first after ion implantation.
Thermal Anneal) and FA (Furnace Anneal) performed at least once after RTA (steps ST5 to ST6).

Also in this modification, the recovery of crystal defects by ion implantation is performed by using R
This is realized by a TA and an FA that is performed continuously or at intervals thereafter. Therefore, generation of secondary defects in the semiconductor substrate can be suppressed, and a high-performance semiconductor element can be formed in a short process.

FIG. 8 shows a second modification of the manufacturing method of FIG. In this manufacturing method, after performing a PEP and an ion implantation process and forming an excess interstitial atomic layer in a semiconductor substrate, the RTA is not immediately performed, but is performed immediately after performing another process (excluding a thermal process). It is characterized in that it is performed (steps ST1 to ST6).

After the RTA, at least one FA is performed continuously to the RTA or after another process (steps ST5 to ST6). Also in this modification,
Recovery of crystal defects by ion implantation is realized by RTA, which is the first thermal step after ion implantation, and FA that is performed continuously or at intervals thereafter. Therefore, generation of secondary defects in the semiconductor substrate can be suppressed, and a high-performance semiconductor element can be formed in a short process.

[0027]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained. Recovery of crystal defects after performing high energy ion implantation,
RTA, the first thermal step after ion implantation, and then
This is realized by FAs performed continuously or at intervals. Therefore, generation of secondary defects in the semiconductor substrate can be suppressed, and a high-performance semiconductor element can be formed in a short process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part of a manufacturing method of the present invention.

FIG. 2 is a view showing one step of a manufacturing method according to the embodiment of the present invention.

FIG. 3 is a view showing one step of a manufacturing method according to the embodiment of the present invention.

FIG. 4 is a view showing one step of a manufacturing method according to the embodiment of the present invention.

FIG. 5 is a view showing one step of a manufacturing method according to the embodiment of the present invention.

FIG. 6 is a view showing one step of a manufacturing method according to the embodiment of the present invention.

FIG. 7 is a view showing a first modification of the manufacturing method of FIG. 1;

FIG. 8 is a view showing a second modification of the manufacturing method of FIG. 1;

FIG. 9 is a view showing one step of a conventional manufacturing method.

FIG. 10 is a view showing one step of a conventional manufacturing method.

FIG. 11 is a view showing one step of a conventional manufacturing method.

FIG. 12 is a view showing one step of a conventional manufacturing method.

[Explanation of symbols]

 11: semiconductor substrate, 12: thermal oxide film, 13: resist, 14: ion, 15: excess interstitial atomic layer, 16: impurity activation layer, 17: impurity layer.

Claims (5)

[Claims] 1. A step of implanting ions into a semiconductor substrate by an ion implantation method, a step of performing rapid thermal annealing as a first thermal step after the ion implantation, and at least one step after the rapid thermal annealing. Performing a multiple furnace anneal. 2. The method according to claim 1, wherein the ion implantation is a high energy ion implantation using an acceleration energy of 300 keV or more. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the dose of ions in said ion implantation method is 1 × 10 ¹³ atoms / cm ² or more. 4. The method according to claim 1, wherein the rapid thermal annealing and the furnace annealing are both performed at a high temperature of 900 ° C. or higher. 5. The rapid thermal anneal,
2. The method according to claim 1, wherein the method is performed immediately after the ion implantation.