JPH04328846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a buried layer having no surface defect by a method wherein after an impurity is ion-implanted in a substrate, the substrate is annealed in a non-oxidizing atmosphere and moreover, while the substrate is heated up, an ion-implanted region is expanded to form the buried layer and an epitaxial layer is grown. CONSTITUTION:An opening is formed in the surface, which is located over a region for forming a buried layer in a P-type substrate 1, of the substrate 1 to fonp a resist 2 on the surface and the opening, in which the resist 2 is not formed, is used as a window region W. An impurity is ion-implanted in the substrate 1 through the region W to fom an ion-implanted region, that is, a P<+> region 3, and after the resist 2 is removed, the substrate 1 is annealed in a non-oxidizing atmosphere. Morevoer, while the substrate 1 is heated up, the region 3 is expanded to form the P<+> buried layer 4 and while the layer 4 is formed, an epitaxial layer 5 is grown at a point of time when the region 3 does not reach the surface of the substrate 1. Thereby, with an auto-doping not generated in the substrate 1 surface, which is located over the region for forming the buried layer, the layer 4 having not a surface defect, can be formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by the step of forming a buried layer.

0002

[Prior Art] p+ in semiconductor devices such as semiconductor ICs
When performing up-down isolation, the buried layer is used not only from the surface of the epitaxial layer but also from the bottom of the epitaxial layer (
In other words, when re-diffusion is also performed upward (from the substrate side), shortening the isolation time suppresses the lateral expansion of the isolation (p-diffusion) region, reducing the chip area, and increasing the This is provided with the intention of improving withstand voltage by reducing the voltage.

Taking an npn type transistor as an example of a semiconductor device having a buried layer, the steps for manufacturing the buried layer in the method for manufacturing this transistor are as shown in FIGS. 5 to 8. First, in step 1 shown in FIG. 5, an oxide film mask 12 made of SiO2 is provided on a p-type substrate 11 made of silicon or the like so that the surface of the substrate 11 in a region where a buried layer is to be formed is exposed. Substrate 1 without mask 12
1 is defined as a window area W.

Next, in step 2 in FIG. 6, ions of boron (B) as a p-type impurity, for example, are implanted into the substrate 11 from the window region W to form an ion implantation region 13 in the substrate 11. In step 3 of FIG. 7, the entire substrate 11 is heated to a temperature of about 800 to 1300° C. in an oxidizing atmosphere such as dry oxygen or water vapor. As a result, the p-type impurity is diffused into the substrate 11, and a p+ diffusion region is formed below the window region W.
A region 14' is formed. During the diffusion, an SiO2 oxide film 15 is also formed in the window region W of the substrate 11.

At step 4 in FIG. 8, the SiO2 mask 12 and the SiO2 oxide film 15 are removed to expose the p+ region 14' in the window region W of the substrate 11, which is to be used as the p+ buried layer 14. Note that by removing the oxide film 15, a step 14a is generated in a portion of the p+ buried layer 14 corresponding to the peripheral portion of the window region W. The obtained semiconductor is subjected to the next step in order to complete it as an npn type transistor. For example, as shown in step 5 of FIG. 9, an epitaxial layer 16 is further grown on the surface of the substrate 11.

[0006]

According to the buried layer manufacturing process as described above, in order to form the buried layer 14, ion implantation is performed in step 2 of FIG. 6, and heat treatment is performed in step 3 of FIG. is being carried out. When ion implantation is performed in step 2, the surface of the window region W of the substrate 11 is severely damaged. While the surface is still damaged, heat treatment is performed in the next step 3 to form the p+ region 14', and the p+ region 14' is formed in step 4 of FIG.
When ' is the p+ buried layer 14, surface defects appear in the buried layer 14. This is undesirable because it causes structural defects in the transistor as a product.

Furthermore, what is most undesirable is that the diffusion reaches the surface of the substrate 1 during the heat treatment at step 3 in FIG.
Autodoping occurs during epitaxial growth. Therefore, in view of the above problems, the object of the present invention is to
To provide a method for manufacturing a semiconductor device that does not cause autodoping on the surface of a substrate, which is a region where a buried layer is to be formed, causes as little damage to the surface as possible, and can produce a buried layer free of surface defects.

[0008]

Means for Solving the Problems In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes opening a region on a substrate where a buried layer is to be formed, forming a resist on the surface, and forming a resist on the surface of the substrate. After ion-implanting impurities into the substrate and removing the resist, the substrate is annealed in a non-oxidizing atmosphere, and the impurity ion-implanted region is gradually heated to prevent the ion-implanted region from reaching the substrate surface. The method is characterized in that it includes a step of expanding a buried layer to form a buried layer, and then growing an epitaxial layer.

According to the manufacturing method of the present invention, in the step of manufacturing the buried layer, the ion implantation and heat treatment employed in the conventional manufacturing method are not combined, but annealing is performed in a non-oxidizing atmosphere after the ion implantation. Then, the impurity ion implantation region is expanded while the temperature is further increased, and when this expansion does not reach the substrate surface, a switch is made to epitaxial growth, and epitaxial growth is started. Therefore, there is little damage to the substrate surface, which is the region where the buried layer is to be formed, autodoping does not occur on the substrate surface, and no defects occur on the surface of the buried layer.

The impurity to be ion-implanted in the manufacturing method of the present invention is not particularly limited as long as the conductivity type is p type since a p+ buried layer is formed, and boron (B) and aluminum (Al) are exemplified. Ru. Further, by annealing performed after ion implantation, the implanted impurity ions are activated and diffused at the same time, and the p+ region, which is the ion implantation region, expands to a certain extent. Since this diffusion is performed in a non-oxidizing atmosphere, oxidation (formation of oxide film 15 in FIG. 7) that occurs in conventional manufacturing methods does not occur. The gas used as the atmosphere during annealing is not particularly limited as long as it is non-oxidizing. For example, there are H2 gas, N2 gas, Ar gas, and He gas.

After the annealing, the p+ region diffused by the annealing is further expanded. This extension is based on the temperature (
This is done by gradually raising the temperature of the substrate to about 1000°C. However, it is important to extend the p+ region so that it does not reach the substrate surface. In other words, it is sufficient to activate the implanted ions to the extent that they enter the lattice points. Then, when the expansion is completed, epitaxial growth is started to grow epitaxial crystals on the substrate.

In the manufacturing method of the present invention, the steps after the step of manufacturing the buried layer may be the same manufacturing process as the conventional manufacturing process, and the semiconductor provided with the buried layer is manufactured as a semiconductor device using the conventional manufacturing process. Finalize.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be explained below based on examples. In this embodiment, in order to clarify the difference between the present invention and the prior art by comparing it with the manufacturing method disclosed in the prior art, an npn type transistor will be described as an example as in the prior art.

FIGS. 1 to 4 show the manufacturing process (steps 1 to 4) of the buried layer. First, as shown in step 1 of Figure 1,
On a p-type substrate 1 made of silicon or the like, a region where a p+ buried layer is to be formed is opened and the surface is covered with a resist 2. The opening in the substrate 1 on which the resist 2 is not provided is defined as a window region W. Note that an SiO2 film may be provided on the substrate 1, and in reality, a SiO2 film of about 1000 Å is present on the substrate 1. Damage can be further reduced by the SiO2 film.

Next, in step 2 shown in FIG. 2, boron (B) as a p-type impurity is ion-implanted into the substrate 1 from the window region W, and an ion-implanted region (p+ region) 3 is formed in the substrate 1.
form. Then, in step 3 of FIG. 3, the resist 2 is removed. Here, before proceeding to the next step 4, the substrate 1 is chemically cleaned and then placed in an epitaxial growth furnace. Note that if an SiO2 film is present, it is removed by etching.

Thereafter, in step 4 of FIG. 4, the oxygen present in the growth reactor is first purged with N2 gas to remove oxygen. Next, H2 gas is introduced into the growth furnace, the N2 gas in the furnace is exhausted, and the N2 gas is replaced with H2 gas.
2 Replace all (100%) with gas. As a result, the growth furnace is filled with H2 gas to prepare a non-oxidizing atmosphere. In this H2 gas atmosphere, the substrate 1 is annealed to activate and simultaneously diffuse boron ions. In this diffusion, boron ions only need to be activated, and p
+ The spread of region 3 does not have to be large. After sufficiently activating boron ions, annealing is completed.

After annealing, the temperature inside the growth furnace is gradually raised to a temperature (approximately 1000° C.) at which epitaxial growth to be performed after the buried layer is formed, so that the p+ region 3 in the substrate 1 forms a window region W on the surface of the substrate 1. The p+ region 3 is further expanded, taking care not to reach the p+ buried layer 4. At the point when the p+ region 3 does not reach the window region W on the surface of the substrate 1, the temperature at which epitaxial crystals are precipitated (1000°C
After the temperature is further increased to (above), an epitaxial layer 5 is grown on the substrate 1. Note that before epitaxial growth, H
By flowing Cl gas into the growth furnace, the surface of the substrate 1 is made extremely thin (1
It is more preferable to perform etching (approximately 0.000 Å) and cleaning. However, it is important to prevent p+ region 3 from appearing on the surface of substrate 1 by etching.

The semiconductor provided with the p+ buried layer 4 in this manner is further processed into an npn layer using a normal semiconductor manufacturing process.
It is sufficient to complete it as a type transistor. In the above embodiments, an npn transistor is used as a semiconductor device, but it goes without saying that the manufacturing method of the present invention is not limited to this, and can be applied to any semiconductor device having a buried layer. be able to. Further, in the above embodiment, a p-type substrate is used, but an n-type substrate can be used in the same manner, and the effect is comparable to that of a p-type substrate.

Furthermore, the manufacturing method of the present invention includes an n-type impurity (
It can also be applied to an n+ buried layer made of As or Sb). In this case, high energy ion implantation or double charge method may be used for implantation.

[0020]

As explained above, in the method for manufacturing a semiconductor device of the present invention, after implanting impurity ions in the step of forming the buried layer, annealing is performed in a non-oxidizing atmosphere, and the temperature is gradually increased. While expanding the ion implantation region to form a buried layer, the process switches to epitaxial growth when the ion implantation region does not reach the substrate surface.
The following effects are achieved compared to conventional manufacturing methods that involve ion implantation and heat treatment. (1) After ion implantation, OSF (Oxide in
This method does not cause crystal defects such as reduced stacking faults. (2) Since the implanted impurity does not appear on the substrate surface at the time of starting epitaxial growth, autodoping does not occur, and the impurity profile of epitaxial growth can be controlled with high precision. (3) There is little damage to the window region on the substrate surface, which is the region where the buried layer is to be formed, and a buried layer without surface defects can be produced. (4) The manufacturing process of the buried layer can be simplified.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining step 1 of the buried layer manufacturing process in the manufacturing method of the present invention.

FIG. 2 is a diagram for explaining step 2 of the buried layer manufacturing process in the manufacturing method of the present invention.

FIG. 3 is a diagram for explaining step 3 of the buried layer manufacturing process in the manufacturing method of the present invention.

FIG. 4 is a diagram for explaining step 4 of the buried layer manufacturing process in the manufacturing method of the present invention.

FIG. 5 is a diagram for explaining step 1 of a buried layer manufacturing process in a conventional manufacturing method.

FIG. 6 is a diagram for explaining step 2 of a buried layer manufacturing process in a conventional manufacturing method.

FIG. 7 is a diagram for explaining step 3 of a buried layer manufacturing process in a conventional manufacturing method.

FIG. 8 is a diagram for explaining step 4 of a buried layer manufacturing process in a conventional manufacturing method.

FIG. 9 is a diagram for explaining step 5 of the next step in the conventional buried layer manufacturing process.

[Explanation of symbols]

1 p-type substrate 2 Resist 3 Ion implantation region (p+ region) 4 p+ buried layer 5 Epitaxial layer

Claims (1)

[Claims] 1. A region where a buried layer is to be formed is opened on a substrate, a resist is formed on the surface, impurity ions are implanted into the opening, the resist is removed, and then the substrate is opened in a non-oxidizing atmosphere. The method includes the steps of annealing, gradually increasing the temperature of the substrate, expanding the impurity ion implantation region so that the ion implantation region does not reach the substrate surface to form a buried layer, and then growing an epitaxial layer. A method for manufacturing a featured semiconductor device.