JPH0729845A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To provide an impurity diffusion method being employed in the fabrication of semiconductor device in which a diffusion layer having suppressed residual defect can be obtained without conducting low dose implantation while ensuring a required dosage. CONSTITUTION:A single crystal Si substrate 1 is processed as follows. 1. As<+> ions are implanted with a dosage of 3X10<15>cm<-2> at an injection energy of 40keV to form an amorphous layer 2. 2). Furnace annealing is then conducted for 30min at 850 deg.C to recrystallize the amorphous layer 2. 3). As+ ions are implanted again with a dosage of 3X10<15>cm<-2> at an injection energy of 40keV to form an amorphous layer 3. 4). Furnace annealing is conducted for 60min at 900 deg.C for the purpose of activation. Some residual defects 4, unobservable by means of a transmission electron microscope, are generated at a depth of about 0.07mum from the surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor impurity diffusion process technology.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, ion implantation has become the mainstream in recent years for forming impurity diffusion regions. When the semiconductor substrate is ion-implanted, it is uniformly amorphized from the substrate surface to a depth determined by the implantation conditions. This amorphization serves to suppress channeling at the time of implantation to form a shallow implantation impurity distribution, is easily recrystallized at the time of heat treatment, and has an effect of increasing the activation rate.

However, a large number of minute defects are generated in the substrate region directly below the amorphous layer. This defective region is difficult to recover and forms a dislocation loop after heat treatment. This is a so-called residual defect near the A / C interface.

This region is less likely to disappear even if a heat treatment is applied, as compared with other defect regions, for example, those generated near the projected range (Rp) during implantation. In addition, among the defects caused by the injection, the defects are generated in the deepest part of the substrate, and the leakage current is generated near the junction position.

Conventionally, since heat treatment was possible at a relatively high temperature,
This residual defect does not occur so much, and even if it occurs, the junction position becomes deeper than the defect position due to impurity diffusion, and it did not lead to the generation of leak current.

However, in the future, as the degree of integration becomes higher, the process temperature will be lowered in order to prevent heat diffusion. In this case, the residual defects at the A / C interface are more prominently generated, and since the junction position is shallower, the defect generation position approaches the defect generation position. Due to the effects of both of these, the junction leakage current increases so much that it cannot be ignored. In order to obtain a shallow junction, this measure has no choice but to suppress the generation of defects, but there is no decisive means therefor, and low-temperature long-time annealing is considered. However, even in this case, impurity diffusion occurs, and it is considered difficult to form a shallow junction.

[0007]

SUMMARY OF THE INVENTION The present invention reduces the amount of residual defects generated by low temperature heat treatment and shifts the generation position to the substrate surface side away from the bonding position. It is intended to suppress the occurrence of.

As described in the above section [Prior Art],
Regarding the influence of the residual defects caused by the A / C interface on the leak current, the amount and position of the generation thereof become a problem. here,
Consider activation of the As ⁺ implant layer. Since the radius of As atoms is close to that of Si and there are no impurities such as F that prevent recrystallization at the time of BF ₂ ⁺ implantation, the amount of residual defects generated after activation is small. However, since the As atoms are extremely heavy with a mass number of 75, they are amorphized at the time of implantation to a deeper region. This means that the residual defects due to the A / C interface will occur at a deeper position, that is, at a position closer to the junction position, which causes an increase in leak current.

On the contrary, in the case of BF ₂ ⁺ implantation, the amorphous layer is not as thick as in As ⁺ implantation, and the junction position and the defect position are less accessible than the As ⁺ implantation layer. However, the amount of defects itself is larger than the amount of As ⁺ implantation, which also leads to an increase in leak current. From the above, it is understood that in order to suppress the leak current, it is necessary to suppress the defect generation amount and also make the generation position shallow.

The defect generation amount is most dependent on the activation condition, but when it is constant, it is controlled by the implantation dose amount. That is, as the dose amount is smaller, the implantation damage is smaller, the generation of micro defects is also reduced, and the density of residual defects is finally lowered.

As an example, an As ⁺ implantation layer is formed with a concentration of 6 × 10 ¹⁵ c.
When the morphology of the layer activated by being implanted with m ⁻² , 3 × 10 ¹⁵ cm ⁻² was examined by a TEM photograph, it was found that the dislocation loop 31 was generated at a dose of 6 × 10 ¹⁵ cm ⁻² . On the other hand, it was found that dislocation loops did not occur at a dose of 3 × 10 ¹⁵ cm ^-2 .

Regarding the position, the amorphous layer thickness is the generation position depth, which is determined by the implantation conditions. The implantation energy has a great effect, but the dose dependence is also recognized. FIG. 4 shows the results of F distribution obtained by SIMS analysis when BF ₂ ⁺ was injected at different doses.

In this figure, the arrow indicates the position of the A / C interface, which has two peaks at an injection dose of 1 × 10 ¹⁵ cm ⁻² and 3 × 10 ¹⁵ cm ⁻² and 5 × 10 ¹⁴ cm ⁻² . Although one peak is generated at the time of dose, the former second peak and the latter peak show segregation of F to A / C interface defects. That is, it can be seen that the position where this peak occurs is the position where the residual defect occurs, but it shifts to a shallower direction as the dose is lowered. That is, the thickness of the amorphous layer becomes thin due to the low dose, and as a result, the defect occurrence position moves to the surface side.

From the above, the decrease of the implantation dose is caused by A / C.
It can be seen that it is effective in reducing the generation amount of residual defects near the interface and shifting the generation position to the surface side (that is, separating from the bonding position). However, the implantation dose is an important factor that determines the resistance value of the diffusion layer, and cannot be lowered more than necessary by the usual method.

The present invention is intended to solve this problem and to obtain the same effect as in the case of performing low dose implantation while securing the required dose amount.

[0016]

According to the present invention, when a diffusion region is formed by ion implantation, a required dose amount is not continuously implanted, but is interrupted once when a certain dose amount is implanted, It is characterized in that the substrate is recrystallized by applying a heat treatment, and then the implantation is restarted again.

When the implantation is further applied to the region where the substrate is made amorphous, the thickness of the amorphous layer is increased and the minute defects are also increased. This is the case in the case of high dose implantation, and the above-mentioned problems occur. However, if the amorphous substrate is heat-treated once to be single-crystallized and then the implantation is continued, the subsequent implantation damage is consumed again for the substrate amorphization from the surface. Therefore, from the point of view of the final implantation damage, the amount of the subsequent implantation can be almost ignored. That is, the impurity ions to be actually implanted have high dose implantation, but the implantation damage can be suppressed to the level of low dose implantation.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the implantation dose is suppressed once, the substrate is monocrystallized by the subsequent heat treatment, and the implantation is performed several times to obtain the required dose. It is a thing. The heat treatment here is performed to recrystallize the substrate by solid-phase growth, and activation of implanted impurities is not intended. On the contrary, since diffusion causes a problem due to heat treatment, low temperature treatment of 850 ° C. or lower for As ⁺ implantation layer and 800 ° C. or lower for BF ₂ ⁺ implantation layer suppresses diffusion. Then, after completing the implantation of the required implantation dose, a heat treatment for activation is applied.

A method of manufacturing a semiconductor device according to a second aspect of the invention is characterized in that the number of times of implantation division is two and the implantation conditions of both implantations are the same. In the case of a normal diffusion layer formation, especially an N ⁺ layer, a sufficient effect can be obtained if the dose amount is halved by dividing into two times. Making the injection conditions the same is
This has the effect of increasing the throughput by unifying the injection processing recipes. Further, in order to make the depth of defect layer formation shallowest,
It is best to make both implant doses the same. here,
The implantation dose per injection is set to be equal to or more than the critical amount of substrate amorphization, because it is recrystallized at a low temperature and the residual defects generated thereby are suppressed as much as possible. Further, even when the heat treatment for activation is finally applied, the activation rate becomes higher when it is made amorphous.

The method of manufacturing a semiconductor device according to a third aspect is characterized in that the implantation energy is changed by two times of implantation, but this makes the total implantation profile have two peaks, and the activation energy is 1 after activation. The purpose is to obtain a more uniform profile than the conditional implantation. This contributes to lowering the resistance of the diffusion layer. When the low energy implantation is performed first and the high energy implantation is performed thereafter, the defect region generated in the first implantation is included in the amorphous region generated in the second implantation and disappears. That is, it becomes possible to further reduce the final residual defects.

The method of manufacturing a semiconductor device according to a fourth aspect is an example in which the present invention is applied to an actual semiconductor device.

[0022]

EXAMPLES Examples of the manufacturing method described in claims 2 and 3 and comparative examples by the conventional method will be described below with reference to the drawings.

Example 1 [Claim 2, FIG. 1 (a) to (d)]
Implanted As ⁺ references] monocrystalline Si substrate 1 energy 40ke
Implantation is performed with V and an implantation dose amount of 3 × 10 ¹⁵ cm ⁻² . As a result, it is amorphized to a region of about 0.07 μm from the surface, and the amorphous layer 2 is formed [FIG.
(A)].

A furnace body annealing treatment is performed at 850 ° C. for 30 minutes. The amorphous layer 2 is recrystallized. [Fig. 1
(B)].

Injection energy of As ⁺ is again 40 ke
Implantation is performed with V and an implantation dose amount of 3 × 10 ¹⁵ cm ⁻² . Amorphization is performed again to the same depth to form the amorphous layer 3. [FIG. 1 (c)].

The furnace body is annealed at 900 ° C. for 60 minutes for activation. At a depth of about 0.07 μm from the surface, some crystal defects, that is, residual defects 4 which are difficult to observe by a transmission electron microscope observation occur (FIG. 1 (d)).

Comparative Example 1 [See FIGS. 2 (a) and 2 (b)] A diffusion layer having the same impurity distribution as in Example 1 is manufactured by the following procedure.

As ⁺ is implanted into the single crystal Si substrate 11 at an implantation energy of 40 keV and an implantation dose amount of 6 × 10 ¹⁵ cm ^-2 . As a result, the region of about 0.08 μm from the surface is amorphized to form the amorphous layer 12 [FIG. 2 (a)].

The furnace body is annealed at 900 ° C. for 60 minutes for activation. Crystal defects (dislocation loops), that is, residual defects 13 occur at a depth of about 0.08 μm from the surface [FIG. 2 (b)].

Comparing the diffusion layer produced by the method according to claim 2 (FIG. 1) and the conventional method (FIG. 2), the conventional method produces more residual defects in a deeper region.

Embodiment 2 [Claim 3, FIG. 3 (a) to (d)]
Implanted As ⁺ into the reference] single-crystal Si substrate 21 energy 30k
Implantation is performed with eV and an implantation dose amount of 3 × 10 ¹⁵ cm ⁻² . As a result, it is amorphized to a region of about 0.06 μm from the surface, and an amorphous layer 22 is formed [FIG.
(A)].

A furnace body annealing treatment is performed at 850 ° C. for 30 minutes. The amorphized layer is recrystallized [Fig. 3
(B)].

Injection energy of As ⁺ is again 40 ke
Implantation is performed with V and an implantation dose amount of 3 × 10 ¹⁵ cm ⁻² . As a result, it is amorphized to a depth of about 0.07 μm from the surface, and an amorphous layer 23 is formed [FIG.
(C)].

The furnace body is annealed at 900 ° C. for 60 minutes for activation [FIG. 3 (d)].

Through the above process, it is possible to obtain a diffusion layer which is shallower than that in the method according to the second aspect and has few residual defects 24.

[0036]

As is apparent from the above description, according to the present invention, when the diffusion region is formed by the ion implantation, the required dose amount is not continuously implanted, but when a certain dose amount is implanted. It is characterized by interrupting once, applying heat treatment to recrystallize the substrate, and then restarting implantation again.
The following effects can be achieved. Claim 1
By applying the above process, it is possible to obtain a diffusion layer with few residual defects while ensuring a sufficient impurity concentration. If the process of claim 2 is applied, complication of the process can be suppressed to a minimum and the effect of the process of claim 1 can be obtained. If the process of claim 3 is applied, in addition to the effect of the process of claim 1, a diffusion layer having a uniform distribution and a low sheet resistance can be obtained. By applying the method of claim 4, it is possible to obtain a semiconductor device having a low resistance and a shallow source / drain region with few residual defects. The present invention can be effectively applied to the manufacture of MOS transistors.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a semiconductor device manufacturing process according to a first embodiment of the present invention, which is a sectional view of a substrate.

FIG. 2 is an explanatory diagram of a semiconductor device manufacturing process in Comparative Example 1 according to a conventional method, and is a sectional view of a substrate.

FIG. 3 is an explanatory diagram of a semiconductor device manufacturing process according to the second embodiment of the present invention, which is a sectional view of a substrate.

FIG. 4 is a graph showing results obtained by SIMS analysis of F distribution when BF ₂ ⁺ is injected into a semiconductor substrate at different dose amounts.

[Explanation of symbols]

 1,11,21 Single crystal Si substrate 2,3,12,22,23 Amorphous layer 4,13,24 Residual defect 31 Dislocation loop

Claims (4)

[Claims] 1. In a semiconductor device manufacturing process, when an impurity diffusion region is formed by ion implantation, the implanted impurities do not diffuse after the ion implantation at a low temperature (85 at As ⁺⁾ .
0 ° C or less, BF ₂ ⁺ 800 ° C or less)
Repeating the step of heat treatment performed injected again, after implanting an impurity to a concentration necessary, heat treatment for activation (As ⁺ at 900 ° C. or higher, BF ₂ ⁺ at 850 ° C. or higher), characterized in that the addition of Manufacturing method of semiconductor device. 2. In the semiconductor device manufacturing process, when the impurity diffusion region is formed by ion implantation, the implantation is performed twice under the same conditions (the implantation dose amount is equal to or more than the amorphization critical dose amount: As ⁺² . × 10 ¹⁴ cm
^-2 , 5 × 10 ¹⁴ cm ^{-2 for} BF ₂ ⁺ ) and low temperature (850 ° C. or less for As ⁺ , where diffusion of impurities does not occur between both implants)
A method of manufacturing a semiconductor device, which comprises subjecting a substrate to recrystallization by applying a heat treatment at BF ₂ ⁺ at 800 ° C. or lower). 3. In a semiconductor device manufacturing process, when the impurity diffusion region is formed by ion implantation, the implantation is carried out in two steps with different energies (the implantation dose amount is equal to or more than the amorphization critical dose amount: As ⁺² . × 10
¹⁴ cm ^-2, BF ₂ ⁺ at 5 × 10 ¹⁴ cm ^-2), and both injection diffusion of the impurity does not occur between the low temperature (As ⁺ at 850 ° C.
Hereinafter, a method for manufacturing a semiconductor device is characterized in that the substrate is recrystallized by performing heat treatment at BF ₂ ⁺ at 800 ° C. or lower. 4. A method of manufacturing a semiconductor device, wherein the manufacturing method of claim 1 is applied to source / drain formation.