JPH03201535A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an effect on the characteristics of a device of a secondary defect such as a dislocation easy to be formed after annealing when the deep impurity distribution of a collector, etc., is formed through ion implantation, by forming a gettering layer, which does not contribute to conduction, at a position deeper than an impurity layer on viewing from the surface of a silicon semiconductor substrate. CONSTITUTION:An oxide film 2 is formed onto a silicon substrate 1, and a polyimide 3 and an amorphous silicon 4 are deposited as a mask for implanting ions. An N-well forming region is bored, P<+> ions are implanted in dosage of 1X10<14>cm<-2> by 1MeV energy, an N well 5 is shaped, Ar ions are implanted in 1X10<15>cm<-2> by 5MeV, and a gettering layer 6 as a defect is formed. The gettering layer at that time is formed in an approximately 1mum region before and after a projection range. The spread of the region is increased with the augmentation of dosage. When annealing for thirty min at 1000 deg.C is conducted after the mask for implantation is removed, phosphorus is activated, and a secondary defect is gettered to the Ar implanting layer 6, thus shaping the N well 5 containing no secondary defect.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention aims to prevent junction leakage that deteriorates device characteristics when impurities are introduced from the surface into deep regions by ion implantation in the manufacture of semiconductor devices. The present invention relates to a semiconductor device and a method for manufacturing the same that prevents the occurrence of secondary defects that may cause such defects.

(Prior art) In order to form a collector layer of a bipolar transistor, a well in OMO3, etc., a deep impurity distribution is formed by so-called high-energy ion implantation, in which ions with an energy of several 100 keV to several MeV are implanted into a semiconductor substrate. A method is proposed.

(Problems to be Solved by the Invention) In the above method, if the implanted impurity is introduced so deep that it is embedded from the substrate surface, secondary defects such as dislocations are likely to be formed after annealing. If these defects are formed in the device active region near the surface or in the well-substrate PN junction, junction leakage will occur and device characteristics will deteriorate.

At present, there is no effective means to prevent such a situation, so the current situation is to suppress the occurrence of defects by reducing the amount of impurity implanted.

However, if the amount of impurity implanted is limited, it is not possible to form a layer with lower resistance, and there is a drawback that it is not possible to respond to higher functionality of devices.

The present invention was proposed to improve the above-mentioned drawbacks, and its purpose is to form deep impurity distributions such as wells or collectors by ion implantation in the manufacture of semiconductor devices such as CMO3 and bipolar transistors. Another object of the present invention is to provide a method for preventing secondary defects such as dislocations that are likely to be formed after annealing from affecting the characteristics of a device.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a device in which a P or N type layer is formed on a silicon semiconductor substrate using an impurity that determines the conductivity type. The gist of the invention is a semiconductor device characterized in that a gettering layer that does not contribute to conduction is formed at a position deeper than the impurity layer when viewed from the surface of the semiconductor device.

Furthermore, in the case of ion implantation into a silicon semiconductor substrate, when an impurity that determines the conductivity type is introduced into a deep position buried from the surface of the semiconductor substrate to form a P or N type layer, at least The gist of the invention is a method for manufacturing a semiconductor device, which is characterized in that an element that does not contribute to conduction or an element that forms a layer of the opposite conductivity type is ion-implanted from the surface of a semiconductor substrate at a position deeper than the projected range and then heat-treated. It is something to do.

(Function) The main feature of the present invention is that after ion implantation of an impurity that determines the conductivity type, an element such as argon is further ion-implanted to a position deeper than the impurity that determines the conductivity type, and heat treatment is performed. Therefore, the present invention can suppress the occurrence of defects that affect device characteristics without depending on the amount of impurity implanted that determines the conductivity type. In other words, the damaged region formed by elements such as argon implanted deep into the
Annealing has the effect of gettering defects and making the device active region defect-free.

(Example) Next, an example of the present invention will be described. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

In Figure 1, according to the conventional method, for example, phosphorus ion (P゛)
was injected with I XIO"c+n-" at I MeV and
The impurity distribution and defect distribution when annealed at 0° C. for 30 minutes are shown. At this time, defects are introduced throughout the injection layer.

FIG. 2 shows that, in accordance with the present invention, after implanting P" ions at I MeV and I XIO" cm, argon ions were further implanted at I X 10" cm at 5 MeV.
The impurity distribution and defect distribution when annealed at ℃ for 30 minutes are shown.

At this time, the entire P° ion-implanted layer is made defect-free, and junction leakage of devices formed in this layer can be reduced.

Curve 1 is P4 ion I MeV+ I Xl0I4
For cIl-', curve 2 is Ar'' ion 5 MeV
, l x 10"cm-" is shown.

Only P''' ions are converted to I MeV at l XIO"c++-
``The injected sample and P° ions (I MeV, l
In addition to X10"c+w-"), a sample in which argon (Ar") ions were implanted at 4.5 MeV for 5 The table below shows the results of investigating the depth distribution of etch pits. It can be seen that the device region is made defect-free by the Ar'' implantation.

Table Next, an example in which the present invention is applied to the formation of an N well of CMO3 is shown below along with FIG.

(a) After forming an oxide film 2 on a silicon substrate 1, 7n of polyimide 3 is deposited as a mask for ion implantation. Furthermore, 500 layers of amorphous silicon 4 are deposited to prevent charge-up. (Fig. 3a) (b) Open the N-well formation region. (Figure 3b)
(C) P'' ion with energy IMeV (projected range).

The N-well 5 is formed by implanting the N-well 5 with a dose of IXIO"cm-" (approximately In). (Fig. 3C) (d) Ar (argon) ions are implanted at 5 MeV (projected range 3.5n) to form a defective gettering layer 6. At this time, the gettering layer is , is formed in a region approximately IIrm before and after the projected range.The spread of this region increases as the dose increases.(Fig. 3d) (e) After removing the implantation mask, 1000"C for 130 minutes This activates phosphorus (P), and the secondary defects are replaced by Ar implanted N
N-well 5 that is gettered to 6 and does not contain secondary defects
is formed. (FIG. 3e) The present invention can also be applied in a similar manner to the formation of N-type deep conduction layers, for example the formation of the collector layer of NPN bipolar transistors. Further, by using boron (B) instead of phosphorus (P), it can be applied to the formation of a P-type deep conductive layer such as the formation of a P well of CMO3 or the collector layer of a PNP bipolar transistor.

Further, the process configuration is not limited to the process described here. Further, instead of the ^r ions, an element that does not contribute to conduction, such as fluorine, silicon, or germanium, may be implanted.

In addition, when B' ions are implanted with high energy into the surface side, P' ions are substituted for Ar' etc. ions at a deeper position.
``Ions may be implanted.

(Effects of the Invention) The present invention is similar to soft soil in ion implantation into a silicon semiconductor substrate, by introducing impurities that determine the conductivity type into a deep position buried from the surface of the semiconductor substrate to form a P or N type layer. In the case of formation, at least an element that does not contribute to conduction is added at a position deeper than the projected range of the impurity.
Alternatively, if the present invention is applied to forming a Pl or N well of CMO3 or a collector of a bipolar transistor by ion-implanting an element forming a layer of the opposite conductivity type from the surface of the semiconductor substrate and heat-treating it, junction leakage can be reduced. It is possible to realize a high-performance device with reduced energy consumption.

[Brief explanation of drawings]

FIG. 1 shows the impurity distribution and defect distribution of the conventional method, FIG. 2 shows the impurity distribution and defect distribution of the present invention, and FIG. 3 shows the manufacturing method according to the present invention. l...Silicon substrate 2...Oxide film 3...Polyimide 4...Amorphous silicon 5...N well 6...Gettering layer Figure 1 Depth 3 [JJml Diagram 2] S (j-+mJ Fig. 3 5 3・-・ Imide 4- Oucrystalline Sicon 5--・ N'7 Conyl 6--・ Kentarinkun Soda

Claims (2)

[Claims] (1) In a device in which a P or N type layer is formed on a silicon semiconductor substrate using an impurity that determines the conduction type, a conduction layer is formed at a position deeper than the impurity layer when viewed from the surface of the silicon semiconductor substrate. A semiconductor device characterized in that a gettering layer that does not contribute is formed. (2) In ion implantation into a silicon semiconductor substrate, when a P or N type layer is formed by introducing an impurity that determines the conductivity type into a deep position buried from the surface of the semiconductor substrate, at least the projection of the impurity is 1. A method of manufacturing a semiconductor device, comprising ion-implanting an element that does not contribute to conduction or an element that forms a layer of the opposite conductivity type from the surface of a semiconductor substrate at a deeper position than the surface of the semiconductor substrate, followed by heat treatment.