KR0151990B1 - Formation method of gattering layer in silicon substrate - Google Patents
Formation method of gattering layer in silicon substrate Download PDFInfo
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- KR0151990B1 KR0151990B1 KR1019940038975A KR19940038975A KR0151990B1 KR 0151990 B1 KR0151990 B1 KR 0151990B1 KR 1019940038975 A KR1019940038975 A KR 1019940038975A KR 19940038975 A KR19940038975 A KR 19940038975A KR 0151990 B1 KR0151990 B1 KR 0151990B1
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 16
- 239000010703 silicon Substances 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000012535 impurity Substances 0.000 claims abstract description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 229910052786 argon Inorganic materials 0.000 claims abstract description 17
- 238000005247 gettering Methods 0.000 claims abstract description 16
- -1 argon ions Chemical class 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000001133 acceleration Effects 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 25
- 238000010438 heat treatment Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000003917 TEM image Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
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Abstract
반도체소자의 제조에 있어서, 실리콘 기판에 불순물 이온근처에 근접 게터링 층을 형성하는 방법이 제공된다. 이 방법은 실리콘기판에 SiO2산화막을 형성하고 불순물등이 주입될 이온주입 부위를 에칭으로 제거한 후, 불순물을 주입하기전에 그 불순물의 비정거리보다 수배이상 깊은 곳에 점결함층이 형성되도록 결함회복이 늦은 아르곤이온을 임계 도우즈량 미만으로 주입하므로써 근접 게터링층을 형성하고, 이 근접게터링층에 의해 불순물에 의해 형성된 점결함을 흡수하여 접합층의 전기적 특성을 개선시킨다.In the manufacture of a semiconductor device, a method of forming a near gettering layer near an impurity ion in a silicon substrate is provided. This method forms a SiO 2 oxide film on a silicon substrate, removes the ion implantation site where impurities are to be implanted, and then recovers the defects late so that a point defect layer is formed several times deeper than the specific distance of the impurities before implanting the impurities. By injecting argon ions below the critical dose amount, a proximity gettering layer is formed, which absorbs point defects formed by impurities, thereby improving the electrical properties of the bonding layer.
Description
제1도(a)내지(c)는 본 발명에 의한 방법을 실시하기 위한 공정의 일예를 단계적으로 나타낸 공정개략도.1 (a) to (c) are process schematic diagrams showing an example of a process for carrying out the method according to the present invention step by step.
제2도는 본발명의 방법에 따라 제조된 기판의 깊이에 따른 면저항 분포와, 도우즈량이 보다 많은 경우에 형성된 결함층의 단면 투과 전자 현미경 사진이다.2 is a cross-sectional transmission electron micrograph of a defect layer formed according to the depth of a substrate manufactured according to the method of the present invention, and a defect layer formed when the dose is larger.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : SiO2산화막1: silicon substrate 2: SiO 2 oxide film
3 : 이온주입 부위 4 : 아르곤 이온3: ion implantation site 4: argon ion
5 : 아르곤 이온주입에 의해 형성된 점결함층 6 : 불순물 이온(붕소)5: point defect layer formed by argon ion implantation 6: impurity ions (boron)
7 : 불순물 이온에 의한 접합영역 8 : 근접 게터링층7: junction region by impurity ions 8: proximity gettering layer
본발명은 반도체 소자의 제조방법에 관한 것이며, 보다 상세히는 반도체 소자 제조시 불순물이온이 분포한 위치와 근접한 위치에 게터링(getteriong)층을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a getterion layer at a position close to a position where impurity ions are distributed in manufacturing a semiconductor device.
최근 반도체소자의 고집적화에 따라 기판표면근처에 분포된 금속불순물을 제거하고, 불순물이온의 주입에 따라 형성된 결함 등을 제거함으로써 불순물이온이 주입된 영역의 전기적 특성을 개선시키고자 하는 노력이 계속되고 있다.In recent years, efforts have been made to improve the electrical characteristics of regions implanted with impurity ions by removing metal impurities distributed near the surface of the substrate and removing defects formed by implantation of impurity ions due to high integration of semiconductor devices. .
이같은 노력의 일환으로 종래에는 기판뒷면에 폴리실리콘층을 형성하거나 기판상에 세라믹입자 등을 분사시켜 기판내에 금속불순물을 제거하기 위한 게터링 방법이 사용되어 왔으나, 이는 불순물(dopant)이온의 주입에 따라 형성된 결함은 제거하지 못하는 문제점을 갖고 있는 것이다.As part of such efforts, a gettering method has been conventionally used to remove metal impurities in a substrate by forming a polysilicon layer on the back surface of the substrate or by spraying ceramic particles on the substrate, which is used for implanting dopant ions. The defect thus formed has a problem that cannot be removed.
이외에도 고에너지로 기판내에 실리콘 이온 등을 주입하여 근접 게터리층을 형성하는 방법이 사용되기도 하였으나 이때 결함층이 너무 크거나 혹은 쉽게 소멸되어 게터링 층으로서의 역할을 제대로 수행하지 못하는 문제점이 있는 것이다.In addition, a method of forming a proximity battery layer by injecting silicon ions or the like into a substrate at high energy has been used, but there is a problem in that the defect layer is too large or easily extinguished, thereby failing to properly function as a gettering layer.
이에 본 발명의 목적은 상기와 같은 종래의 문제점을 해결한 보다 개선된 게터링층 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a more improved gettering layer forming method that solves the conventional problems as described above.
나아가 본 발명의 목적은 기판내에 아르곤이온을 고에너지로 임계농도미만으로 주입하여 적정깊이에 점결함층을 형성한 후 불순물이온을 주입함으로써, 기판의 표면근방에서는 높은 면 저항값을 나타내고, 어느 정도의 깊이에서는 많은 점결함들이 기판내부에 분포하고 있어서, 깊이 조정으로 근접 게터링층으로서의 역할을 충분히 할 수 있는 게터링층 형성방법을 제공하고자 하는데 있다.Furthermore, an object of the present invention is to inject a high concentration of argon ions into the substrate below a critical concentration to form a point defect layer at an appropriate depth, and then to implant impurity ions, thereby exhibiting high sheet resistance in the vicinity of the surface of the substrate. In the depth, many point defects are distributed in the substrate, and to provide a method of forming a gettering layer which can sufficiently serve as a proximity gettering layer by adjusting the depth.
본 발명에 의하면, 실리콘 기판상에 SiO2산화막을 형성한 후, 이온이 주입되는 부위를 에칭하는 단계;According to the present invention, after forming a SiO 2 oxide film on a silicon substrate, etching the portion implanted with ions;
상기 이온주입부위를 통해 고에너지 아르곤(Ar)이온을 1X1015/cm2미만의 도우즈량으로 주입하여 점 결함층을 형성하는 단계;Implanting a high energy argon (Ar) ion at a dose of less than 1 × 10 15 / cm 2 through the ion implantation site to form a point defect layer;
상기 이온주입 부위를 통해 기판내에 불순물(dopant)을 주입하는 단계; 및 질소 분위기하에서 고온으로 급속 열처리하는 단계; 를 포함하는 실리콘기판내 근접 게터링층 형성방법이 제공된다.Implanting dopants into the substrate through the ion implantation site; And rapid heat treatment at high temperature in a nitrogen atmosphere. A method of forming a proximity gettering layer in a silicon substrate is provided.
이하 본 발명에 대하여 상세히 설명한다.Hereinafter, the present invention will be described in detail.
통상 반도체소자 제조시에는 실리콘 기판의 표면에 SiO2산화막을 형성한 후, 이온 주입부위를 에칭하고 그 이온 주입부위를 통해 불순물(dopant)를 주입하여 기판에 확산시키게 된다.In general, in manufacturing a semiconductor device, after forming a SiO 2 oxide film on a surface of a silicon substrate, an ion implantation site is etched, and a dopant is implanted through the ion implantation site to diffuse the substrate.
이 불순물은 반도체 소자의 필요한 전기적 성질을 얻기 위하여 의도적으로 주입하는 것이나 이 불순물에 의해 형성된 점결함은 반도체 소자의 전기적특성에 나쁜 영향을 미치므로 본 발명에서는 불순물 이온 분포 근접위치에 게터링층을 형성함으로써 불순물에 의해 형성된 점결함을 흡수하여 반도체 소자의 전기적 특성을 향상시키고자 하는 것이다.This impurity is intentionally implanted to obtain the required electrical properties of the semiconductor device, but the point defects formed by this impurity adversely affect the electrical properties of the semiconductor device. It is intended to improve electrical characteristics of semiconductor devices by absorbing point defects formed by impurities.
본 발명의 방법에 의하면, 실리콘 기판에 통상의 방법으로 SiO2산화막을 형성한 후 불순물이 주입되는 부위를 에칭제거 하고, 이어서 이 불순물 주입부위를 통해 불순물을 주입하기 전에 불순물의 비정거리보다 수배이상 깊은 위치에 점결함층이 형성되도록 1MeV이상의 고에너지로 아르곤 이온을 도우즈량 1X1015/cm2미만으로 이온 주입하는 단계를 포함한다.According to the method of the present invention, after forming a SiO 2 oxide film on a silicon substrate in a conventional manner, the portion where the impurity is implanted is etched away, and then several times more than the specific distance of the impurity before implanting the impurity through the impurity implantation site. And implanting argon ions at a dose of less than 1 × 10 15 / cm 2 with a high energy of 1 MeV or more to form a point defect layer at a deep position.
이같이 주입된 아르곤 이온에 의해 형성된 점결함층은 이후에 주입되는 불순물에 의해 형성된 점결함을 흡수하는 근접 게터링층을 형성하므로서 전기적 특성을 좋게하는데 크게 기여하게 된다.The point defect layer formed by the implanted argon ions thus contributes to the improvement of the electrical properties by forming a proximity gettering layer that absorbs the point defects formed by the implanted impurities.
이때 아르곤 이온의 사용은 다른 이온에 비하여 결함회복이 늦어 이에 의해 형성된 근접 게터링층이 쉽게 소멸되지 않는 장점이 있는 것이다.At this time, the use of argon ions has the advantage that the defect recovery is slow compared to other ions so that the proximity gettering layer formed thereon is not easily extinguished.
본 발명의 발명에 사용될 수 있는 아르곤 이온은 주입에너지에서 점결합층을 형성할 수 있는 정도의 양으로 주입하는 것이 바람직하다.Argon ions that can be used in the present invention is preferably implanted in an amount sufficient to form a point bonding layer in the implantation energy.
본 발명의 방법에서 실리콘 기판에의 SiO2산화막형성, 불순물이 주입되는 부위의 에칭 제거 및 불순물이나 아르곤이온의 주입은 이 분야에서 공지된 어떠한 방법이라도 이용가능한 것이며, 본 발명의 열처리 역시 램프 가열법 등을 포함하여 이 분야에서 공지된 방법을 이용할 수 있다.In the method of the present invention, the formation of SiO 2 oxide film on the silicon substrate, the etching removal of the site where the impurity is implanted, and the implantation of the impurity or argon ion can be used by any method known in the art. Methods known in the art can be used, including the like.
이하, 본 발명의 실시예를 첨부도면을 참조하여 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[실시예]EXAMPLE
본 실시예에서는 p-형 실리콘 기판을 사용하였으나, 이는 결코 본발명의 범위를 한정하는 것이 아니며, 본 발명은 n-형 실리콘기판에도 적용가능한 것이다.In this embodiment, a p-type silicon substrate is used, but this is by no means limited to the scope of the present invention, the present invention is also applicable to n-type silicon substrate.
[발명예]Invention
제1도는 본 발명의 방법을 실시하기 위한 공정의 일예를 개략적으로 나타낸 것이다. 제1도(a)에 도시한 바와 같이 p형 실리콘 기판(1) SiO2산화막(2)을 형성한 후 불순물 주입부위를 에칭으로 제거하여 이온주입 부위(3)을 형성하였다. 이후 상기 이온주입부위(3)를 통해 가속전압 1MeV에서 아르곤 이온(4)을 이온 임프랜테이션(ion implantation)법을 사용하여 주입하였으며, 이때 도우즈량은 1X1014/cm2였다.(제1도(b)참조)1 schematically shows an example of a process for carrying out the method of the invention. As shown in FIG. 1A, after forming the p-type silicon substrate 1 SiO 2 oxide film 2, the impurity implantation site was removed by etching to form the ion implantation site 3. Subsequently, argon ions 4 were implanted using the ion implantation method at an acceleration voltage of 1MeV through the ion implantation site 3, wherein the dose was 1 × 10 14 / cm 2 . (b) see)
제1도(b)에서(5)는 아르곤이온 주입에 의해 형성된 점결함층을 나타낸다. 그 후 제1도(c)에서와 같이, 불순물이온 붕소(B)(6)을 주입하는바, 이 역시 이온 임프랜테이션법에 의하였다.(B) in FIG. 5 shows a point-defect layer formed by argon ion implantation. Thereafter, as shown in FIG. 1 (c), impurity ion boron (B) 6 was implanted, which was also based on the ion implantation method.
불순물이온 주입이 끝난 실리콘 기판을 램프가열 방식에 의한 금속열처리 장치로 질소 분위기하에서 1100℃의 온도에서 10초간 열처리 하였으며, 제1도 (c)는 열처리후 기판내에 접합영역(7)과 근접 게터링층(8)이 형성된 것을 보여준다.After the impurity ion implantation, the silicon substrate was heat treated for 10 seconds at a temperature of 1100 ° C. under a nitrogen atmosphere by a metal heat treatment apparatus using a lamp heating method. It shows that layer 8 is formed.
[비교예][Comparative Example]
상기 발명예에서와 같은 절차에 따라 접합영역을 형성하되, 아르곤 이온을 가속전압 1MeV에서 도우즈량 1X1015/cm2으로 주입한후 1100℃에서 램프 가열 방식에 의해 열처리를 하였다. 이 역시 이온 임프렌테이션법에 의하였다.A junction region was formed according to the same procedure as in the above example, but after argon ions were implanted at an acceleration voltage of 1 MeV at a dose of 1 × 10 15 / cm 2 , heat treatment was performed at 1100 ° C. by lamp heating. This was also based on the ion implantation method.
상기 발명예에서 얻은 점결함층이 형성된 기판에 대한 면 저항 분포를 구하고, 발명예에서 얻은 기판 및 비교예에서 얻은 기판을 투과전자현미경 관찰하였다. 이때 본 발명의 방법으로 얻은 기판(A)에서는 단면투과 전자현미경 관찰에서 결함이 관찰되지 않았다. 그러나 제2도에 의하면 많은 점결함들이 기판내부에 분포하고 있어서 깊이 조정에 의해 근접게터링층으로서의 역할을 충분히 할수 있음을 알 수 있다.The surface resistance distribution of the board | substrate with which the point defect layer obtained by the said invention example was formed was calculated | required, and the board | substrate obtained by the invention example and the board | substrate obtained by the comparative example were observed with the transmission electron microscope. At this time, no defect was observed in the cross-sectional transmission electron microscope observation in the substrate A obtained by the method of the present invention. However, it can be seen from FIG. 2 that many point defects are distributed in the substrate, and thus, the depth can be sufficiently served as a proximity gettering layer.
이는 비교예의 방법으로 얻은 기판(B)내부에 너무 많은 결함이 관찰되어서 표면쪽으로 분해되어 전기적으로 특성이 나쁘게 되는 것과 같은 기능성을 배제하고 근접 게터링층을 형성할 수 있도록 개선이 이루어짐을 알 수 있다. 또한, 고농도의 아르곤 이온주입에 의해 형성된 시료 B는 많은 전위환등이 관찰되나 본 발명에서는 관찰되지 않고, 면저항 분포도로부터 많은 안정된 점결함층이 존재하는 게터링층을 얻을 수 있는 것이다.It can be seen that the improvement can be made to form a near gettering layer without the functionality such that too many defects are observed inside the substrate B obtained by the method of the comparative example and decomposed toward the surface, thereby resulting in poor electrical properties. . In addition, although many dislocation rings and the like are observed in Sample B formed by the high concentration of argon ion implantation, it is not observed in the present invention, and a gettering layer in which many stable point-defect layers are present from the sheet resistance distribution chart can be obtained.
상기한 바와같이, 본 발명의 방법에 의하면, 기판내에 아르곤이온을 고에너지로 임계농도미만인 저농도로 이온주입하여 적정깊이에 점결함층을 형성하여 게터링층을 형성함으로써, 기판의 표면근방에서는 높은 면 저항값을 갖게하고 어느 정도의 깊이에서는 많은 점결함들이 기판내부에 분포하도록하여 불순물 주입으로 형성된 점결함을 흡수하여 반도체소자의 전기적 특성을 개선시킬 수 있는 것이다.As described above, according to the method of the present invention, argon ions are implanted into the substrate at low concentrations with high energy and less than the critical concentration to form a point defect layer at an appropriate depth to form a gettering layer, thereby providing a high surface near the surface of the substrate. It has a resistance value, and at a certain depth, many point defects are distributed inside the substrate to absorb the point defects formed by impurity injection, thereby improving the electrical characteristics of the semiconductor device.
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| KR1019940038975A KR0151990B1 (en) | 1994-12-29 | 1994-12-29 | Formation method of gattering layer in silicon substrate |
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| KR1019940038975A KR0151990B1 (en) | 1994-12-29 | 1994-12-29 | Formation method of gattering layer in silicon substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980030411A (en) * | 1996-10-29 | 1998-07-25 | 김영환 | Method of forming a protective film of a semiconductor device |
| KR100727262B1 (en) * | 2006-08-30 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Method of forming metal in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980030411A (en) * | 1996-10-29 | 1998-07-25 | 김영환 | Method of forming a protective film of a semiconductor device |
| KR100727262B1 (en) * | 2006-08-30 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Method of forming metal in semiconductor device |
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| KR960026414A (en) | 1996-07-22 |
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