KR960012288A - Wafer for semiconductor device manufacturing and its manufacturing method - Google Patents

Wafer for semiconductor device manufacturing and its manufacturing method Download PDF

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Publication number
KR960012288A
KR960012288A KR1019940022550A KR19940022550A KR960012288A KR 960012288 A KR960012288 A KR 960012288A KR 1019940022550 A KR1019940022550 A KR 1019940022550A KR 19940022550 A KR19940022550 A KR 19940022550A KR 960012288 A KR960012288 A KR 960012288A
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South Korea
Prior art keywords
wafer
manufacturing
gas
semiconductor device
heat treatment
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KR1019940022550A
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Korean (ko)
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조병진
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김주용
현대전자산업 주식회사
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Priority to KR1019940022550A priority Critical patent/KR960012288A/en
Publication of KR960012288A publication Critical patent/KR960012288A/en

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Abstract

본 발명은 반도체 소자 제조용 웨이퍼 및 그 제작방법에 관한 것으로, 웨이퍼 내부에 존재하는 금속성 불순물 또는 결정결함을 제거하며 인(P)에 의한 반응로의 튜브 오염을 방지하기 위하여 웨이퍼 후면의 소정깊이에 버리드 형태(Buried Type)의 산화층(Oxide Layer)을 형성하고 고 에너지(High Energy)에 의한 이온주입(Implantation)공정을 실시하여 상기 산화층 보다 깊게 인-도프영역(P-doped region)을 형성한 다음 열처리(Annealing)하므로써 무결점의 웨이퍼를 제작하여 소자의 수율을 향상시킬 수 있도록 한 반도체 소자 제조용 웨이퍼 및 그 제작방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer for manufacturing a semiconductor device and a method of fabricating the same, and removes metallic impurities or crystal defects present in the wafer, and discards it at a predetermined depth on the back surface of the wafer to prevent tube contamination of the reactor by phosphorus (P). A buried type oxide layer is formed, and an ion implantation process is performed by high energy to form a P-doped region deeper than the oxide layer. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer for manufacturing a semiconductor device and a method of manufacturing the same, which are capable of improving the yield of a device by fabricating a defect-free wafer by annealing.

Description

반도체 소자 제조용 웨이퍼 및 그 제작방법Wafer for semiconductor device manufacturing and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A 내지 제1E도는 본 발명에 따른 반도체 소자 제조용 웨이퍼의 제작방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method for manufacturing a wafer for manufacturing a semiconductor device according to the present invention.

Claims (8)

반도체 소자 제조용 웨이퍼에 있어서, 웨이퍼의 후면으로부터 소정깊이에 버리드 형태의 산화층이 형성되며, 게터링을 위한 열처리 공정시 웨이퍼내에 존재하는 결정결함등이 포획도록 상기 산화층보다 깊게 인-도프 영역이 형성된 것을 특징으로 하는 반도체 소자 제조용 웨이퍼.In a wafer for manufacturing a semiconductor device, a buried oxide layer is formed at a predetermined depth from a rear surface of the wafer, and an in-doped region is formed deeper than the oxide layer so as to capture crystal defects, etc. present in the wafer during a heat treatment process for gettering. Wafer for manufacturing a semiconductor device, characterized in that. 반도체 소자 제조용 웨이퍼의 제작방법에 있어서, 웨이퍼 후면에 산소이온을 주입한 후 1 열처리 공정을 실시하여 상기 웨이퍼 후면의 소정깊이에 산화층을 형성시키는 단계와 상기 단계로부터 인(P)이온을 주입하여 상기 산화층보다 깊게 인-도프 영역을 형성시키는 단계와, 상기 단계로부터 웨이퍼 내부에 존재하는 금속성 불순물 또는 결정결함을 상기 인-도프 영역으로 확산시켜 포획되도록 2차 열처리 공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.In the method of manufacturing a wafer for manufacturing a semiconductor device, injecting oxygen ions on the back surface of the wafer and then performing a heat treatment process to form an oxide layer at a predetermined depth on the back surface of the wafer and injecting phosphorus (P) ions from the step Forming a phosphorus-doped region deeper than an oxide layer, and performing a secondary heat treatment process to diffuse metallic impurities or crystal defects present in the wafer into the phosphorus-doped region and to capture them. A method of manufacturing a wafer for manufacturing a semiconductor device. 제2항에 있어서, 상기 산소이온 주입시 이온주입량은 1×1017내지 1×1018이온/㎤이며, 이온주입에너지는 50 내지 250KeV인 것을 특징으로 하는 반도체 제조용 웨이퍼의 제작방법.The method of claim 2, wherein the ion implantation amount is 1 × 10 17 to 1 × 10 18 ions / cm 3, and the ion implantation energy is 50 to 250 KeV. 제2항에 있어서, 상기 1차 열처리공정은 1200 내지 1300℃ 온도 및 소정의 가스 분위기하에서 5 내지 8시간 실시되는 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.The method of claim 2, wherein the first heat treatment is performed for 5 to 8 hours at a temperature of 1200 to 1300 ° C. and a predetermined gas atmosphere. 제4항에 있어서, 상기 1차 열처리 공정시 분위기 가스는 N2가스 또는 Ar 가스에 O2가스가 소정비율로 혼합된 가스된 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.The method of claim 4, wherein the atmosphere gas is a gas in which an O 2 gas is mixed with N 2 gas or Ar gas in a predetermined ratio during the first heat treatment process. 제5항에 있어서, 상기 O2가스는 N2가스 또는 Ar 가스에 1 내지 3%정도 혼합된 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.The method of claim 5, wherein the O 2 gas is mixed with N 2 gas or Ar gas by about 1 to 3%. 제2항에 있어서, 상기 인(P)-이온 주입시 이온주입량은 1×1014내지 1×1016이온/㎤이며, 이온주입에너지는 50 내지 2MeV인 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.The method of claim 2, wherein the ion implantation amount during implantation of phosphorus (P) ions is 1 × 10 14 to 1 × 10 16 ions / cm 3, and the ion implantation energy is 50 to 2MeV. Way. 제2항에 있어서, 상기 2차 열처리 공정을 900 내지 1000℃ 온도 및 N2가스 분위기하에서 1 내지 2시간동안 실시되는 것을 특징으로 하는 반도체 소자 제조용 웨이퍼의 제작방법.The method of claim 2, wherein the secondary heat treatment process is performed at 900 to 1000 ° C. and N 2 gas atmosphere for 1 to 2 hours. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940022550A 1994-09-08 1994-09-08 Wafer for semiconductor device manufacturing and its manufacturing method KR960012288A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030032448A (en) * 2001-10-18 2003-04-26 주식회사 실트론 A Single Crystal Silicon Wafer having a gettering means and a Method for making thereof
KR100423754B1 (en) * 2001-12-03 2004-03-22 주식회사 실트론 A method for high temperature heating of silicon wafer
KR20040031877A (en) * 2002-10-07 2004-04-14 한종휘 tunnel vision system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030032448A (en) * 2001-10-18 2003-04-26 주식회사 실트론 A Single Crystal Silicon Wafer having a gettering means and a Method for making thereof
KR100423754B1 (en) * 2001-12-03 2004-03-22 주식회사 실트론 A method for high temperature heating of silicon wafer
KR20040031877A (en) * 2002-10-07 2004-04-14 한종휘 tunnel vision system

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