TW521351B - Fabrication method of semiconductor device with low resistivity/ultra-shallow junction - Google Patents

Abstract

This invention provides a fabrication method of semiconductor device with low resistivity/ultra-shallow junction, which is characterized in: after implantation on the LDD region is carried out, performing an annealing treatment in a gas atmosphere containing NO, N2O or NH3 to drive in the implanted ions. The RTN process can improve the activation rate of the doped ions and concurrently reduce the transient enhance diffusion (TED) phenomenon during annealing treatment.

Description

521351

Page 4 V. Description of the invention (2) A problem to be solved urgently. To understand the background of Ming and Ming, the following will cooperate with the illustration in Figure 3 and the production process of the / n source / drain region (LDD) where the defect is located. First, please come to Japan to make a circle, 1 2 to define the ^ area. 'Even on the substrate 10, an isolation oxide is formed to form an n? 2 on the surface of the element area, and then a square product (cvfD ^ S 14 is thermally oxidized, and a conductive layer 16 is used, for example, chemical vapor deposition is used.' Wang, > The stacked polycrystalline silicon layer 'covers on the gate oxide layer 14. Then it is imaged by the image and Wei Sui, que. @.',, Qiu / Private sequence conductive layer 16 and gate oxide The pattern of layer 14 together constitutes a gate electrode structure G. As shown in Fig. 2, the bottom of the mouth 1 η ί ΐ 1 on the exposed substrate (base 10 and polycrystalline spar layer 16 in a pure oxygen environment). The surface is oxidized to form-shield oxide layer 18: two = two. Due to the money engraved in the closed-polar structure defined above, it may cause some defects in the gate oxide layer and the wafer surface. Therefore: The procedure (re-oxidation) can shield the oxide layer 18 from the damage caused by the etching. It is used to protect the closed oxide layer and the substrate from ion A. The same% can prevent The implanted ions are lost from the surface during the subsequent tempering procedure. Next, as shown in FIG. 3, the gate electrode structure G is used as the cloth. An appropriate dose of ions (such as boron, phosphorus, or arsenic ions) is implanted into the substrate and then thermally tempered in a nitrogen environment to diffuse the human implanted ions into the drlve-silicon substrate. To form a pair of lightly doped / drain regions 20. However, since some ions may be implanted during ion implantation, 521351 V. Description of the invention (3) Combined with impurities in Shi Xijing to form a complex (c 〇mplex), will cause the activation rate of the ions after tempering to decrease, resulting in higher resistance. Figure 4 shows the relationship between the projection distance (pro j ec ted range) of boron implantation and the activation rate; The size can represent the level of energy used for implantation. In this figure, boron ions at a dose of 1 X 1013 / cm2 are implanted into a silicon wafer with different implantation energies (5 ~ 160 keV), and then at 90%. Tempering at 20 ° C for 20 seconds. It can be found from the figure that the activation rate of boron ions is significantly reduced when implanted at low energy (~ 5keV). Due to the activation effect mechanism of boron ions, it depends on the insertion of shed ions from the gap The lattice position enters the substitutional lattice position. The number of vacancies at the surface is greatly reduced, which makes B-impurity coompiex unable to enter the vacancies and achieve activation. Related literature can refer to F. pr i〇 丨 〇, e1: al · , APL 72 (23), ρ · 3011 (1998). On the other hand, when ion implantation is performed, various defects will be generated in Shi Xijing according to the type and degree of implanted ions, such as insertion. Interstitial Type, Vacancy Type, etc. 'Self-Interstitial Type Defects are one of the main causes of transient accelerated diffusion during RTA processing. Figure 5 illustrates the phenomenon of transient accelerated diffusion using ion implantation as an example. It shows that the boron implantation has undergone RTA tempering at 800 ° c for 15 seconds, 15 minutes, 1 hour, and 2 hours. Depth map. As shown in Figure 5, rotten ions are at § 〇 〇. The transient acceleration phenomenon below 〇 becomes saturated within 15 minutes, and after that, even if the tempering lasts for two hours, it will not increase the depth of diffusion, so it is called " transient " accelerated diffusion. For the literature on transient accelerated diffusion, please refer to L · η. Z h a n g, e t V. Description of the invention (4) al ·, APL 67 (14), ρ · 2052 (1 995). Generally speaking, the treatment of implantation ions in RTA by RTA can reduce the surface energy by reducing the energy at the time of implantation, and temporarily accelerate the spread of sorrow. It is mentioned that reducing the energy of implantation will inevitably lead to live ^^ High in the previous article. Therefore, how to mitigate the transient accelerated expansion and decrease the electrical limit of the junction surface and reduce its resistivity at the same time, so as to form a very shallow existence. It is a kind of improved LDD system in the conventional technology that has become the focus of the present invention. The growth of the B layer directly implants ions in the substrate, and does not pass through the shielding of the oxidants. However, when this method eliminates the f layer that shields the fluorinated layer and leaves it by thermal tempering, it will cause damage to the gate oxide layer, which will not only cover the oxide layer of the ion cloth, but also cause ionization. Less shadowing shown during tempering. [Please refer to Mark G. Stlns (; \ Lost, as shown in Figure 6 22 487 (1991)] ai ·, ED-38 (3), ρ · Ion under the protection of another improved method in the conventional technology The implantation, however, is performed after the masking oxide layer of the masking oxide layer is stripped off, and the masking oxide layer is destroyed by ion implantation in a thirsty etching manner. Although this method can avoid instability As a result, it is still unavoidable that when T is not tempered and the masking oxide layer is not stripped during tempering, the potential is lost from the surface, and in addition, a part of the gate oxide is etched in time. , = Also because of its isotropic etching, this method also has a complete gate oxide layer ^ 1 shown in Figure 7 at 24, so in view of the above problems, the problem of the present invention exists. &Quot; Manufacturing and methods of conductor elements, The purpose is to provide a kind of half // alleviation of 521351 during the tempering treatment of doped ions. V. Description of the invention (5) Temporarily accelerate the diffusion phenomenon to form a very shallow junction surface, and at the same time, doped ions Activation rate to form a low-resistance joint. 'Another object of the present invention is Provided is a method for manufacturing a semiconductor device, which can prevent dopant loss on the surface of a doped region, and at the same time ensure layer integrity. ≪ To achieve the above-mentioned object, the method of the present invention is performed after LDD implantation and contains rhenium. Or rapid thermal tempering under the gas environment of Dragon 3 to replace the traditional thermal tempering under pure nitrogen (n2). Jian Luzhi 'method of the present invention includes the following steps: (a) providing a semiconductor A substrate on which a gate structure is formed; (b) a substrate that shields an oxide layer on both sides of the gate structure; (c) performing an ion implantation to form a lightly doped region in the substrate on both sides of the gate structure ; And (d) implement a quickening process.

The rapid nitriding process (RapU) performed in step (d) of the present invention

Thermal Wtridatbn), rapid thermal tempering in a gas environment containing N0, n2〇, or Nh3. For example, it can be tempered under a mixed gas of N at 90 0 ~ 1 050 ° C for 5 ~ 30 seconds. bell. The nitriding process here can release inject vacancies in the Shi Xi lattice, which has the following two effects: (1) lattice vacancies released by nitriding can help dopant-impurity complexes ( dopant — impuritycomp lex) dissolves, because it can be improved>, the rate of tongue ^ is as described above, when low energy doping, because the density near the surface is not enough, there will be a problem of low activation rate, and According to the present invention, the lattice vacancies released by the method can be used to make up the number of surface vacancies. ^ Bu 521351 5. Invention description (6), therefore, the activation rate of ions can be increased, and a low-resistance junction can be formed. (2) The lattice vacancies released by nitridation can recombine the silicon atoms located at the interstitial spaces and enter the appropriate vacancies, thereby reducing the transient accelerated diffusion. As mentioned above, the interstitial-type defects caused by ion implantation are one of the main reasons for the transient accelerated diffusion, and the lattice vacancies released by nitriding in the present invention can make the originals located at the interstitial spaces ( Interstitia 1) Shi Xi atoms enter the appropriate vacancies through lattice recombination, so the number of silicon atoms at the interstitial space can be reduced, thereby reducing the phenomenon of light transient accelerated diffusion and forming a very shallow junction. In addition, after step (d), those skilled in the art can make insulating sidewall layers and source / drain regions according to conventional process technologies to complete field effect transistors with low resistance / very shallow junctions. Making. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings 1 to 3 The figure is a series of cross-sectional views, which are used to explain the process of making LDD. Fig. 4 is a graph showing the relationship between the projection distance of boron implantation and the activation rate. Figure 5 is a concentration depth map of boron ion implantation after undergoing RTA tempering at different times to illustrate the phenomenon of transient accelerated diffusion. Figures 6 and 7 are cross-sectional views of the manufacturing process, respectively illustrating two conventional LDD improvement processes. Figures 8 to 10 are a series of cross-sectional views to illustrate the preferred embodiment of the present invention.

V. Description of the invention (7) Example of symbolic flow chart for making LDD in the examples 10, 30 ~ silicon substrate; 12 layers; 16 and 36 ~ conductive layers to isolate oxides; 14, 34 ~ gate oxygen doping Source / drain region; & 18, 38 ~ shielding oxide layer; 20, 40 ~ fading; 4 2 ~ sidewall spacers · surface dopant loss; 2 4 ~ gate oxide layer missing '4 ~ source / Drain region; G ~ gate structure. —Example The following is an example of the present invention. As described in detail in FIG. 8 to FIG. 10, a detailed description is given by applying a lightly doped τ① of an N-type ion to form a PMOS element. The system's P β catastrophe (STI) is used to form an isolation / field rolling method (LOC0S) or a shallow trench isolation device area to form a free pole: 32 'to define the device area' and then, as in Section 8 As shown. Structure G, including the gate oxide layer 34 and the gate 36 layer, is usually a dry thin layer 34 is a thin layer of non-pollution oxygen, and the coarse-type or wet thermal oxidation method is slow Formation; interfacial electrodes 36, 疋 L / pre-vapour deposition (CVD) or similar methods, and multiple crystals. After forming the stacked interlayer oxide layer 34 and the gate compound silicon layer 36, they are defined as the gate structure G shown in FIG. Referring to FIG. 9, a shielding oxide layer is formed on the substrates on both sides of the gate structure g. 38 ° A shielding oxide layer is grown at a temperature of 900-1000 ° C in a pure oxygen environment, with a thickness of about 20 ~ 70 0 Angstroms. At this time, a masking oxide layer 38 will be formed on the exposed surface of the substrate 30 and the polycrystalline silicon layer 36, as shown in FIG. due to

521351 V. Description of the invention

The aforementioned definition of some defects on the surface of the gate structure, so the process j here may lead to the surface of the wafer table 30 and the polycrystalline silicon layer 36. The lice process can recover the bare substrate. It is oxidized to damage the etching. Please continue to refer to Fig. 9. Structure G is used as a mask, and it is implanted with LDD. Use the gate electrode to form the source / :: implant, the protection provided by the oxide layer 38 on opposite sides of the gate? Miscellaneous area 42, at this time, the edge of the oxide layer 3 4 can be avoided due to the shadowing.

The two implants can be destroyed to ensure the integrity of the gate oxide layer. The LDD of the PMOS element was implanted using boron difluoride (Bf2) ions at a dose of about 1013 to 1015 / cnr2 and an energy of about 3 to 15 keV. Next, the key step of the present invention is performed, and rapid thermal tempering is performed in a gas environment containing N 0, κ 0 or MI. In this embodiment, 2 is a mixed gas of n2 / nh3 (gas flow ratio: nH3 / N 疒 0 · ι ~ 80%), and is continuously tempered at a temperature of 900 ~ 1050 C for 5 ~ 30 seconds. To complete the implantation of ions. At this time, 'lattice vacancies released by the nitridation process can increase the activation rate of ions' and at the same time reduce the phenomenon of transient accelerated diffusion, so a low-resistance and extremely shallow junction surface can be formed after tempering. On the other hand, due to this tempering process

The sequence is performed under the covering of an oxide layer, so that the dopant can be prevented from being lost from the surface. Please refer to Figure 10, and the following steps. Those skilled in this art can make the sidewall spacer 42 and the source electrode according to the traditional process technology. / Pole area 4 4 to complete the fabrication of PM0S transistor. For example, an oxide layer having a thickness of about 1000 to 2500 angstroms can be deposited on the substrate 30 and the gate structure G first, and then plasma etching is used.

Page 11 521351 V. Description of the invention (9) The oxide layer is anisotropically etched into a sidewall spacer layer 42. Then, using the electrode structure G and the sidewall spacer 42 together as a mask, implanting a higher dose of ions into the substrate to form a strongly doped source and drain region 44 is completed as shown in FIG. 10 The shown Mos transistor. It can be seen from the above description that the present invention provides a simple and effective solution to the problem: the transient acceleration of the phenomenon of ΪΪ, which can solve the problem of low-energy implantation in the conventional process rate Ϊ 时. To sum up, the process of the present invention has the following advantages compared with Bai Zhiyi, which has the following advantages: The activation rate can be reduced to obtain a low-resistance joint surface. The sub-plant destroys the transient state of households and accelerates the spread. ν ύ 八 Avoid the loss of adulteration on the surface. < [Peptide (4) · Ensure gate oxide integrity. The present invention has been disclosed in a preferred embodiment. Anyone skilled in the art is familiar with the above, but it is not within the range of t. It can be used to make various changes. f Without departing from the spirit and scope of the present invention, the scope of the patent application attached hereto shall be regarded as the definition of the guarantee of the present invention shall prevail.

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Claims (1)

521351 6. Scope of patent application 1. A method for manufacturing a low-resistance / very shallow junction semiconductor device, including the following steps: (a) providing a semiconductor substrate having a gate structure formed thereon; (b) forming a masking oxide A substrate layered on both sides of the gate structure; (c) performing an ion implantation to form a doped impurity region in the substrate on both sides of the gate structure; and (d) performing a rapid nitriding process. 2. The manufacturing method according to item 1 of the scope of patent application, wherein the gate structure includes a conductive layer and a gate oxide layer. 3. The manufacturing method according to item 1 of the scope of patent application, wherein the thickness of the shielding oxide layer is 20 to 70 angstroms. 4. The manufacturing method as described in item 3 of the scope of patent application, wherein the shielding oxide layer is formed by a thermal oxidation method at a temperature of 900 to 100 ° C. 5. The manufacturing method described in item 1 of the scope of patent application, wherein step (d) is rapid thermal tempering in a gas environment containing NO, N20, or NH3. 6. As described in item 5 of the scope of patent application The manufacturing method, wherein the step (d) is continuously tempered for 5 to 30 seconds at 900 to 105 ° C. 7. The manufacturing method as described in item 6 of the scope of patent application, wherein step (d) is performed by rapid thermal tempering in a gas environment containing N2 and NH3. 8. The manufacturing method as described in item 7 of the scope of patent application, wherein the gas flow ratio: ΝΗ3 / Ν2 = 0.1 to 80%. Page 13