1376018 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構的形成方法，且特別 是有關於記憶體元件之製程技術。 【先前技術】 隨著先進的CMOS技術中，通道長度的逐漸縮短，造 φ 成通道區與源極與汲極之空乏區重疊比例上升而使短通道 效應更為嚴重’為了抑制pMOSFET(p型金氧半場效電晶 體）之短通道效應（short-channel effect, SCE)，廣泛地使用雙 多晶矽閘極與表面通道金氧半場效電晶體。 在P+多晶矽閘極製程中，需掺雜夠高的侧以提供適合 的閘極導電率。然而，硼在高溫製程時具相對高的活性， 會有部分的硼在多晶矽晶界中快速擴散。甚至部分的硼原 子會穿越閘極介電層到達基底，造成元件效能衰退，例如 • 啟始電壓不穩定或次啟始電流擺蕩退化（subthreshold swing degradation)等。此現象即為硼穿透效應（B penetration effect)。隨著元件尺寸的縮小化，硼穿透所引發 元件效能與可靠度上的不良影響更為嚴重。 為了抑制硼的穿透效應，習知技術常使用去耦合電漿 氮化（decoupled plasma nitridation，DPN)法與後氮化退火 (post nitridation anneal，PNA)法於閘極氧化層之上表面摻 雜氮。閘極氧化層上之高濃度氮可擋住隨後形成於其上之 閘極中的硼原子，使其無法在製程期間擴散進入閘極氧化 97-012/0492-A41863-TW/fi^ 5 1376018 層中及pMOSFET之通道區。隨後的後氮化退火可進一步 增加薄膜之穩定性與電性。 然而，對於快閃記憶體技術而言，無法直接採用上述 去耦合電漿氮化法與後氮化退火法來抑制硼穿透效應。這 是因為對快閃記憶體而言，其記憶陣列區已形成有電荷阻 絕層。電荷阻絕層之結構一般為氧化層_氮化層_氧化層之 堆疊結構。若於此時對快閃記憶體之周邊區進行氮化製程 以擋住隨後所形成之閘極(例如低電壓閘極或高電壓閘極) 中之硼擴散，會連同將電荷阻絕層上層之氧化層氮化，造 成δ己憶體效能衰退，例如抹除速度或資料保存的效能衰 退雖然，亦可先行在基底上形成閘極層（隨後經圖案化可 作為控制閘極)將電荷阻絕層蓋住，以避免氧化層受氮化。 但此舉同時亦會將周邊區蓋住，因而需多一道微影及蝕刻 製程以將周邊區上所形成之閘極層移除，才能繼續接下來 的製程，造成製作成本的增加。 【發明内容】 本發明提供一種半導體結構的形成方法，包括提供具有記 憶陣列區與周邊區之基底，且記憶陣列區包括至少一閘極堆 f，形成第一氧化層於閘極堆疊上，形成氮化層於第一氧化層 上’對基底佈植以於周邊區中形成低壓井區及高壓井區，以第 一溫度對基底進行第一熱處理以於低壓井區及高壓井區上分 別形成第一閘極氧化層與第二閘極氧化層，第一閘極氧化層之 厚度小於第二閘極氧化層，且第一熱處理大抵不使氮化層之上 表面氧化，於第一閘極氧化層與第二閘極氧化層中導入擴散阻 97-012/0492-A41863-TW/f7 6 1376018 第:^對基底進行第二熱處 二氧化層。 κ θ、衫―祕氧化層上形成第 :讓:發明之上述和其他目的、特徵、和優點能更明顯 易下文特舉出較佳實施例，並配合所_式，作詳細 說明如下： 【實施方式】 第1-7圖顯示本發明實施例之一系列製程剖面圖。如 第1圖所示，首先提供具有記憶陣列區1與周邊區2之基 底100。記憶陣列區！中至少包括一閉極堆疊1〇2，而第1 圖所顯示之實施例除了記憶陣列區1包括閘極堆疊102 外，周邊區2亦包括閘極堆疊1〇2。此外，亦可視情況於 基底_中形朗以隔離元件的淺槽絕緣區3。基底1〇〇 可包括半導體材料，例如梦、鍺、補、化合物半導體材 料、或其他適合的半導體材料。閘極堆疊1〇2包括多晶石夕 閘極及閘極介電層。淺溝槽絕緣區3例如可以高密度電衆 ;儿積法將絕緣材料填入溝槽中而形成。 記憶陣列區1將用以形成記憶體元件，而周邊區2將 用以形成低航件與高壓元件。在—實施射，將於記憶 陣列區1形成快閃記憶體。快閃記憶體—般包括電荷阻絕 層於閘極堆#1G2上，通常電荷阻絕層包括由氧化層-氣化 層-氧化層（ΟΝΟ)所組成之疊層。 清接著參照第1圖，於閑極堆疊1〇2上形成第一氧化 層104’並接著於第一氧化層1〇4上形成氣化層ι〇6。本發 97-012/0492-Α41863-TW/£^ 7 1376018 明實施例有別於習知技術一次依序形成氧化層_氮化層氣 化層之電荷阻絕層’係採分次形成電荷阻絕層之方式。先 只依序形成氧化層與氮化層，河·避免最上層之氧化層受到 氮化而影響記憶體之效能。在一實施例中，可使用熱氧化 法形成第一氧化層1〇4。接著，可以化學氣相沉積法形成 氮化層106。 接著’對基底1〇〇佈植以於周邊區2形成低壓井區與 _ 高壓井區。如第2圖所示，可先形成第一遮蔽層1〇8於記 憶陣列區1上以露出周邊區2。第一遮蔽層108可例如為 圖案化光阻層。接著，以第一遮蔽層1〇8為罩幕將周邊區 2上之閘極堆疊1〇2、第一氧化層1〇4、及氮化層1〇6移除， 並於周邊區2摻雜適合濃度之摻質（dopant)以分別形成低 壓井£ 110與局壓井區112。低壓井區與高塵井區Η: 之佈植較佳以離子佈植的方式進行，為避免離子佈植的能 量過高而傷害基底1〇〇，較佳於蝕刻移除周邊區2上之閘 Φ 極堆疊102、第一氧化層1〇4、及氮化層106時，刻意保留 閘極堆疊102下之一犧牲氧化層113以減緩離子佈植時對 基底100之衝擊。犧牲氧化層113可為基底之原生氧化層 或如第1圖所示在形成淺溝槽絕緣區3時於閘極堆疊12曰〇 下方所形成之氧化層。在形成低壓井區11〇與高壓井區ιΐ2 後，可如第3圖所示將犧牲氧化層113移除而露出其下之 低壓井區110與高壓井區112之表面。 请接著參照第4圖，在-實施例中，可先將第一遮蔽 層108移除，並接著例如以熱氧化法於周邊區2上形成初 97-012/0492-A41863-TW/f^ 8 1376018 始閘極氧化層114。接著，形成第二遮蔽層ii6於記憶陣 列區1與周邊區2中之高壓井區112上，並露出低壓井區 110上之初始閘極氧化層114。第二遮蔽層116可例如為圖 案化光阻層。 在-實施例中’可以第二遮蔽層116為罩幕，對低壓 井區110進行啟始電壓摻雜，此#蓺人丄π、a比ό认 G筏蟄人士可視情況摻雜適1376018 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of forming a semiconductor structure, and more particularly to a process technology for a memory device. [Prior Art] With the CMOS technology, the channel length is gradually shortened, and the overlap ratio between the channel region and the source and drain regions is increased, which makes the short channel effect more serious. The short-channel effect (SCE) of the gold-oxygen half-field effect transistor, the double-polysilicon gate and the surface channel gold-oxygen half-field effect transistor are widely used. In the P+ polysilicon gate process, a sufficiently high side is required to provide a suitable gate conductivity. However, boron has a relatively high activity in a high-temperature process, and a part of boron rapidly diffuses in the polycrystalline twin boundaries. Even some of the boron atoms pass through the gate dielectric layer to the substrate, causing component degradation, such as • initial voltage instability or subthreshold swing degradation. This phenomenon is the B penetration effect. As the size of the components shrinks, the adverse effects of component efficiency and reliability caused by boron penetration are more serious. In order to suppress the penetration effect of boron, the prior art often uses a decoupled plasma nitridation (DPN) method and a post-nitridation anneal (PNA) method to dope the upper surface of the gate oxide layer. nitrogen. The high concentration of nitrogen on the gate oxide layer blocks the boron atoms in the gate formed subsequently, making it impossible to diffuse into the gate oxide during the process. 97-012/0492-A41863-TW/fi^ 5 1376018 Medium and pMOSFET channel area. Subsequent post-nitridation annealing can further increase the stability and electrical properties of the film. However, for the flash memory technology, the above-described decoupling plasma nitriding method and post-nitriding annealing method cannot be directly used to suppress the boron penetrating effect. This is because for the flash memory, the memory array region has formed a charge blocking layer. The structure of the charge blocking layer is generally a stacked structure of an oxide layer - a nitride layer - an oxide layer. If at this time, the peripheral region of the flash memory is nitrided to block the diffusion of boron in the subsequently formed gate (for example, a low voltage gate or a high voltage gate), together with oxidation of the upper layer of the charge blocking layer. Layer nitridation, causing degradation of δ mnemonic performance, such as erasing speed or performance degradation of data storage, although the gate layer can be formed on the substrate (subsequently patterned to serve as a control gate) Live to avoid oxidation of the oxide layer. However, this will also cover the surrounding area, so a lithography and etching process is required to remove the gate layer formed on the surrounding area to continue the next process, resulting in an increase in production costs. SUMMARY OF THE INVENTION The present invention provides a method of forming a semiconductor structure, including providing a substrate having a memory array region and a peripheral region, and the memory array region includes at least one gate stack f, forming a first oxide layer on the gate stack to form The nitride layer is implanted on the first oxide layer to form a low-pressure well region and a high-pressure well region in the peripheral region, and the first heat treatment is performed on the substrate at the first temperature to form the low-pressure well region and the high-pressure well region respectively. a first gate oxide layer and a second gate oxide layer, the first gate oxide layer has a thickness smaller than the second gate oxide layer, and the first heat treatment does not substantially oxidize the upper surface of the nitride layer to the first gate A diffusion barrier 97-012/0492-A41863-TW/f7 6 1376018 is introduced into the oxide layer and the second gate oxide layer to form a second thermal oxide layer on the substrate. The above-mentioned and other objects, features, and advantages of the invention are more obvious. The preferred embodiments are described below, and the detailed description is as follows: Embodiments Figs. 1-7 are cross-sectional views showing a series of processes in an embodiment of the present invention. As shown in Fig. 1, a substrate 100 having a memory array region 1 and a peripheral region 2 is first provided. Memory array area! At least one closed-pole stack 1 〇 2 is included, and the embodiment shown in FIG. 1 includes a gate stack 1 〇 2 in addition to the memory array region 1 including the gate stack 102. In addition, it is also possible to isolate the shallow trench isolation region 3 of the component from the substrate _ in the middle. Substrate 1 〇〇 may comprise a semiconductor material such as a dream, germanium, make-up, compound semiconductor material, or other suitable semiconductor material. The gate stack 1〇2 includes a polycrystalline gate and a gate dielectric layer. The shallow trench isolation region 3 can be formed, for example, by a high-density electricity source; the insulating material is filled in the trench. Memory array area 1 will be used to form memory elements, while peripheral area 2 will be used to form low and high voltage components. In the implementation of the shot, a flash memory will be formed in the memory array area 1. The flash memory generally includes a charge blocking layer on the gate stack #1G2. Typically, the charge blocking layer comprises a stack of an oxide layer-gasification layer-oxide layer. Next, referring to Fig. 1, a first oxide layer 104' is formed on the dummy pad stack 1 2 and then a vaporization layer ι 6 is formed on the first oxide layer 1〇4. The present invention is different from the prior art in that the oxide layer is formed in sequence, and the charge blocking layer of the vaporized layer of the nitride layer is formed to form a charge block. The way of the layer. First, the oxide layer and the nitride layer are formed only in order, and the river avoids the oxidation of the uppermost layer to affect the memory. In one embodiment, the first oxide layer 1〇4 may be formed using a thermal oxidation process. Next, the nitride layer 106 can be formed by chemical vapor deposition. Next, the substrate 1 is implanted to form a low pressure well region and a high pressure well region in the peripheral region 2. As shown in Fig. 2, a first mask layer 1 〇 8 may be formed on the memory array region 1 to expose the peripheral region 2. The first masking layer 108 can be, for example, a patterned photoresist layer. Then, the gate stack 1〇2, the first oxide layer 1〇4, and the nitride layer 1〇6 on the peripheral region 2 are removed by using the first shielding layer 1〇8 as a mask, and are doped in the peripheral region 2 A dopant of suitable concentration is formed to form a low pressure well £110 and a crush zone 112, respectively. Low-pressure well zone and high-dust well zone: The planting is preferably carried out by ion implantation. In order to avoid the excessive energy of ion implantation and damage the substrate, it is better to etch and remove the peripheral zone 2 When the gate Φ pole stack 102, the first oxide layer 1〇4, and the nitride layer 106 are deliberately retained one of the sacrificial oxide layers 113 under the gate stack 102 to mitigate the impact on the substrate 100 during ion implantation. The sacrificial oxide layer 113 may be a native oxide layer of the substrate or an oxide layer formed under the gate stack 12A when the shallow trench isolation region 3 is formed as shown in Fig. 1. After forming the low pressure well region 11 and the high pressure well region ι2, the sacrificial oxide layer 113 can be removed as shown in Fig. 3 to expose the surface of the lower low pressure well region 110 and the high pressure well region 112. Referring to FIG. 4, in the embodiment, the first shielding layer 108 may be removed first, and then the first 97-012/0492-A41863-TW/f^ is formed on the peripheral region 2 by, for example, thermal oxidation. 8 1376018 Start gate oxide layer 114. Next, a second masking layer ii6 is formed on the high voltage well region 112 in the memory array region 1 and the peripheral region 2, and the initial gate oxide layer 114 on the low voltage well region 110 is exposed. The second masking layer 116 can be, for example, a patterned photoresist layer. In the embodiment, the second shielding layer 116 can be used as a mask to initiate voltage doping of the low-voltage well region 110, and the #蓺人丄π, a is more suitable for the person in question.
合種類與濃度之摻質。由於低愿并F 元件，-般需要較薄之閘極氧化t^係用以形成低壓 較佳更包括於低壓井區110佈植氣化此在一實施例中， 雜氮。接著，將低壓井區110上之初弘制雜質，例如可摻 除。在移除低壓井區110上之初始。閘極氧化層114移 第二遮蔽層116移除。 玉氣化層114後，將 接著’進行本發明實施例之— 不，以第一溫度對基底100進行第—7驟，如第5圖所 110及高壓井區II2上分別形成第一熱處理以於低壓井區 二閘極氧化層120，其中第一閘極閘極氣化層118與第 第二閘極氧化層120〇這是因為在二化層118之厚度小於 氧化層120是由如第4圖所示 實施例中，第二閘極 一熱處理所生成之氧化層共同，極氣化層114鱼第 需之較厚閘極氧化層。此外 j ’因而具有高墨元 =井區m上佈植氧化抑制雜；貧施例中’更包括先於 熱處理下，低壓井區110上質’例如氣，因此 慢，而具有低壓元件所需 閘極氣化層 笛<較⑽^ 的成長速度較 第一閘極氧化層12〇在上 岡極氣化層。^ μ 上述實施例中，/嘈。此外，雖然 97-012/0492-A41863-TW/F 二由初始閘極氧化 曰114與第一熱處理所成長之氧化層共同形成，然初始閘 極氧化層之形成並非必須。在其他實施例中，可省略初始 閘極氧化層之形成步驟而僅於低壓井區110上佈植氧化抑 ，雜質，如此仍能於第一熱處理進行的過程中，於低壓井 區110上形成較薄之閘極氧化層，而於高壓井區112上形 成較厚之閘極氧化層以符合各元件之需求。 _第一熱處理之第一溫度為刻意選擇之溫度，以使閘極 氧化層僅於低壓井區110與高壓井區112上形成，而大抵 不使記憶陣列區1上之氮化層106上表面氧化。在一實施 例中，第一溫度介於約75(rc至約950〇c之間，較佳介於約 850 C至約900。(：之間，以使周邊區2上閘極氧化層成長期 間’大抵不於氮化層106上形成氧化層。這是因為在相對 低/JHL的熱處理下’氧化層不易於氮化層上生成。在一實施 例中’第一熱處理是在純氧氣或氧氣氫氣混合之氣氛下， 以第一溫度熱處理約數分鐘至數十分鐘。在一實施例中， 例如可採用臨场蒸汽氧化(in sku steain generati〇n，isSG) 製程來進行第一熱處理。 接著’於第一閘極氧化層118與第二閘極氧化層120 中導入擴散阻擋材料124。閘極氧化層中所導入之擴散阻 擋材料可於後續製程中，避免形成於其上之閘極(例如多晶 矽閘極）中的摻質（如硼）擴散穿過閘極氧化層，進而到達低 壓井區11〇或高壓井區112中而影響元件之運作。在一實 苑例中，擴散阻擋材料124例如包括氮，可使用例如去耦 合電漿氮化(DPN)法將氮導入閘極氧化層中。在另一實施 97-012/0492-A41863-TW/f/ 1376018 I括仃熱處理(壯後1^化退火法）而將擴散 :材料活化，進一步増進穩定性與電性。後氮化退火之 …、處理溫度可介於約950°C至約l〇5〇t之間。 請接著參照第6圖，以高於第一溫度之第二溫度對基 _ 100進仃第二熱處理以於氮化層讓上形成第二氧化層 122。記憶陣列區！中之第一氧化層1〇4、氮化層刚、盘 ^一^化層122之疊層將共同組成電荷阻絕層。於此同 μ —熱處理亦會於第—閘極氧化層118與第二閘極氧 形成氧化層’因此第-閘極氧化層m與第二 =:120將分別增厚為第一間極氧化層服與第二 =氧化層1施。第二熱處理具有較高溫之第二 =使於氮化層上仍可形成第：氧化層122。且‘ :之閘極氧化層已佈植有氮，不再需要對基The type and concentration of the dopant. Due to the low wish and the F element, a thinner gate oxide is generally required to form a low voltage. Preferably, it is included in the low pressure well region 110 to be vaporized. In one embodiment, the nitrogen is used. Next, the impurities on the low pressure well region 110 can be doped, for example, by doping. The initial on the low pressure well zone 110 is removed. The gate oxide layer 114 is removed by the second masking layer 116. After the jade gasification layer 114, the first embodiment of the present invention will be followed by a first temperature treatment of the substrate 100 at a first temperature, and a first heat treatment at a high pressure well region II2 as shown in FIG. In the low-voltage well region, the second gate oxide layer 120, wherein the first gate gate gasification layer 118 and the second gate oxide layer 120 are because the thickness of the germanization layer 118 is smaller than the oxide layer 120 is In the embodiment shown in Fig. 4, the oxide layer formed by the heat treatment of the second gate is common, and the thick gas gate layer of the gasification layer 114 is required. In addition, j' thus has a high ink element = planting oxidation inhibition on the well area m; in the poor case, 'more includes the heat treatment, the low pressure well area 110 is superior to the mass, such as gas, and therefore slow, and has the gate gas required for the low voltage component. The growth velocity of the layered flute < (10)^ is higher than that of the first gate oxide layer 12 in the upper gasification layer. ^ μ In the above embodiment, /嘈. Further, although 97-012/0492-A41863-TW/F 2 is formed by the initial gate oxide 曰 114 and the oxide layer grown by the first heat treatment, the formation of the initial gate oxide layer is not essential. In other embodiments, the initial gate oxide formation step may be omitted and only the low pressure well region 110 may be implanted with oxidation, impurities, which may still form on the low pressure well region 110 during the first heat treatment process. A thinner gate oxide layer forms a thicker gate oxide layer on the high voltage well region 112 to meet the requirements of the various components. The first temperature of the first heat treatment is a deliberately selected temperature such that the gate oxide layer is formed only on the low pressure well region 110 and the high voltage well region 112, and substantially does not cause the upper surface of the nitride layer 106 on the memory array region 1. Oxidation. In one embodiment, the first temperature is between about 75 (rc and about 950 〇c, preferably between about 850 C and about 900. (between: and so on, during the growth of the gate oxide layer on the peripheral region 2) 'An oxide layer is not formed on the nitride layer 106. This is because the oxide layer is not easily formed on the nitride layer under a relatively low/JHL heat treatment. In an embodiment, the first heat treatment is in pure oxygen or oxygen. The atmosphere is mixed with hydrogen at a first temperature for about several minutes to several tens of minutes. In one embodiment, for example, a first sku steain generati〇n (isSG) process may be used for the first heat treatment. A diffusion barrier material 124 is introduced into the first gate oxide layer 118 and the second gate oxide layer 120. The diffusion barrier material introduced in the gate oxide layer can avoid the gate formed thereon in a subsequent process (for example The dopant (such as boron) in the polysilicon gate diffuses through the gate oxide layer and reaches the low voltage well region 11 or the high voltage well region 112 to affect the operation of the device. In a practical example, the diffusion barrier material 124 For example, including nitrogen, for example, A coupled plasma nitridation (DPN) method is used to introduce nitrogen into the gate oxide layer. In another implementation, 97-012/0492-A41863-TW/f/ 1376018 I will be heat treated (strong after annealing). Diffusion: material activation, further expansion stability and electrical properties. Post-nitridation annealing..., processing temperature can be between about 950 ° C to about l 〇 5 〇 t. Please refer to Figure 6, above a second temperature of a temperature is applied to the base _100 for a second heat treatment to form a second oxide layer 122 on the nitride layer. The first oxide layer 1〇4, the nitride layer, and the disk in the memory array region! The stack of layers 122 will collectively form a charge blocking layer. The same heat treatment will also form an oxide layer in the first gate oxide layer 118 and the second gate oxide, thus the first gate oxide layer m and The second =: 120 will be thickened separately to the first inter-layer oxide layer and the second = oxide layer 1. The second heat treatment has a higher temperature second = the formation of the first layer on the nitride layer: oxide layer 122 And ': the gate oxide layer has been implanted with nitrogen, no need for the base
St二施财，第二熱處理可為臨場蒸汽氧化 (ISSG)製程，第二熱處理溫度可介於約95代至約則 =:較佳介於約刚代至約赠c之間。第二熱處理可 在氧軋及氫A混合之氣氛下，以第二溫度祕理約數分鐘。 此外，如第4-6圖所示，第一閘極氧化層ma鱼第二 閘極氧化層腿可能包括初始閘極氧化層、第—熱處理戶: 生成之氧化層、與第二熱處理之氧化層。1中，瓿 理所產生之氧化層的厚度受限於所需第二氧化層= 度’不易作調整。然此技藝人士當可明瞭，仍可透 始閉極氧制與第-減輯產生之氧化層的厚度控^ 97-012/0492-A41863-TW/^ 1376018 (例如透過調整熱處理溫度與方式）’來獲得所需的最終第 一閘極氧化層118a與第二閘極氧化層12〇a，以符合個別 元件之需求。St. 2, the second heat treatment may be an on-site steam oxidation (ISSG) process, and the second heat treatment temperature may range from about 95 generations to about =: preferably between about just generations to about c. The second heat treatment may be carried out in an atmosphere of oxygen rolling and hydrogen A for a few minutes at a second temperature. In addition, as shown in Figures 4-6, the second gate oxide layer of the first gate oxide layer may include an initial gate oxide layer, a first heat treatment household: an oxide layer formed, and an oxidation of the second heat treatment layer. Floor. In 1, the thickness of the oxide layer produced by the treatment is limited by the required second oxide layer = degree'. However, it is clear to the skilled person that the thickness of the oxide layer produced by the closed-end oxygen system and the first-decrease can be controlled by the thickness of the oxide layer (for example, by adjusting the heat treatment temperature and mode). 'To obtain the desired final first gate oxide layer 118a and second gate oxide layer 12A to meet the requirements of individual components.
在一實施例中，可接著如第7圖所示，以習知方法(例 如多晶矽層之沉積、材料層之圖案化、與源極/汲極區之佈 植等）於閘極堆疊102之電荷阻絕層上形成控制閘極126, 並於低壓井區110與高壓井區112之第一閘極氧化層Uh 與第一閘極氧化層120a上分別形成低壓閘極128與高壓閘 極130以形成記憶體元件。由於第一問極氧化層與^ 二閘極氧化層120a中已佈植有擴散阻擋材料(例如氮/，' 此低壓閘極或高壓閘極中之較小離子（例如硼）將難以穿尚 閘極氧化層到達井區，可確保低壓元件與高壓元件之4 作。此外，記憶陣歹,m i之第二氧化層122是在擴散Z 材料（例如氮)佈植之後才形成，因而大抵不包括氮，不二 ，習知技術中，記憶體效能因上層氧化層氮化而衰退= 題0 本發明實施例具有許多優點。由於刻意選擇熱處 方式，使氮化層106上大抵不形成氧化層。因此，不合 習知技術中電荷阻絕層之上氧化層受氮化的問題曰= 外，使用本發明實施例之方法不需額外的微影核 程，便可於閘極氧化層中佈植擴散阻擋材料。 雖然本發明已讀個較佳實施例揭露如上， 用以限^本發明，任何所屬技術領域巾具有通常知增去 在不脫離本剌之精神和範#可作任意之更^潤 97-012/0492-A41863-TW/f/ 12 1376018 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1-7圖顯示本發明一實施例之製作半導體結構的一 系列製程剖面圖。 【主要元件符號說明】 1〜記憶陣列區；2〜周邊區；100〜基底；3〜淺溝槽絕緣 區；102〜閘極堆疊；1〇4〜第一氧化層；106〜氮化層；108〜 第一遮蔽層；110〜低壓井區；112〜高壓井區；113〜犧牲氧 化層；1U〜初始閘極氧化層；116〜第二遮蔽層；118、118a〜 第一閘極氧化層；U0、12〇a〜第二閘極氧化層；122〜第二 氧化層’ 124〜擴散阻擋材料；126〜控制閘極；128〜低壓閘 極；130〜高壓閘極。In an embodiment, as shown in FIG. 7, the conventional method (for example, deposition of a polysilicon layer, patterning of a material layer, implantation with a source/drain region, etc.) may be performed on the gate stack 102. A control gate 126 is formed on the charge blocking layer, and a low voltage gate 128 and a high voltage gate 130 are formed on the first gate oxide layer Uh and the first gate oxide layer 120a of the low voltage well region 110 and the high voltage well region 112, respectively. Forming a memory element. Since the first interrogation layer and the second gate oxide layer 120a are implanted with a diffusion barrier material (for example, nitrogen/, 'this low voltage gate or a small ion in the high voltage gate (such as boron) will be difficult to wear. When the gate oxide layer reaches the well region, it can ensure that the low-voltage component and the high-voltage component are used. In addition, the memory matrix, the second oxide layer 122 of mi is formed after the diffusion of the Z-material (for example, nitrogen), so that it is not Including nitrogen, not only, in the prior art, the memory efficiency is degraded by the nitridation of the upper oxide layer. The invention has many advantages. Since the thermal method is deliberately selected, the nitride layer 106 is largely oxidized. Therefore, in the conventional technique, the problem that the oxide layer on the charge blocking layer is nitrided is 曰=, and the method of the embodiment of the present invention can be used in the gate oxide layer without using an additional lithography process. Plant diffusion barrier material. Although the preferred embodiment of the present invention has been disclosed as above, to limit the invention, any of the technical fields of the prior art has the general knowledge that it can be added without any departure from the spirit of the present invention. Run 97-012/0492-A41863 - TW / f / 12 1376018 decoration, so the scope of protection of the present invention is defined by the scope of the appended patent application. [Simplified description of the drawings] Figures 1-7 show the fabrication of a semiconductor structure according to an embodiment of the present invention. A series of process profiles. [Main component symbol description] 1~ memory array area; 2~ peripheral area; 100~ substrate; 3~ shallow trench isolation area; 102~ gate stack; 1〇4~ first oxide layer ; 106~ nitride layer; 108~ first shielding layer; 110~ low pressure well region; 112~ high voltage well region; 113~ sacrificial oxide layer; 1U~ initial gate oxide layer; 116~ second shielding layer; 118, 118a ~ first gate oxide layer; U0, 12〇a~ second gate oxide layer; 122~ second oxide layer '124~ diffusion barrier material; 126~ control gate; 128~ low voltage gate; 130~ high voltage gate pole.
97-012/0492-A41863-TW/f/ 1397-012/0492-A41863-TW/f/ 13