TWI474384B - Method of forming semiconductor device - Google Patents

Description

Semiconductor component manufacturing method

The present invention relates to a method of fabricating an electronic component, and more particularly to a method of fabricating a semiconductor device.

In order to reduce the cost and simplify the process steps of semiconductor components, it has become a trend to integrate the components of the memory cell and the peripheral cell on the same wafer, for example, flash memory and logic circuits. The components are integrated on the same chip, which is called embedded flash memory.

In embedded flash memory, the peripheral region often includes a low voltage component region and a high voltage component region. In the conventional process, the thickness of the gate insulating layer of the low-voltage element region is the same as that of the gate insulating layer of the cell region, and the thickness of each is equivalent. However, such a process will limit the performance of the low voltage device region, resulting in poor electrical performance of the embedded flash memory.

In view of the above, the present invention provides a method of fabricating a semiconductor device which can fabricate a gate insulating layer having a relatively thin thickness with respect to a cell region in a low voltage device region to provide good electrical properties of the semiconductor device.

The present invention provides a method of manufacturing a semiconductor device. A substrate is provided. The substrate has a first zone, a second zone, and a third zone. A first insulating layer is formed on at least the substrates of the first region and the second region. Forming a second on the substrate of the third zone Insulation. A zone of inhibition is formed in the substrate of the second zone. The first insulating layer is removed. Forming a third insulating layer on the substrate, wherein a thickness of the third insulating layer on the suppression region is less than a thickness of the third insulating layer in the first region. A layer of conductive material is formed on the substrate. Performing a patterning step of forming a plurality of first gate structures on the substrate of the first region, forming at least one second gate structure on the substrate of the second region, and forming at least a third portion on the substrate of the third region Gate structure.

In one embodiment of the invention, a method of forming the suppression region includes forming a patterned photoresist layer on a substrate to expose a first insulating layer of the second region; and performing a nitrogen implantation process.

In one embodiment of the invention, the implantation dose of the nitrogen implantation process is about 10 ¹³ to 10 ¹⁵ atoms per square centimeter, and the implantation energy is about 13 to 17 KeV.

In one embodiment of the invention, the nitrogen zone has a thickness of between about 10 angstroms and about 90 angstroms.

In an embodiment of the invention, in the step of forming the third insulating layer, nitrogen in the suppression zone is released from the substrate.

In an embodiment of the invention, the method of forming the third insulating layer includes performing a thermal oxidation process.

In an embodiment of the invention, a method of forming the first insulating layer includes forming a layer of insulating material on a substrate; and removing a portion of the insulating material layer to expose a portion of the substrate of the third region, and forming a remaining insulating material layer The first insulating layer.

In an embodiment of the invention, the method of forming the second insulating layer includes performing a thermal oxidation process.

In an embodiment of the invention, the thickness of the third insulating layer in the first region is smaller than the thickness of the second insulating layer.

In an embodiment of the invention, the first region is a cell region, the second region is a low voltage device region, and the third region is a high voltage device region.

Based on the above, when the semiconductor device of the present invention is applied to an embedded flash memory, nitrogen implantation can be performed in the low voltage device region, and then the gate insulating layer of the cell region and the low voltage device region can be fabricated. In this way, a gate insulating layer having a relatively thin thickness with respect to the cell region can be fabricated on the low voltage device region. By using the manufacturing method of the semiconductor device, a thin gate insulating layer of the low voltage device region can be provided without affecting the electrical properties of the cell region, so as to improve the overall performance of the semiconductor device.

The above described features and advantages of the present invention will be more apparent from the following description.

1A through 1H are schematic cross-sectional views of a semiconductor device in accordance with an embodiment of the invention.

First, referring to FIG. 1A, a substrate 100 is provided. The substrate 100 is, for example, a crucible substrate. The substrate 100 has a first region 100a, a second region 100b, and a third region 100c. In addition, the substrate 100 has a plurality of isolation structures (not shown) therein. The isolation structure is, for example, a shallow trench isolation (STI) structure. The first region 100a, the second region 100b, and the third region 100c of the substrate 100 are isolated from each other by an isolation structure. It is to be noted that when the embedded flash memory is manufactured by the manufacturing method of the semiconductor device of the present invention, the first region 100a is, for example, a unit cell. The region, the second region 100b is, for example, a low voltage device region, and the third region 100c is, for example, a high voltage component region, but the invention is not limited thereto.

Then, a layer of insulating material 102 is formed on the substrate 100. The material of the insulating material layer 102 is, for example, cerium oxide, and the method of forming the same includes performing a thermal oxidation method. Thereafter, a mask material layer 104 is formed on the insulating material layer 102. The material of the mask material layer 104 is, for example, tantalum nitride, cerium oxide, cerium oxynitride or a combination thereof. The method of forming the mask material layer 104 includes performing a chemical vapor deposition method or a physical vapor deposition method. Next, a patterned photoresist layer 106 is applied over the mask material layer 104.

Referring to FIG. 1B, a portion of the mask material layer 104 and a portion of the insulating material layer 102 on the substrate 100 of the third region 100c are sequentially removed by using the patterned photoresist layer 106 as a mask to at least the first region 100a and A first insulating layer 102a and a mask layer 104a are formed on the second region 100b, and a portion of the substrate 100 of the third region 100c is exposed. The above removal process includes performing an etching process. Next, the patterned photoresist layer 106 is removed. In an embodiment, the ashing process can be selectively performed to ensure that the patterned photoresist layer 106 is completely removed. In the present embodiment, although the above removal process only removes part of the substrate 100 of the third region 100c, the invention is not limited thereto. In another embodiment, all of the substrate 100 of the third region 100c can also be removed. In this case, the first insulating layer 102a is formed only on the substrate 100 of the first region 100a and the second region 100b.

Furthermore, although the first insulating layer 102a is formed in such a manner as to remove a portion of the insulating material layer 102 in the present embodiment, the present invention does not limit the manner in which the first insulating layer 102a is formed. That is to say, in other embodiments, The first insulating layer 102a is formed directly on the substrate 100 of the first region 100a and the second region 100b in other suitable manners.

Referring to FIG. 1C, a second insulating layer 108 is formed on the substrate 100 of the third region 100c. The method of forming the second insulating layer 108 includes performing a thermal oxidation method. In the present embodiment, the second insulating layer 108 is formed on a portion of the substrate 100 of the third region 100c and extends into the first insulating layer 102a around it due to the bird's beak effect (as shown in FIG. 1C). Moreover, in the present embodiment, although the second insulating layer 108 is formed only on a part of the substrate 100 of the third region 100c, the invention is not limited thereto. In another embodiment, the second insulating layer 108 may also be formed on all of the substrates 100 of the third region 100c. In addition, in the step of forming the third insulating layer 108, an oxide film layer (not shown) is formed on the surface of the mask layer 104a at the same time. In an embodiment, after the step of forming the third insulating layer 108, a wet dip process may be selectively performed to remove the native oxide layer on the surface of the third insulating layer 108. ). The above wet dipping process can also simultaneously remove the oxide film layer on the surface of the mask layer 104a. Thereafter, the mask layer 104a is removed.

Referring to FIG. 1D, a patterned photoresist layer 110 is formed on the substrate 100 to expose the first insulating layer 102a of the second region 100b. Next, a nitrogen implantation process 112 is performed to form a suppression zone 114 in the substrate 100 of the second zone 100b. In particular, although in the present embodiment, the suppression region 114 is formed only in a portion of the substrate 100 of the second region 100b, the invention is not limited thereto. In another embodiment, the suppression region 114 may also be formed in all of the substrates 100 of the second region 100b. The method of forming the suppression zone 114 includes a nitrogen implantation process 112 performed at an implantation dose of about 10 ¹³ to 10 ¹⁵ atoms per square centimeter and an implantation energy of about 13 to 17 KeV. The thickness of the suppression zone 114 is from about 10 angstroms to about 90 angstroms, more preferably from 10 angstroms to 70 angstroms.

Referring to FIG. 1E, the patterned photoresist layer 110 on the substrate 100 is removed. In an embodiment, the ashing process can be selectively performed to ensure that the patterned photoresist layer 110 is completely removed. Next, the first insulating layer 102a is removed to expose the substrate 100 of the first region 100a and the second region 100b. The method of removing the first insulating layer 102a includes performing an etching process.

It is particularly noted that in the present invention, the nitrogen implantation process 112 for forming the suppression region 114 is performed first, and then the first insulating layer 102a is removed. That is, when the second region 100b is subjected to the nitrogen implantation process 112, the first insulating layer 102a on the second region 100b can serve as a buffer layer for protecting the second region 100b to prevent the nitrogen implantation process 112 from destroying the second layer. The surface of the substrate 100 of the region 100b.

Referring to FIG. 1F, a third insulating layer 116 is formed on the substrate 100. The thickness of the third insulating layer 116 on the suppression region 114 is determined because the nitrogen in the suppression region 114 inhibits the growth rate of the third insulating layer 116. Less than the thickness of the third insulating region 116 in the first region 100a. The method of forming the third insulating layer 116 includes performing a thermal oxidation method. In the embodiment, the thickness of the third insulating layer 116 in the first region 100a is smaller than the thickness of the second insulating layer 108.

It is particularly noted that in the step of forming the third insulating layer 116, nitrogen in the suppression region 114 is released from the substrate 100. Therefore, the suppression zone 114 is represented by a broken line in FIG. 1F. Specifically, the third growth in the furnace tube In the step of the edge layer 116, low pressure purge is simultaneously performed, so that nitrogen in the suppression zone 114 is released upward from the substrate 100 instead of being diffused into the substrate 100. From another point of view, it can be considered that in the final completed semiconductor component (as shown in FIG. 1H), no trace or only a small amount of nitrogen is implanted into the nitrogen implanted in the process 112. Therefore, the nitrogen gas implanted in the nitrogen implantation process 112 does not substantially affect the performance of the semiconductor device.

Referring to FIG. 1G, a conductive material layer 118 is formed on the substrate 100. The conductive material layer 118 covers the second insulating layer 108 and the third insulating layer 116 in a comprehensive manner. The material of the conductor material layer 118 is, for example, polycrystalline germanium, and the method of forming the same includes performing a chemical vapor deposition method.

Next, referring to FIG. 1H, a patterning step is performed to form a plurality of first gate structures 120 on the substrate 100 of the first region 100a, and at least one second gate structure 122 on the substrate 100 of the second region 100b. And forming at least one third gate structure 124 on the substrate 100 of the third region 100c. Each of the first gate structures includes a conductor layer 118a and a third insulating layer 116a located below the conductor layer 118a and located in the first region 100a. The second gate structure 122 includes a conductor layer 118b and a third insulating layer 116a located below the conductor layer 118b and in the second region 100b. The third gate structure 124 includes a conductor layer 118c and a second insulating layer 108a therebelow. Thus far, the fabrication of the semiconductor device of the present invention has been completed.

In summary, the present invention forms a suppression zone 114 in the substrate 100 of the second zone 100b. The suppression region 114 can suppress the thickness of the third insulating layer 116 formed by a later process. That is, the thickness of the third insulating layer 116 on the suppression region 114 in the second region 100b is smaller than the third insulating layer 116 in the first region. The thickness of 100a. When the semiconductor device of the present invention is an embedded flash memory, and the first region 100a is a cell region and the second region 100b is a low voltage device region, the method of the present invention can make the thickness of the gate insulating layer of the low voltage device region smaller than The thickness of the gate insulating layer of the cell region. Further, since the manufacturing method of the present invention does not change the thickness of the third insulating layer 116 of any of the first regions 100a (i.e., the cell regions) as compared with the manufacturing method of the prior art. Therefore, the thickness of the gate insulating layer of the low voltage device region can be effectively reduced without affecting the original electrical properties of the cell region to provide good electrical performance of the embedded flash memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

100a‧‧‧First District

100b‧‧‧Second District

100c‧‧‧ Third District

102‧‧‧Insulation layer

102a‧‧‧First insulation

104‧‧‧ Cover material layer

104a‧‧‧ Cover layer

106, 110‧‧‧ patterned photoresist layer

108, 108a‧‧‧Second insulation

112‧‧‧Nitrogen implantation process

114‧‧‧ suppression zone

116, 116a‧‧‧ third insulation layer

118‧‧‧Conductor layer

118a, 118b, 118c‧‧‧ conductor layer

120‧‧‧First gate structure

122‧‧‧Second gate structure

124‧‧‧ Third gate structure

1A through 1H are schematic cross-sectional views of a semiconductor device in accordance with an embodiment of the invention.

100‧‧‧Base

100a‧‧‧First District

100b‧‧‧Second District

100c‧‧‧ Third District

108a‧‧‧Second insulation

114‧‧‧ suppression zone

116a‧‧‧third insulation

118a, 118b, 118c‧‧‧ conductor layer

120‧‧‧First gate structure

122‧‧‧Second gate structure

124‧‧‧ Third gate structure

Claims (10)

A method of fabricating a semiconductor device, comprising: providing a substrate having a first region, a second region, and a third region; forming a first portion on the substrate of the first region and the second region An insulating layer is formed on the substrate of the third region, the second insulating layer is different from the first insulating layer; a suppression region is formed in the substrate of the second region; An insulating layer; a third insulating layer is formed on the substrate, wherein a thickness of the third insulating layer on the suppression region is smaller than a thickness of the third insulating layer in the first region; forming a conductor on the substrate a material layer; and performing a patterning step of forming a plurality of first gate structures on the substrate of the first region, forming at least one second gate structure on the substrate of the second region, and At least one third gate structure is formed on the substrate of the three regions. The method of fabricating a semiconductor device according to claim 1, wherein the method of forming the suppression region comprises: forming a patterned photoresist layer on the substrate to expose the first insulating layer of the second region; And a nitrogen implantation process. The method of manufacturing a semiconductor device according to claim 2, wherein the nitrogen implantation process has an implantation dose of 10 ¹³ to 10 ¹⁵ atoms per square centimeter and an implantation energy of 13 to 17 KeV. The method of manufacturing a semiconductor device according to claim 2, wherein the nitrogen gas region has a thickness of 10 angstroms to 90 angstroms. The method of manufacturing a semiconductor device according to claim 2, wherein in the step of forming the third insulating layer, nitrogen in the suppression region is released from the substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the third insulating layer comprises performing a thermal oxidation method. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the first insulating layer comprises: forming a layer of insulating material on the substrate; and removing a portion of the insulating material layer to expose the layer A portion of the third region of the substrate, the remaining layer of insulating material forming the first insulating layer. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the second insulating layer comprises performing a thermal oxidation method. The method of fabricating a semiconductor device according to claim 1, wherein the thickness of the third insulating layer in the first region is smaller than the thickness of the second insulating layer. The method of manufacturing a semiconductor device according to claim 1, wherein the first region is a cell region, the second region is a low voltage device region, and the third region is a high voltage device region.