J8-0227 28801twf.doc/n 201017869 九、發明說明： 【發明所屬之技術領域】 β本發明是有關於-種積體電路及其製造方法，且特別 是有關於一種半導體元件及其製造方法。 【先前技術】J8-0227 28801 twf.doc/n 201017869 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit and a method of manufacturing the same, and more particularly to a semiconductor device and a method of fabricating the same. [Prior Art]
更多 隨著科技的發展，輕、薄、短、小且多 =市場之主要訴求。為符合此訴求，單—科技產f = 電路所使狀操作縣必纖之減小，且職的電路或是 積體電路晶片（integrated drcuit chip)之數量及麵也變得 ^通常，電壓位準不同的積體電路之間，是藉由電壓位 準位移電路(voltage level shift circuit)來進行電壓位準轉 、〃、t的電壓位準位移電路通常是由低壓元件接受積體 電路内部元件的訊號，然後經由中壓元件傳送到高壓元 件，之後再由高壓元件將訊號輸出。 含，習知的一種電壓位準位移電路中的中壓元件採用和 N壓7L件組成構件且尺寸相同的結構，且中壓元件的閘介 電1的厚度也與高壓元件的閘介電層的厚度相同。然而， 在操作時’中壓元件的飽和電流非常小，效能不佳。此外， 由於般鬲、中屢元件的尺寸較大，因此，所佔用的晶片 的面積也較大’不僅不利於晶片的縮小且需耗費較高的晶 片成本。 【發明内容】 5 ^-0227 28801twf.doc/n 201017869 本發明提供—種铸體元件，其包 壓元件、中壓元件以及低壓元件，ίΪ;』;; 之電壓位準位移電路時具有==應用於咖動器 片上了=導件’其包括形成在單-的晶 ❹ ❿More With the development of technology, light, thin, short, small and more = the main appeal of the market. In order to meet this demand, the single-tech production f = the circuit of the operation of the county must be reduced, and the number of circuits and the surface of the integrated circuit chip (the integrated drcuit chip) become ^, the voltage level Between different integrated circuits, a voltage level shift circuit is used to perform voltage level shifting, and the voltage level shifting circuit of t is usually received by a low voltage component. The signal is then transmitted to the high voltage component via the medium voltage component, and then the signal is output by the high voltage component. The intermediate voltage component in a conventional voltage level shifting circuit adopts a structure of the same size as the N-voltage 7L component, and the thickness of the gate dielectric 1 of the medium voltage component is also the gate dielectric layer of the high voltage component. The thickness is the same. However, the saturation current of the medium voltage component during operation is very small and the performance is not good. In addition, since the size of the sturdy and medium-sized components is large, the area of the occupied wafer is also large, which is not only disadvantageous for the reduction of the wafer but also requires a relatively high wafer cost. SUMMARY OF THE INVENTION 5 ^-0227 28801 twf.doc / n 201017869 The present invention provides a casting element, the pressure component, the medium voltage component and the low voltage component, the voltage level displacement circuit has == Applied to the coffee machine on the sheet = guide 'which includes the wafer formed in a single - ❿
於高$元件的尺寸，因此整個產品的尺寸可以I 易，元件的製輕方法，其製程簡 本發明提供一種半導體元件，包括基底、具有第 =的第—井區、具有第二導電型的高壓元件、具有第二 =的中壓元件及具有第二導電型的低壓元件。基底^ 间聖電路區、中壓電路區以及低壓電路區。第P ，基底中。高壓元件位於高塵電路區上。中壓元件位= 區上。低壓元件位於低壓電路區上。中壓元件之I /、二壓兀件之結構相同，但與低壓元件之結構不同 i ’向壓元件、巾壓元件與低壓元件分·有第-間介雷 二第-閘介電層與第三閘介電層，其中第二閘介電 厚度小於第一閘介電層的厚度。 Θ之 在本發明之一實施例中，上述之第二閘介電層之 /、該第三閘介電層之厚度實質上相等。 又 發明之—實施例中，上述之高、中壓元件分別為 琢休私金氧半導體元件；低壓元件為金氧半電晶體。*'、' 201017869 --------08-0227 28801twf.doc/n 在本發明之一實施例中，上述之高、中、低壓元件均 分別包括閘極結構及具有第二導電型的二源極與汲極區。 閘極結構位於基底上。源極與汲極區位於閘極結構兩側的 基底中二此外，高、中壓元件更分別包括一隔離結構，分 別位於尚、中壓元件的閘極結構與高、中壓元件的二源極 與没極區之一之間的基底中。 在本發明之-實施例中，上述之中壓元件之隔離結構 的寬度小於高壓元件之隔離結構的寬度。 在本發明之-實施例中，上述之高、中壓元件更分別 包^具有第二導電型的二第二井區，其彼此分隔，分別位 於高、中壓元件的各源極與汲極區周圍的第一井區中。 在本發明之-實施例中，上述之高、中、低壓元 分別包括閘極結構及具有第二導電㈣二源極與沒極區。 閘極結構位於基底上。源極與汲極區位於_結構兩側的 基底中。另外，高、中壓元件更分別包括二隔離結構，分 ，位於高、中壓元件的閘極結構與高、中壓树的各源極 與沒極區之間的基底中。 f本發明之—實施财，上述之中壓元件之隔離結構 的見度小於尚壓TG件之隔離結構的寬度。 在本發明之-實施例中，上述之高、中壓元件更分別 ί括m電型的二第二井區，其彼此分隔，分別位 源一以及與其相鄰之隔離結 在本發明之-實施例中，上述之高、中麼元件更分別 J8-0227 28801twf.doc/n 201017869 包括具有第二導電型的二階區及具有第二導電型的二漂移 區。二階區彼此分隔，分別位於高、中壓元件的各源極與 汲極區周圍的第一井區中。二漂移區彼此分隔，分別位於 向、中壓元件的二隔離結構下方，鄰接高、中壓元件的各 階區。 在本發明之一實施例中，上述之第一導電型為p型， 第二導電型為N型；上述之第一導電型為N型，第二導 型為P型。 ❶ 在本發明之一實施例中，上述之高壓元件的電壓操作 範圍例如為大於30伏特。 —在本發明之一實施例中，上述之中壓元件的電壓操作 範圍例如為10〜30伏特。 ' 在本發明之一實施例中，上述之低壓元件的電壓操作 範圍例如為小於10伏特。 本發明提供一種半導體元件，包括基底、高壓元件、 中壓元件及低壓元件。基底包括高壓電路區、中壓電路區 • 以及低壓電路區。高壓元件位於高壓電路區上。中壓元; 位於中壓電路區上。低壓元件位於低壓電路區上。中壓元 件之結構與高壓元件之結構相同，但與低壓元件之結構不 同。另外，高壓元件、中壓元件與低壓元件分別具有第一 閘介電層、第二閘介電層與第三閘介電層，i中 兩F3 、1昂一閘介 電層之厚度小於第一閘介電層的厚度。The size of the component is high, so the size of the entire product can be easy, and the method of manufacturing the component is simple. The invention provides a semiconductor component including a substrate, a first well region having a first conductivity type, and a second conductivity type. A high voltage component, a medium voltage component having a second = and a low voltage component having a second conductivity type. The substrate has a circuit area, a medium voltage circuit area, and a low voltage circuit area. P, in the base. The high voltage component is located on the high dust circuit area. Medium voltage component = area. The low voltage component is located on the low voltage circuit area. The I / and the two pressure components of the medium voltage component have the same structure, but are different from the structure of the low voltage component. i 'the pressure component, the towel pressure component and the low voltage component have the first-intermediate dielectric-second gate dielectric layer and The third gate dielectric layer, wherein the second gate dielectric thickness is less than the thickness of the first gate dielectric layer. In one embodiment of the invention, the thickness of the second gate dielectric layer and the third gate dielectric layer are substantially equal. Further, in the embodiment, the high and medium voltage elements are respectively 琢 私 金 金 ; ; ; ; ;; *', '201017869 --------08-0227 28801twf.doc/n In an embodiment of the invention, the high, medium and low voltage components respectively comprise a gate structure and a second conductivity type The two sources and the bungee area. The gate structure is located on the substrate. The source and the drain regions are located in the substrate on both sides of the gate structure. In addition, the high and medium voltage components respectively comprise an isolation structure, which are respectively located in the gate structure of the intermediate and medium voltage components and the two sources of the high and medium voltage components. In the base between the pole and one of the poleless zones. In an embodiment of the invention, the width of the isolation structure of the medium voltage component is less than the width of the isolation structure of the high voltage component. In the embodiment of the present invention, the high and medium voltage components further comprise two second well regions of the second conductivity type, which are separated from each other, and are respectively located at the source and the drain of the high and medium voltage components. In the first well area around the area. In an embodiment of the invention, the high, medium and low voltage elements respectively comprise a gate structure and a second conductive (four) two source and a non-polar region. The gate structure is located on the substrate. The source and drain regions are located in the substrate on both sides of the _ structure. In addition, the high and medium voltage components further comprise two isolation structures, respectively, located in the gate structure of the high and medium voltage components and the substrate between the source and the non-polar regions of the high and medium pressure trees. f. In the invention, the isolation structure of the medium voltage component is less than the width of the isolation structure of the TG component. In the embodiment of the present invention, the above-mentioned high and medium voltage components are further divided into two second well regions of the m-electric type, which are separated from each other, and the source source 1 and the adjacent junction thereof are in the present invention - In the embodiment, the above-mentioned high and medium components are further respectively J8-0227 28801 twf.doc/n 201017869 includes a second-order region having a second conductivity type and a two-drift region having a second conductivity type. The second-order regions are separated from each other and are located in the first well regions around the source and drain regions of the high and medium voltage components. The two drift regions are separated from each other, respectively under the two isolation structures of the medium and medium voltage components, adjacent to the respective step regions of the high and medium voltage components. In an embodiment of the invention, the first conductivity type is a p-type, and the second conductivity type is an N-type; the first conductivity type is an N-type, and the second conductivity is a P-type. In one embodiment of the invention, the voltage operating range of the high voltage component described above is, for example, greater than 30 volts. - In an embodiment of the invention, the voltage operation range of the medium voltage component is, for example, 10 to 30 volts. In one embodiment of the invention, the voltage operating range of the low voltage component described above is, for example, less than 10 volts. The present invention provides a semiconductor component including a substrate, a high voltage component, a medium voltage component, and a low voltage component. The substrate includes a high voltage circuit region, a medium voltage circuit region, and a low voltage circuit region. The high voltage component is located on the high voltage circuit area. Medium voltage element; located in the medium voltage circuit area. The low voltage component is located on the low voltage circuit area. The structure of the medium voltage component is the same as that of the high voltage component, but is different from the structure of the low voltage component. In addition, the high voltage component, the medium voltage component and the low voltage component respectively have a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, wherein the thickness of the two F3 and 1 ohm gate dielectric layers is smaller than The thickness of a gate dielectric layer.
在本發明之一實施例中，上述之第二閘介電層之 與第三閘介電層之厚度實質上相等。 θ X w^-0227 28801twf,d〇c/n 201017869 在本發明之一實施例中，上述之高、中壓元件分別為 場漂移互補式金氧半導體元件；低壓元件為互補式金氧半 電晶體。 本發明提供一種半導體元件的製造方法。首先，提供 一基底，基底其包括高壓電路區、中壓電路區以及低壓電 路區。接著，於尚壓電路區、中壓電路區以及低壓電路區 的基底中形成具有第-導電型之第一井區。然後，於高壓 冑路區、中壓電路區之第-井區中形成具有第二導電型之 ^一井區，其彼此分隔。之後，於高壓電路區'中壓電路 區之各第二井區中分別形成二隔離結構，其彼此分隔。繼 之，於高壓電路區、中壓電路區與低壓電路區上形成第— 閘介電層。接著’移除中壓電路區與低壓電路區之第一閉 介電層。然後，於中壓電路區與低壓電路區上分別形成第 二閘介電層，第二閘介電層的厚度小於第一閘介電層的厚 度。之後，於鬲壓電路區之第一閘介電層以及中壓電路區 以及低壓電路區之各第二閘介電層上分別形成閘極。繼之， Φ 於高壓電路區與中壓電路區之各閘極兩侧的第二井區中以 及低壓電路區之閘極兩側的第-井區中分別形成二源極與 >及極區。 在本發明之一實施例中，上述之第一導電型為？型， 第二導電型為N型；上述之第一導電型為N型，第二導 型為P型。 —“ 在本發明之一實施例中，上述之移除中壓電路區與低 壓區上之第一閘介電層的方法包括以下步驟。首先，^基 ϋδ-0227 28801twf.doc/n 201017869 底上形成光阻層’光阻層具有二開口，分別裸露出中屋電 路區與低壓區上之第一閘介電層。接著，進行蝕刻製程， 移除中壓電路區與低壓區上之第一閘介電層。然後，移除 光阻層。 、承 本發明之半導體元件的中壓元件具有較高之飽和電 流，應用於閘極驅動器之電壓位準位移電路時具有較高之 效能。此外，本發明之半導體元件的中壓元件的尺寸小於 高壓元件的尺寸，因此整個產品的尺寸可以大幅縮小。另 外，本發明之半導體元件的製造方法，其製程簡易，成本 低，且符合市場需求。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖1疋依照本發明實施例所繪示之一種半導體元件的 _ 剖面示意圖。 請參照圖1 ’本發明實施例之半導體元件1〇包括具有 第一導電型之基底12或具有第一導電型之第—井區14之 基底12、具有第二導電型之高壓元件2〇〇、具有第二導電 型之中壓元件300與具有第二導電型之低壓元件4〇〇。在 本發明實施例中，是以具有第一導電型之第一井區14之基 底12來說明之。第一導電型和第二導電型為具有不同導電 型者，其可以分別為N型或是P型。 ^6-0227 28801twf.doc/n 201017869 基底12之材質可以是半導體材料例如是矽。基底12 包括尚壓電路區20、中壓電路區3〇以及低壓電路區40。 而本發明實施例之半導體元件1〇的高壓元件2〇〇、中壓元 件300與低壓元件4〇〇 ’則分別位於高壓電路區2〇、中壓 電路區3〇以及低壓電路區4〇上。本發明之半導體元件1〇 的兩壓元件200、中壓元件3〇〇與低壓元件4〇〇之間可以 設置隔離結構16以彼此隔絕之。 ❿ 請繼續參照圖1 ’本發明實施例之高壓元件200可以 例如是場漂移金氧半導體（field drift metal 〇xide semiconductor ’ FDMOS)元件，但不以此為限，其操作電 壓，如是大於30伏特。更具體地說，高壓元件2〇〇包括具 有第二導電型通道之金氧半電晶體2〇2、隔離結構2〇4a、 %4b以及具有第二導電型之兩個第二井區206a、206b。金 氧半電晶體202包括閘極結構2〇8與二源極與汲極區 =〇a、210b。閘極結構2〇8包括閘介電層212以及位於閘 介電層212上的閘極214。閘介電層212的材質例如是氧 • 化石夕。閘極214之材質例如是摻雜多晶石夕。二源極與汲極 區210a、210b，為具有第二導電型之摻雜區，其二者分別 位於閘極結構208兩侧的第二井區206a、206b中。此處的 源極與没極區210a、210b是指在某種電塵操作條件之下， 其中第一個源極與汲極區21〇a做為源極區；第二個源極與 汲極區210b則做為没極區’但，在另一種電壓操作條件之 广個源極與汲極區21〇a做為汲極區；第二個源極與 /玉區21〇b則做為源極區。隔離結構204a、204b的寬度 11 201017869 wiyi.v^j_>-^v08-0227 28801tvvf.doc/n 為Ll ’其分別設置於閘極結構208與各個源極與汲極區 210a、210b之間的第二井區206a、2〇6b中。隔離結構204a' 204b與第二井區206a、206b可用以減缓熱載子效應，以 增加源極與汲極區210a、210b的崩潰電壓。在一些實施例 中’高壓元件200還可以具有第二導電型之埋層205，位 於第一井區14與第二井區206a、206b下方的基底12中。 此外，高壓元件200還可以包括二個具有第一導電型的摻 0 雜區216a、216b，位於第一井區14中’且各摻雜區216a、 216b與各源極與汲極區2l〇a、21〇b分別以隔離結構218a、 218b分隔開。 請繼續參照圖1，本發明實施例之低壓元件400的操 作電壓例如是小於10伏特，其可以例如是金氧半導體，但 不以此為限。更具體地說，低壓元件4〇〇包括具有第二導 電型通道之金氧半電晶體402。金氧半電晶體402包括閘 極結構408與二源極與沒極區410a、410b。閘極結構408 包括閘介電層412以及位於閘介電層412上的閘極414。 β 閘介電層的材質例如是氧化石夕。閘極414之材質例如是摻 雜多晶矽。二源極與汲極區410a、410b，分別位於閘極結 構408兩侧的第一井區14中。源極與汲極區41〇a、41% 分別包括具有第二導電型之濃摻雜區411a、411b與淡摻雜 區409a、409b。此處的源極與汲極區4l〇a、410b是指在 某種電壓操作之下，其中第一個源極與汲極區41〇a做為源 極區；第二個源極與汲極區410b則做為汲極區，但，在另 一種電壓操作之下，第一個源極與汲極區41〇a做為汲極 12 201017869 08-0227 28801twf.doc/n 區；第二個源極與没極區410b則做為源極區。 換言之，在本發明實施例中，低壓元件4〇〇與高壓元 件200的結構不同。此處所述的結構不同是指組成的構件 不同。更具體地說，本實施例中低壓元件400的兩個源極 與汲極區410a、410b與閘極結構408之間並不包括兩個隔 離結構’且在第一井區14中並不包括兩個具有第二導電型 之第二井區。而且低壓元件400的閘介電層412的厚度遠 ❿ 小於高壓元件200的閘介電層212的厚度。 請繼續參照圖1，本發明實施例之中壓元件3〇〇可以 例如是場漂移金氧半導體元件，但不以此為限，其操作電 壓例如是10〜30伏特。更具體地說，中壓元件3〇〇包括具 有第二導電型通道之金氧半電晶體3〇2、隔離結構3〇4/、、 =)4b以及具有第二導電型之兩個第二井區3〇如、3〇你。金 氧半電晶體302包括閘極結構3〇8與二源極與没極區 310a、3娜。閘極結構308包括閘介電層312以及位於閑 介電層312上的閘極3M。閘介電層312的材質例如是氧 化石夕。閘極3U之材質例如是摻雜多晶石夕。二源極與沒極 區310a、31%，為具有第二導電型之推雜區，其二者分別 位於閘極結構308兩側的第二井區3〇6a、3〇6b +。此處的 =與没極區31Ga、3勘是指在某種電壓操作條件之下， 厂中第-個源極與沒極區31〇a做為源極區；第二個源極與 =虽區310b則做為汲極區’但，在另一種電麗操作條件之 二弟-個源極與汲極區31Ga做為雜區；第二個源極與 極區憑則做為源極區。隔離結構304a、304b的寬度 13 J8-0227 28801twf.doc/n 201017869 為L2，其分別設置於閘極結構3〇8與各個源極與汲極區 310a、310b之間的弟二井區306a、306b中。隔離結構304a、 304b與第二井區306a、306b可用以減緩熱載子效應，以 增加源極與汲極區310a、310b的崩潰電壓。在一些實施例 中，中壓元件300還可以具有第二導電型之埋層3〇5，位 於第一井區14與第二井區306a、306b下方的基底12中。 此外，中壓元件300還可以包括二個具有第一導電型的掺 ❹ 雜區316a、316b’位於第一井區14中，且各摻雜區316a、 316b與各源極與汲極區3l〇a、310b分別以隔離結構318a、 318b分隔開。 換言之，本發明實施例之中壓元件3〇〇與低壓元件4〇〇 之結構不同，但是，中壓元件3〇〇的閘介電層312的厚度 與低壓元件400的閘介電層412的厚度大致相同。另一方 面，本發明實施例之中壓元件300與高壓元件2〇〇具有相 同的結構，但是，不同的是中壓元件3〇〇的閘介電層312 的厚度遠小於高壓元件200的閘介電層212的厚度。另外， ❹ 中壓元件300的隔離結構304a、304b的寬度L2小於高壓 元件200的隔離結構204a、204b的寬度L1。此處所述的 結構不同是指組成的構件不同；而結構相同，則是指組成 的構件相同，但，尺寸不一定相同。 由於本發明實施例之中壓元件300的閘介電層312的 厚度與低壓元件200的閘介電層212的厚度相當，因此， 相較於使用較厚之閘介電層的中壓元件，本發明實施例之 中壓元件300可以提供較大的飽和電流，約為2 5至5倍， 14 201017869 umv.iy-xv08-0227 28801twf.doc/n 因此，本發明之半導體元件10應用於閘極驅動器之電壓位 準位移電路時具有較高的效能。 此外，由於中壓元件300可以提供較大的飽和電流， 因此，其隔離結構304a、304b的寬度可以L2縮小。另一 方面’由於中壓元件300所需的隔離結構304a、304b的寬 度可以大幅縮小，因此’可以有效縮小中壓元件3〇〇的尺 寸。 ❹ 再者，由於高壓元件200、中壓元件300以及低壓元 件400可以同時形成在單一的晶片上，因此整個產品的尺 寸可以大幅縮小。 請參照圖1，在以上的實施例中，高壓元件2〇〇的源 極與没極區210a、210b與中壓元件300的源極與沒極區 310a、310b是指在某種電壓操作條件之下，其中第一個源 極與;及極區210a、310a做為源極區；第二個源極與没極區 210b、310b則做為沒極區，但，在另—種電壓操作條件之 下，第一個源極與汲極區210a、310a做為汲極區；第二個 ❹ 源極與汲極區21〇b、310b則做為源極區。因此，兩個源極 與〉及極區210a、210b、310a、310b與閘極結構208、308 之間均形成了隔離結構204a、204b、304a、304b，使得高 壓元件200與中壓元件300均分別呈對稱之結構。然而间 在另-個實施例中，若是區域21%、31%固定做為汲極 區；而區域210a、310a固定做為源極區，則僅需在做為汲 極區的區域210b、310b與閘極結構2〇8、3〇8之間設置隔 離結構204b、304b ;而選擇性在做為源極區的區域21〇&、 υ〇-0227 2880Itwf.doc/n 201017869 3l〇a與閘極結構208、308之間設置隔離結構2〇4a、3〇4&。 如圖2所示者，高壓元件200與中壓元件3〇〇均只有在做 為汲極區的區域210b、310b與閘極結構2〇8、308之間設 置隔離結構204b、304b，使其分別呈不對稱之結構。 此外，在以上的實施例是具有第一導電型之基底12 或具有第一導電型之第一井區14之基底12、具有第二導 電型之尚壓元件200、具有第二導電型之中壓元件3〇〇與 具有第一導電型之低塵元件400來說明本發明之半導體元 件10。然而，本發明之半導體元件並不以此為限，高壓元 件200、中壓元件3〇〇及低壓元件4〇〇均可以同時具有第 一導電型之元件與第二導電型之元件。舉例來說，高壓元 件200例如是同時包括FD NM〇s元件以及FD pM〇s元 件的FD CMOS元件，中壓元件300例如是同時包括jpD NMOS元件以及FD PMOS元件的FD CM〇s元件，而低 壓元件400例如是同時包括NM〇s電晶體以及pM〇s電 晶體的CMOS電晶體，.如圖5所示。 ❹ 此外，在以上的實施例中的高壓元件200與中壓元件 300均是以FD MOS元件說明之，但，本發明並不以此為 限。高壓元件200與中壓元件300在不脫離本發明的精神 範圍内，當可依據實際的需要作些許之更動與潤飾。例如， 請參照圖3與圖1，圖1高壓元件2〇〇中具有第二導電型 的第二井區206a、206b可分別變更為具有第二導電型的階 區220a與漂移區222a以及具有第二導電型的階區22〇b 與漂移區222b。中壓元件3〇〇中具有第二導電型的第二井 16 iM-0227 28801twf.doc/n 201017869 區306a、306b可分別變更為具有第二導電型的階區32〇a 與漂移區322a以及具有第二導電型的階區32〇b與漂移區 322b。階區220a、220b、320a、320b分別位於源極與汲極 區210a、210b、310a、310b的周圍的第一井區14中。漂 移區 222a、222b、322a、322b 則與階區 220a、220b、320a、 320b電性耦接，位於隔離結構2〇4a、2〇牝、3〇4a、3〇仆 的下方。In one embodiment of the invention, the thickness of the second gate dielectric layer and the third gate dielectric layer are substantially equal. θ X w^-0227 28801 twf, d〇c/n 201017869 In one embodiment of the invention, the high and medium voltage components are field drift complementary MOS devices; the low voltage components are complementary MOSs Crystal. The present invention provides a method of manufacturing a semiconductor device. First, a substrate is provided which includes a high voltage circuit region, a medium voltage circuit region, and a low voltage circuit region. Next, a first well region having a first conductivity type is formed in the substrate of the voltage circuit region, the medium voltage circuit region, and the low voltage circuit region. Then, a well region having a second conductivity type is formed in the first well region of the high voltage bypass region and the medium voltage circuit region, which are separated from each other. Thereafter, two isolation structures are formed in each of the second well regions of the medium voltage circuit region of the high voltage circuit region, which are separated from each other. Then, a first gate dielectric layer is formed on the high voltage circuit region, the intermediate voltage circuit region, and the low voltage circuit region. Next, the first closed dielectric layer of the medium voltage circuit region and the low voltage circuit region is removed. Then, a second gate dielectric layer is formed on the intermediate voltage circuit region and the low voltage circuit region, and the thickness of the second gate dielectric layer is smaller than the thickness of the first gate dielectric layer. Thereafter, a gate is formed on each of the first gate dielectric layer and the intermediate voltage circuit region of the rolling circuit region and each of the second gate dielectric layers of the low voltage circuit region. Then, Φ forms a second source and a > respectively in the second well region on both sides of each gate of the high voltage circuit region and the medium voltage circuit region and in the first well region on both sides of the gate of the low voltage circuit region; Polar zone. In an embodiment of the invention, the first conductivity type is ? The second conductivity type is N type; the first conductivity type is N type, and the second type is P type. - "In one embodiment of the invention, the above method of removing the first thyristor layer on the medium voltage circuit region and the low voltage region comprises the following steps. First, ^ ϋ δ-0227 28801 twf.doc/n 201017869 Forming a photoresist layer on the bottom. The photoresist layer has two openings, respectively exposing the first gate dielectric layer on the middle and low voltage regions. Then, an etching process is performed to remove the medium voltage circuit region and the low voltage region. The first gate dielectric layer. Then, the photoresist layer is removed. The medium voltage component of the semiconductor component of the invention has a high saturation current, and is applied to a voltage level shift circuit of the gate driver. In addition, the size of the medium voltage element of the semiconductor element of the present invention is smaller than the size of the high voltage element, so that the size of the entire product can be greatly reduced. In addition, the manufacturing method of the semiconductor element of the present invention is simple in process, low in cost, and conforms to The above and other objects, features and advantages of the present invention will become more <RTIgt; 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. Referring to FIG. 1 , a semiconductor device 1 of the embodiment of the present invention includes a substrate 12 having a first conductivity type or has a first embodiment. a substrate 12 of a conductive type first well region 14, a high voltage element 2A having a second conductivity type, a medium voltage element 300 having a second conductivity type, and a low voltage element 4 having a second conductivity type. In the embodiment, the substrate 12 having the first well region 14 of the first conductivity type is illustrated. The first conductivity type and the second conductivity type are different conductivity types, which may be N-type or P-type, respectively. ^6-0227 28801twf.doc/n 201017869 The material of the substrate 12 may be a semiconductor material such as germanium. The substrate 12 includes a voltage circuit region 20, a medium voltage circuit region 3A, and a low voltage circuit region 40. The high-voltage element 2〇〇, the medium-voltage element 300 and the low-voltage element 4〇〇' of the semiconductor element 1 are respectively located in the high-voltage circuit region 2〇, the intermediate voltage circuit region 3〇, and the low-voltage circuit region 4〇. Two voltages of the semiconductor element 1〇 The isolation structure 16 may be disposed between the device 200, the medium voltage component 3A and the low voltage component 4A to be isolated from each other. ❿Continuously referring to FIG. 1 'The high voltage component 200 of the embodiment of the present invention may be, for example, a field drift MOS. (field drift metal 〇xide semiconductor ' FDMOS) component, but not limited thereto, the operating voltage is, for example, greater than 30 volts. More specifically, the high voltage component 2 〇〇 includes a gold oxide half-electricity having a second conductivity type channel Crystal 2〇2, isolation structure 2〇4a, %4b, and two second well regions 206a, 206b having a second conductivity type. The MOS transistor 202 includes a gate structure 2〇8 and two source and drain electrodes Area = 〇a, 210b. The gate structure 2〇8 includes a gate dielectric layer 212 and a gate 214 on the gate dielectric layer 212. The material of the gate dielectric layer 212 is, for example, oxygen/fossil. The material of the gate 214 is, for example, doped polysilicon. The two source and drain regions 210a, 210b are doped regions having a second conductivity type, which are respectively located in second well regions 206a, 206b on either side of the gate structure 208. The source and the non-polar regions 210a, 210b herein are under some electric dust operating conditions, wherein the first source and the drain region 21〇a are used as the source region; the second source and the drain are The polar region 210b is used as the non-polar region' However, in a wide range of voltage operating conditions, the source and the bungee region 21〇a are used as the bungee region; the second source and the /Yu region 21〇b are It is the source area. The width of the isolation structures 204a, 204b is 11 201017869 wiyi.v^j_>-^v08-0227 28801tvvf.doc/n is Ll' which is respectively disposed between the gate structure 208 and the respective source and drain regions 210a, 210b. In the second well area 206a, 2〇6b. Isolation structures 204a' 204b and second well regions 206a, 206b may be used to mitigate the hot carrier effect to increase the breakdown voltage of the source and drain regions 210a, 210b. In some embodiments, the high voltage component 200 can also have a buried layer 205 of a second conductivity type in the substrate 12 below the first well region 14 and the second well region 206a, 206b. In addition, the high voltage component 200 can further include two doped regions 216a, 216b having a first conductivity type, located in the first well region 14 and each doped region 216a, 216b and each source and drain region 2l a, 21〇b are separated by isolation structures 218a, 218b, respectively. Continuing to refer to FIG. 1, the operating voltage of the low voltage component 400 of the embodiment of the present invention is, for example, less than 10 volts, which may be, for example, a MOS semiconductor, but is not limited thereto. More specifically, the low voltage component 4A includes a MOS transistor 402 having a second conductive type via. The MOS transistor 402 includes a gate structure 408 and two source and gate regions 410a, 410b. The gate structure 408 includes a gate dielectric layer 412 and a gate 414 on the gate dielectric layer 412. The material of the β-gate dielectric layer is, for example, oxidized stone. The material of the gate 414 is, for example, doped polysilicon. The two source and drain regions 410a, 410b are respectively located in the first well region 14 on either side of the gate structure 408. The source and drain regions 41A, 41% respectively include concentrated doped regions 411a, 411b and lightly doped regions 409a, 409b having a second conductivity type. The source and drain regions 4l〇a, 410b herein refer to a certain voltage operation, wherein the first source and the drain region 41〇a are used as the source region; the second source and the drain are The polar region 410b is used as the drain region, but under another voltage operation, the first source and the drain region 41〇a are used as the bungee 12 201017869 08-0227 28801twf.doc/n region; The source and the immersion area 410b are used as the source area. In other words, in the embodiment of the present invention, the structure of the low voltage element 4 is different from that of the high voltage element 200. The structural differences described herein refer to the different components of the composition. More specifically, in the present embodiment, the two source and drain regions 410a, 410b of the low voltage component 400 do not include two isolation structures between the gate structures 408 and are not included in the first well region 14. Two second well regions having a second conductivity type. Moreover, the thickness of the gate dielectric layer 412 of the low voltage component 400 is much less than the thickness of the gate dielectric layer 212 of the high voltage component 200. Continuing to refer to FIG. 1 , the voltage element 3 〇〇 in the embodiment of the present invention may be, for example, a field-drift MOS device, but not limited thereto, and the operating voltage is, for example, 10 to 30 volts. More specifically, the medium voltage element 3A includes a gold oxide semiconductor transistor 3 having a second conductivity type channel, an isolation structure 3〇4/, , =) 4b, and two seconds having a second conductivity type. Well area 3, such as 3, you. The MOS transistor 302 includes a gate structure 3〇8 and two source and no-pole regions 310a and 3a. The gate structure 308 includes a gate dielectric layer 312 and a gate 3M on the dummy dielectric layer 312. The material of the gate dielectric layer 312 is, for example, oxidized oxide. The material of the gate 3U is, for example, doped polycrystalline stone. The two source and the non-polar regions 310a and 31% are the second conductivity type doping regions, which are respectively located in the second well regions 3〇6a and 3〇6b+ on both sides of the gate structure 308. Here, the = and the immersion zone 31Ga, 3 survey means that under certain voltage operating conditions, the first source and the non-polar region 31〇a are used as the source region; the second source and = Although zone 310b is used as the bungee zone, 'the other source and the bungee zone 31Ga are used as the miscellaneous zone. The second source and the polar zone are used as the source. Area. The width 13 J8-0227 28801 twf.doc/n 201017869 of the isolation structures 304a, 304b is L2, which are respectively disposed between the gate structure 3〇8 and the dipole regions 306a and 306b between the respective source and drain regions 310a and 310b. in. Isolation structures 304a, 304b and second well regions 306a, 306b may be used to mitigate the hot carrier effect to increase the breakdown voltage of the source and drain regions 310a, 310b. In some embodiments, the medium voltage component 300 can also have a buried layer 3〇5 of a second conductivity type in the substrate 12 below the first well region 14 and the second well region 306a, 306b. In addition, the medium voltage component 300 may further include two doped regions 316a, 316b' having a first conductivity type located in the first well region 14, and each doped region 316a, 316b and each source and drain region 3l 〇a, 310b are separated by isolation structures 318a, 318b, respectively. In other words, in the embodiment of the present invention, the structure of the piezoelectric element 3 is different from that of the low voltage element 4, but the thickness of the gate dielectric layer 312 of the medium voltage element 3 is the same as that of the gate dielectric layer 412 of the low voltage element 400. The thickness is approximately the same. On the other hand, in the embodiment of the present invention, the piezoelectric element 300 has the same structure as the high voltage element 2, but the difference is that the thickness of the gate dielectric layer 312 of the medium voltage element 3 is much smaller than that of the high voltage element 200. The thickness of the dielectric layer 212. Further, the width L2 of the isolation structures 304a, 304b of the ❹ medium voltage element 300 is smaller than the width L1 of the isolation structures 204a, 204b of the high voltage element 200. The difference in structure described here means that the components are different; and the structure is the same, the components are the same, but the dimensions are not necessarily the same. Since the thickness of the gate dielectric layer 312 of the piezoelectric element 300 is equivalent to the thickness of the gate dielectric layer 212 of the low voltage component 200 in the embodiment of the present invention, compared to the medium voltage component using a thicker gate dielectric layer, In the embodiment of the present invention, the medium voltage element 300 can provide a large saturation current, which is about 25 to 5 times. 14 201017869 umv.iy-xv08-0227 28801twf.doc/n Therefore, the semiconductor device 10 of the present invention is applied to the gate. The voltage level displacement circuit of the pole driver has higher performance. In addition, since the medium voltage element 300 can provide a large saturation current, the width of its isolation structures 304a, 304b can be reduced by L2. On the other hand, since the widths of the isolation structures 304a, 304b required for the medium voltage element 300 can be greatly reduced, the size of the medium voltage element 3 can be effectively reduced. Further, since the high voltage element 200, the medium voltage element 300, and the low voltage element 400 can be simultaneously formed on a single wafer, the size of the entire product can be greatly reduced. Referring to FIG. 1, in the above embodiment, the source and the non-polar regions 210a, 210b of the high voltage component 2 and the source and the gate regions 310a, 310b of the medium voltage component 300 refer to a certain voltage operating condition. Below, the first source and the; and the polar regions 210a, 310a as the source region; the second source and the non-polar region 210b, 310b as the non-polar region, but in another voltage operation Under the condition, the first source and drain regions 210a, 310a are used as the drain regions; the second source and drain regions 21〇b and 310b are used as the source regions. Therefore, isolation structures 204a, 204b, 304a, and 304b are formed between the two source and > and pole regions 210a, 210b, 310a, and 310b and the gate structures 208, 308 such that the high voltage component 200 and the medium voltage component 300 are both They are symmetrical structures. However, in another embodiment, if the regions 21% and 31% are fixed as the drain regions; and the regions 210a and 310a are fixed as the source regions, only the regions 210b and 310b serving as the drain regions are required. Isolation structures 204b, 304b are provided between the gate structures 2〇8 and 3〇8; and the regions 21〇&, υ〇-0227 2880Itwf.doc/n 201017869 3l〇a are selectively selected as the source regions. Isolation structures 2〇4a, 3〇4& are provided between the gate structures 208, 308. As shown in FIG. 2, the high voltage element 200 and the medium voltage element 3 are provided with isolation structures 204b, 304b only between the regions 210b, 310b as the drain regions and the gate structures 2A, 308, 308. They are respectively asymmetric structures. Further, in the above embodiment, the substrate 12 having the first conductivity type or the substrate 12 having the first well region 14 of the first conductivity type, the voltage-receiving element 200 having the second conductivity type, and the second conductivity type are included. The piezoelectric element 10 of the present invention will be described with respect to the piezoelectric element 3 and the low-dusting element 400 having the first conductivity type. However, the semiconductor device of the present invention is not limited thereto, and the high voltage element 200, the medium voltage element 3A, and the low voltage element 4A may have both the first conductivity type element and the second conductivity type element. For example, the high voltage component 200 is, for example, an FD CMOS component including both a FD NM〇s component and an FD pM〇s component, and the medium voltage component 300 is, for example, an FD CM〇s component including both a jpD NMOS component and an FD PMOS component. The low voltage element 400 is, for example, a CMOS transistor including both an NM〇s transistor and a pM〇s transistor, as shown in FIG. Further, the high voltage element 200 and the medium voltage element 300 in the above embodiments are all described as FD MOS elements, but the invention is not limited thereto. The high voltage component 200 and the medium voltage component 300 can be modified and retouched according to actual needs without departing from the spirit of the invention. For example, referring to FIG. 3 and FIG. 1, the second well regions 206a, 206b having the second conductivity type in the high voltage device 2A of FIG. 1 can be changed to the second region 220a and the drift region 222a having the second conductivity type, respectively. The second conductivity type step region 22b and the drift region 222b. The second well 16 having the second conductivity type among the medium voltage elements 3 i iM-0227 28801 twf.doc/n 201017869 regions 306a, 306b can be changed to the second region of the second conductivity type 32a and the drift region 322a, respectively The step region 32〇b and the drift region 322b of the second conductivity type. The step regions 220a, 220b, 320a, 320b are located in the first well region 14 around the source and drain regions 210a, 210b, 310a, 310b, respectively. The drift regions 222a, 222b, 322a, 322b are electrically coupled to the step regions 220a, 220b, 320a, 320b, and are located below the isolation structures 2〇4a, 2〇牝, 3〇4a, 3〇.
依圖1以及圖2纷示之對稱以及非對稱之 元件製作厚度分別為150埃以及850埃的閘介電層之中壓 元件，並在閘極施加5伏特電壓’在汲極施加2〇伏特電壓 以測1其電性，結果如表1所示。 ❿ 表1 FD NMOS 元件 對稱結構 參數 啟始電壓 崩潰電| 飽和電流 啟始電壓 150埃的 閘介電| 0.68伏特 44伏特 1.55毫安培 850埃的 閘介電層 1.0伏特 60伏特 〇·6毫安培 不對稱結構 0.72伏特 崩潰電壓 1·7伏特 37伏特 50伏特 --安培 ~ 由表1的結果顯示， :，、、15〇埃’可以使得對稱的巾壓元件的飽和電流提升^ 倍；使得補帽元件龍和電流提升5倍。此外.， 150埃的閘介電制帽元件崩潰電壓仍有37伏特以上， 17 201017869〇 -0227 28801twf.doc/n 符合閘極驅動器之電壓位準位移電路之需求。 圖4A至4D疋依據本發明實施例所纟會示之一種半導體 元件的製造流程剖面示意圖。 請參照圖4A，提供基底12,基底例如是p型矽基 底或是N型矽基底。基底12包括高壓電路區2〇、中壓電 路區30以及低壓電路區4〇。接著，在基底p的高壓電路 區20、中壓電路區30以及低壓電路區4〇中形成具有第一 導電型之第一井區14。然後，在高壓電路區2〇 ^第一井 區14中形成具有弟一導電型的第二井區2〇6a、2〇6b，並 在中壓電路區30的第一井區η中形成具有第二導電型的 第二井區306a、306b。在一實施例中，第一井區14與第 二井區206a、206b、306a、306b的形成方法可以分別=具 有第‘皂型之離子植入製程以及具有第二導電型之離子 植入製程直接形成在基底12之中。在另一實施例中，第一 ，區14與第二井區206a、206b、306a、306b的形成方法 可以先在基底12表面上先形成一層具有第一導電型之磊 藝 ^ ’再進行具有第二導電型之離子植人製程，以在蟲晶 層中形成第-井區14與第二井區2〇6a、施b、3嶋、纖。 具有第-導電型之蟲晶層的形成方法例如是以化學氣相沈 積法沈積非晶石夕材料層並在沈積時臨場摻雜第-導電型離 子，之後，再對非晶矽材料層進行固相磊晶製程。 在一些實施例中，在形成第一井區14之前，還會在高 f電路區20、中壓電路區30中預定形成第一井㊣14的下 方形成具有第二導電型之埋層2〇5、3〇5。之後，在基底12 18 J-0227 28801twf.doc/n J-0227 28801twf.doc/n 。罩幕層18例如是由依 冬以及氮化矽層22所組 上形成罩幕層18’定義出主動區。 序堆豐在基底12上的塾氧化層％ 成0According to the symmetrical and asymmetrical components shown in FIG. 1 and FIG. 2, a dielectric layer of a gate dielectric layer having a thickness of 150 angstroms and 850 angstroms, respectively, and a voltage of 5 volts applied to the gate are applied, and 2 volts is applied to the drain. The voltage was measured for its electrical properties, and the results are shown in Table 1. ❿ Table 1 FD NMOS component symmetrical structure parameters start voltage collapse | saturation current start voltage 150 amp gate dielectric | 0.68 volts 44 volts 1.55 mA 850 ohms gate dielectric layer 1.0 volts 60 volts 6 6 amps Asymmetric structure 0.72 volts breakdown voltage 1·7 volts 37 volts 50 volts - ampere ~ The results of Table 1 show that :,,, 15 〇 ' can increase the saturation current of the symmetrical wiper element by a factor of two; The cap element dragon and current are increased by 5 times. In addition, the breakdown voltage of the gate dielectric cap component of 150 angstroms is still more than 37 volts, 17 201017869 〇 -0227 28801 twf.doc/n meets the requirements of the voltage level shift circuit of the gate driver. 4A to 4D are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. Referring to Figure 4A, a substrate 12 is provided, such as a p-type germanium substrate or an N-type germanium substrate. The substrate 12 includes a high voltage circuit region 2, a medium voltage circuit region 30, and a low voltage circuit region 4A. Next, a first well region 14 having a first conductivity type is formed in the high voltage circuit region 20, the intermediate voltage circuit region 30, and the low voltage circuit region 4A of the substrate p. Then, a second well region 2〇6a, 2〇6b having a conductivity type is formed in the first well region 14 of the high voltage circuit region 2, and is formed in the first well region η of the medium voltage circuit region 30. A second well region 306a, 306b having a second conductivity type. In one embodiment, the first well region 14 and the second well region 206a, 206b, 306a, 306b may be formed by an ion implantation process having a first soap type and an ion implantation process having a second conductivity type, respectively. Formed directly in the substrate 12. In another embodiment, the first, the region 14 and the second well region 206a, 206b, 306a, 306b may be formed by first forming a layer of the first conductivity type on the surface of the substrate 12. The second conductivity type ion implantation process is to form the first well region 14 and the second well region 2〇6a, apply b, 3嶋, and fiber in the crystal layer. The method for forming a parasitic layer having a first conductivity type is, for example, depositing an amorphous layer of a stellite material by chemical vapor deposition and doping a first-conducting type ion on the surface during deposition, and then performing a layer on the amorphous bismuth material. Solid phase epitaxial process. In some embodiments, before the formation of the first well region 14, a buried layer 2 having a second conductivity type is also formed under the predetermined formation of the first well 14 in the high f circuit region 20, the medium voltage circuit region 30. 〇 5, 3 〇 5. After that, the substrate is 12 18 J-0227 28801 twf.doc/n J-0227 28801 twf.doc/n. The mask layer 18 defines an active region, for example, by forming a mask layer 18' on the group of the winter and tantalum nitride layers 22. The proportion of the niobium oxide layer on the substrate 12 is 0.
第一導.電型之场植入區(未'繪'示）。然後 曾’以做為隔離結構 304b、318a、318b。 318b下方形成具有 ’在高壓電路區20、 / …、丨又，π冋%、 中壓電路㈣以及低壓電路區4G所裸露絲底12表面上 形成閘介電層212。閘介電層犯的形成方法例如是進行 熱氧化製程，⑽餘切層，氧切層的厚度約為85〇 埃。之後’進行啟始電壓調整步驟。其後，在閘介電層212 上形成光阻層26，光阻層26覆蓋住轉電路區2()上的間 ;ι電層212，且光阻層26具有兩個開口 28、32，分別裸露 出中壓電路區30以及低壓電路區4〇上的閉介電層212。 其後，請參照圖4C，將開口 28、32所裸露出的閘介 電層212移除，裸露出中墨電路區30以及低壓？路區4〇 的基底12表面。移除開口 28、32所裸露出的閘介電層212 的^法可以以氫氟酸浸蝕之。之後，移除光阻層26，再於 中壓電路區30以及低壓電路區4〇所裸露的基底12表面上 分別形成閘介電層312與412。閘介電層312與412的厚 度大致相等且可關時形成之。其形成方法例如是進行熱 氧化製程’以形成氧化矽層，氧化矽層的厚度約為15〇埃。' 然後’形成導電層34。導電層34的材質例如是摻雜多晶 19 201017869 „J-0227 28801twf.doc/n 矽，形成的方法例如是化學氣相沈積法。 之後’請參照圖4D，將導電層34圖案化，以分別在 高壓電路區20、中壓電路區30以及低壓電路區40上形成 閘極214、314以及414。閘極214、314以及414分別與 閘介電層212、312、412形成閘極結構208、308、408。 之後，在低壓電路區40之閘極結構408的兩侧形成具有第 二導電型的淡摻雜區409a、409b。然後，在閘極結構208、 308、408的侧壁形成間隙壁36。其後，在高壓電路區20 ❹之閘極結構208之兩侧的第二井區2〇6a、206b中分別形成 具有第二導電型的源極與汲極區210a、210b，在中壓電路 區30之閘極結構308之兩側的第二井區306a、306b中分 別形成具有第二導電型的源極與汲極區3i〇a、3l〇b，並且 在低壓電路區40之閘極結構408之兩侧的第一井區14中 形成具有第二導電型的濃摻雜區411a、411b，其中濃摻雜 區411a、411b分別與淡摻雜區4〇9a、40%電性耦接，構 ，源極與汲極區410a、41〇b。之後，在高壓電路區2〇的 春第一井區14中形成摻雜區216a、216b，並在中壓電路區 30的第一井區14申形成摻雜區316a、316b。 本發明實施例之半導體元件的製造方法簡易， 低，且符合市場需求。 或本 _、本發明已以實施例縣如上，鮮麟用以限定 發明任何㈣此技藝者’林麟本發明之精神和範 冬^田可作些許之更動與潤飾，因此本發明之保護範圍 虽視後附之申請專利範圍所界定者為準。 20 ,3-0227 2880 ltwf.doc/n 【圖式簡單說明】 圖1是依照本發明實施例所繪示之一種半導體元件的 剖面示意圖。 圖2是依照本發明另一實施例所繪示之一種半導體元 件的剖面示意圖。 圖3是依照本發明又一實施例所繪示之一種半導體元 件的剖面示意圖。 圖4A至4D是依據本發明實施例所繪示之一種半導體 ❹ 元件的製造流程剖面示意圖。 圖5是依照本發明又一實施例所繪示之一種半導體元 件的剖面示意圖 【主要元件符號說明】 10:半導體元件 12 :基底 14:第一導電型之第一井區 φ 16、204a、204b、218a、218b、304a、304b、318a、 318b :隔離結構 18 :罩幕層 20 .南壓電路區 22 :墊氧化層 24 :氮化矽層 26 :光阻層 28、32 :開口 21 201017869 _ 8-0227 2880 ltwf.doc/n 30 :中壓電路區 34 :導電層 36 :間隙壁 40 :低壓電路區 200、高壓元件 202、302、402 :金氧半電晶體 205、305 :埋層 206a、206b、306a、306b :第二導電型之第二井區 β 208、308、408 :閘極結構 210a、210b、310a、310b、410a、410b :第二導電型 之源極與>及極區 212、312、412 :閘介電層 214、314、414 :閘極 216a、216b、316a、316b:第一導電型掺雜區 220a、220b、320a、320b :第二導電型之階區 222a、222b、322a、322b :第二導電型之漂移區 參 300:中壓元件 400 :低壓元件 409a、409b :第二導電型之淡摻雜區 411a、411b :第二導電型之濃摻雜區 22Field implant area of the first conductivity type (not shown). Then used as the isolation structure 304b, 318a, 318b. Below the 318b, a gate dielectric layer 212 is formed on the surface of the bare wire substrate 12 having the high voltage circuit region 20, / ..., 丨 π 冋 %, the medium voltage circuit (4), and the low voltage circuit region 4G. The formation method of the gate dielectric layer is, for example, a thermal oxidation process, and (10) a co-cut layer having a thickness of about 85 angstroms. Then, the start voltage adjustment step is performed. Thereafter, a photoresist layer 26 is formed on the gate dielectric layer 212. The photoresist layer 26 covers the interlayer on the turn circuit region 2 (); the photoresist layer 26 has two openings 28, 32. The dielectric layer 212 and the closed dielectric layer 212 on the low voltage circuit region 4 are exposed, respectively. Thereafter, referring to FIG. 4C, the gate dielectric layer 212 exposed by the openings 28, 32 is removed, and the in-ink circuit region 30 and the low voltage are exposed. The surface of the base 12 of the road zone 4〇. The method of removing the gate dielectric layer 212 exposed by the openings 28, 32 can be etched with hydrofluoric acid. Thereafter, the photoresist layer 26 is removed, and the gate dielectric layers 312 and 412 are formed on the surface of the substrate 12 exposed by the intermediate voltage circuit region 30 and the low voltage circuit region 4, respectively. The gate dielectric layers 312 and 412 are substantially equal in thickness and can be formed when off. The formation method is, for example, a thermal oxidation process to form a ruthenium oxide layer having a thickness of about 15 Å. The conductive layer 34 is then formed. The material of the conductive layer 34 is, for example, doped polycrystal 19 201017869 „J-0227 28801 twf.doc/n 矽, and the formed method is, for example, a chemical vapor deposition method. Then, referring to FIG. 4D, the conductive layer 34 is patterned to Gates 214, 314, and 414 are formed on the high voltage circuit region 20, the intermediate voltage circuit region 30, and the low voltage circuit region 40. The gates 214, 314, and 414 form a gate structure with the gate dielectric layers 212, 312, and 412, respectively. 208, 308, 408. Thereafter, lightly doped regions 409a, 409b having a second conductivity type are formed on both sides of the gate structure 408 of the low voltage circuit region 40. Then, on the sidewalls of the gate structures 208, 308, 408 A spacer 36 is formed. Thereafter, source and drain regions 210a, 210b having a second conductivity type are formed in the second well regions 2A, 6a, 206b on both sides of the gate structure 208 of the high voltage circuit region 20, respectively. Forming a source and a drain region 3i〇a, 3l〇b having a second conductivity type in the second well regions 306a, 306b on both sides of the gate structure 308 of the medium voltage circuit region 30, respectively, and at a low voltage Forming a second conductivity type in the first well region 14 on both sides of the gate structure 408 of the circuit region 40 The regions 411a and 411b, wherein the heavily doped regions 411a and 411b are electrically coupled to the lightly doped regions 4〇9a and 40%, respectively, and the source and drain regions 410a and 41〇b. Thereafter, in the high voltage circuit region. The doped regions 216a, 216b are formed in the first well region 14 of the spring, and the doped regions 316a, 316b are formed in the first well region 14 of the intermediate voltage circuit region 30. The fabrication of the semiconductor device of the embodiment of the present invention The method is simple, low, and meets the market demand. Or this _, the present invention has been used in the example of the county as above, and the fresh lining is used to limit the invention. (4) This artist's spirit of Lin Lin's invention and Fan Dong ^ Tian can make some changes. And the scope of protection of the present invention is defined by the scope of the appended claims. 20, 3-0227 2880 ltwf.doc/n [Simplified Schematic] FIG. 1 is drawn in accordance with an embodiment of the present invention. 2 is a schematic cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device in accordance with yet another embodiment of the present invention. 4A to 4D are implemented in accordance with the present invention FIG. 5 is a schematic cross-sectional view showing a semiconductor device according to still another embodiment of the present invention. [Main component symbol description] 10: Semiconductor component 12: Substrate 14: First conductivity region φ 16, 204a, 204b, 218a, 218b, 304a, 304b, 318a, 318b of a conductivity type: isolation structure 18: mask layer 20. south voltage circuit region 22: pad oxide layer 24: nitridation矽 layer 26: photoresist layer 28, 32: opening 21 201017869 _ 8-0227 2880 ltwf.doc / n 30: medium voltage circuit region 34: conductive layer 36: spacer 40: low voltage circuit region 200, high voltage component 202, 302, 402: MOS semi-transistor 205, 305: buried layer 206a, 206b, 306a, 306b: second well type second well region β 208, 308, 408: gate structure 210a, 210b, 310a, 310b, 410a, 410b: source of the second conductivity type and > and polar regions 212, 312, 412: gate dielectric layers 214, 314, 414: gates 216a, 216b, 316a, 316b: first conductivity type doped regions 220a, 220b, 320a, 320b: second conductivity type step regions 222a, 222b, 322a, 322b: second conductivity type drift region 300: MV element 400: a low pressure member 409a, 409b: second conductivity type of the lightly doped regions 411a, 411b: second conductivity type heavily doped region 22 of the