JPH03265172A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03265172A
JPH03265172A JP6272690A JP6272690A JPH03265172A JP H03265172 A JPH03265172 A JP H03265172A JP 6272690 A JP6272690 A JP 6272690A JP 6272690 A JP6272690 A JP 6272690A JP H03265172 A JPH03265172 A JP H03265172A
Authority
JP
Japan
Prior art keywords
film
silicon
ions
chlorine
fluorine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6272690A
Other languages
Japanese (ja)
Inventor
Katsuo Oikawa
及川 勝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6272690A priority Critical patent/JPH03265172A/en
Publication of JPH03265172A publication Critical patent/JPH03265172A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease imperfections and uniformize film thickness by forming a semiconductor layer on an Si oxide film, Si nitride film, or Si oxide nitride film, ion-implanting fluorine, chlorine, and bromine, and heat-treating and diffusing them. CONSTITUTION:A silicon oxide film, silicon nitride film, or silicon oxide nitride film 2 is formed on a silicon substrate 1, and on the film 2 a semiconductor layer 3 is formed. In this layer fluorine, chlorine, or bromine ions are implanted, and heat-treated and diffused into the film 2. This makes it possible to form the film 2 by using a thermal oxidation or CVD method, and the fluorine, chlorine, or bromine ions are diffused uniformly in the film 2. Accordingly, imperfections existing in the film 2 are removed by a gettering effect, the film thickness can be made uniform, and the reliability increases.

Description

【発明の詳細な説明】 (概要) 半導体装置の製造方法、特に、MO3型トランジスタの
ゲート絶縁膜の形成方法に関し、欠陥が少なく、しかも
、膜厚が均一であるゲート絶縁膜を経済的負担を増加さ
せることなく製造しうる方法を提供することを目的とし
、酸化シリコン膜、窒化シリコン膜、または、酸窒化シ
リコン膜上に半導体層を形成し、この半導体層にフッ素
イオン、塩素イオン、または、臭素イオンをイオン注入
し、熱処理を施し、前記のフッ素、塩素、または、臭素
を前記の酸化シリコン腹、窒化シリコン膜、または、酸
窒化シリコン膜中に拡散するように構成する。
[Detailed Description of the Invention] (Summary) Regarding a method for manufacturing a semiconductor device, in particular, a method for forming a gate insulating film of an MO3 type transistor, it is possible to create a gate insulating film that has few defects and has a uniform film thickness without causing an economic burden. The purpose of the present invention is to provide a method that can be manufactured without increasing the number of semiconductors, and a semiconductor layer is formed on a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Bromine ions are implanted and heat treated to diffuse the fluorine, chlorine, or bromine into the silicon oxide film, silicon nitride film, or silicon oxynitride film.

〔産業上の利用分野] 本発明は、半導体装置の製造方法、特に、MO3型トラ
ンジスタのゲート絶縁膜の形成方法に関する。
[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gate insulating film of an MO3 type transistor.

〔従来の技術〕[Conventional technology]

欠陥が少なく信頼性の高いゲート絶縁膜を形成する方法
として、酸素に塩素系ガスを混入した混合カス中におい
てシリコン基板を熱酸化して二酸化シリコン絶縁膜を形
成する塩#酸化法が知られている、酸素中に混入された
塩素系ガスのゲッタリング効果によって、二酸化シリコ
ン絶縁膜中の不純物や欠陥が除去され、良質の絶縁膜が
形成されるものである。
As a method for forming a highly reliable gate insulating film with few defects, the salt #oxidation method is known, in which a silicon substrate is thermally oxidized in a mixture of oxygen and chlorine gas to form a silicon dioxide insulating film. The impurities and defects in the silicon dioxide insulating film are removed by the gettering effect of the chlorine-based gas mixed into the oxygen, forming a high-quality insulating film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、塩酸酸化法に使用される装置は、塩素系ガス
を含む排ガスを廃棄するための特別な処理装置等が必要
になるため、装置が大型になり、経済的負担が増大する
と云う欠点がある。また、シリコン基板に接触する塩素
系ガスの濃度が基板面内において均一にはならないため
、二酸化シリコン膜の膜厚が不均一に戒長し、また、二
酸化シリコン膜中の塩素の量が不均一になるという欠点
がある。
By the way, the equipment used in the hydrochloric acid oxidation method requires special processing equipment to dispose of exhaust gas containing chlorine gas, which has the disadvantage of increasing the size of the equipment and increasing the economic burden. . In addition, since the concentration of chlorine-based gas that comes into contact with the silicon substrate is not uniform within the substrate surface, the thickness of the silicon dioxide film becomes uneven, and the amount of chlorine in the silicon dioxide film becomes uneven. It has the disadvantage of becoming

本発明の目的は、これらの欠点を解消することにあり、
欠陥が少なく、しかも、膜厚が均一であるゲート絶縁膜
を経済的負担を増加させることなく製造しうる方法を提
供することにある。
The purpose of the present invention is to eliminate these drawbacks,
It is an object of the present invention to provide a method of manufacturing a gate insulating film having few defects and having a uniform thickness without increasing the economic burden.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的は、酸化シリコン膜、窒化シリコン膜、また
は、酸窒化シリコン膜(2)上に半導体層(3)を形成
し、この半導体層(3)にフッ素イオン、塩素イオン、
または、臭素イオンをイオン注入し、熱処理を施し、前
記のフッ素、塩素、または、臭素を前記の酸化シリコン
膜、窒化シリコン膜、または、酸窒化シリコン膜(2)
中に拡散する工程を有する半導体装置の製造方法によっ
て達成される。
The above purpose is to form a semiconductor layer (3) on a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (2), and to add fluorine ions, chloride ions,
Alternatively, bromine ions are implanted, heat treatment is performed, and the fluorine, chlorine, or bromine is added to the silicon oxide film, silicon nitride film, or silicon oxynitride film (2).
This is achieved by a method for manufacturing a semiconductor device that includes a step of diffusing into the semiconductor device.

〔作用〕[Effect]

酸化シリコン膜、窒化シリコン膜、または、酸窒化シリ
コン膜を、塩素系ガスを混入することなく、通常の熱酸
化法またはCVD法を使用して形成することができるの
で、これらの絶縁膜のy厚は均一に形成される。この均
一な膜厚を有する絶縁膜上に半導体層を形成してフッ素
イオン、塩素イオン、または、臭素イオンをイオン注入
し、熱処理を施すことによって、所望の量のフッ素、塩
素、または、臭素が絶縁膜中に均一に拡散し、そのゲッ
タリング効果によって絶縁膜中に存在する欠陥が除去さ
れ、膜厚が均一で信頼性の高い絶縁膜が経済的負担を増
大することなく形成される。
Silicon oxide film, silicon nitride film, or silicon oxynitride film can be formed using normal thermal oxidation method or CVD method without mixing chlorine-based gas. The thickness is uniform. A semiconductor layer is formed on this insulating film having a uniform thickness, ion implantation of fluorine ions, chlorine ions, or bromine ions is performed, and a desired amount of fluorine, chlorine, or bromine is applied. It diffuses uniformly into the insulating film, and its gettering effect removes defects present in the insulating film, allowing a highly reliable insulating film with uniform thickness to be formed without increasing economic burden.

〔実施例〕〔Example〕

以下、図面を参照しつ装、本発明の一実施例に係るMO
S型ダイオードの製造方法について説明する。
Hereinafter, with reference to the drawings, an MO according to an embodiment of the present invention will be described.
A method for manufacturing an S-type diode will be explained.

第1図(a)参照 シリコン基板1上に通常の熱酸化により85人厚の二酸
化シリコンM2を形成する。
Referring to FIG. 1(a), silicon dioxide M2 having a thickness of 85 mm is formed on a silicon substrate 1 by normal thermal oxidation.

第1図(b)参照 CVD法を使用し、3.000λ厚の多結晶シリコン層
3を形成する。
Referring to FIG. 1(b), a polycrystalline silicon layer 3 having a thickness of 3.000λ is formed using the CVD method.

第1図(C)参照 ヒ素イオンを打ち込みエネルギー100KeV、ドーズ
量3 X 1015cm−”をもってイオン注入し、次
いで、三フン化ホウ素(BF、)をイオン化して抽出し
たフッ素イオンを打ち込みエネルギー60KeV、ドー
ズii I X 1015cv−2をもってイオン注入
する。なお、ヒ素イオンをイオン注入する目的は、多結
晶シリコン層3を導電性のゲート電極にするためである
Refer to Figure 1 (C) Arsenic ions were implanted at an energy of 100 KeV and a dose of 3 x 1015 cm-'', and then fluorine ions extracted by ionizing boron trifluoride (BF) were implanted at an energy of 60 KeV and a dose of ii Ion implantation is performed using I.sub.X 1015 cv-2.The purpose of implanting arsenic ions is to make the polycrystalline silicon layer 3 into a conductive gate electrode.

第1図(d)参照 次いで、850°Cの温度において120分間熱処理を
施し、多結晶シリコンJi3をゲート電極とし、二酸化
シリコン膜2をゲート絶縁膜とするMOSダイオードを
形成する。
Refer to FIG. 1(d) Next, heat treatment is performed at a temperature of 850° C. for 120 minutes to form a MOS diode having the polycrystalline silicon Ji3 as the gate electrode and the silicon dioxide film 2 as the gate insulating film.

第2図参照 第2図は、前記の工程をもって製造されたMOSダイオ
ードの深さ方向に対するヒ素・フッ素及び酸素の二次イ
オンカウント数を示す。この図から明らかなように、二
酸化シリコン膜中にフッ素が十分導入されている。
See FIG. 2 FIG. 2 shows the secondary ion counts of arsenic, fluorine, and oxygen in the depth direction of the MOS diode manufactured by the above-described steps. As is clear from this figure, fluorine is sufficiently introduced into the silicon dioxide film.

第3図参照 第3図は、前記のMOSダイオードのFowlerNo
rdhei+n )ンネル電流によるストレス発生後の
フラットバンド電圧のシフト量と二酸化シリコン膜中の
フッ素イオン注入量との関係を示す。この図から明らか
なように、二酸化シリコン膜中にフッ素が十分導入され
ていればフラットバンド電圧のシフト量が少なくなる。
See Figure 3. Figure 3 shows the Fowler No. of the MOS diode.
rdhei+n) shows the relationship between the shift amount of flat band voltage after stress generation due to channel current and the amount of fluorine ions implanted into the silicon dioxide film. As is clear from this figure, if sufficient fluorine is introduced into the silicon dioxide film, the amount of shift in the flat band voltage will be reduced.

フラットバンド電圧のシフト量が少ないということは、
素子特性が安定していることを表している。
The fact that the amount of shift in the flat band voltage is small means that
This indicates that the device characteristics are stable.

なお、イオン注入するイオンとしては、フッ素イオンの
外、塩素イオン、または、臭素イオンを使用してもよい
Note that as the ions to be implanted, in addition to fluorine ions, chlorine ions or bromine ions may be used.

また、フッ素イオン、塩素イオン、または、臭素イオン
をイオン注入して熱処理を施した後に、ヒ素イオンをイ
オン注入して熱処理を施してもよく、または、逆にヒ素
イオンをイオン注入して熱処理を施した後に、フッ素イ
オン、塩素イオン、または、臭素イオンをイオン注入し
て熱処理を施してもよい。
Furthermore, after ion implantation of fluorine ions, chloride ions, or bromine ions and heat treatment, arsenic ions may be ion-implanted and heat treatment performed, or conversely, arsenic ions may be ion-implanted and heat treatment is performed. After that, fluorine ions, chlorine ions, or bromine ions may be implanted and heat treated.

また、ゲート絶縁膜を窒化シリコン膜、#窒化シリコン
膜、または、酸化シリコン膜と窒化シリコン膜との積層
膜をもって形成した場合にも、フッ素イオン、塩素イオ
ン、または、臭素イオンをイオン注入することによって
酸化シリコン膜の場合と同一の効果が得られる。
Also, when the gate insulating film is formed using a silicon nitride film, #silicon nitride film, or a laminated film of a silicon oxide film and a silicon nitride film, ion implantation of fluorine ions, chlorine ions, or bromine ions is not necessary. The same effect as in the case of a silicon oxide film can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明せるとおり、本発明に係る半導体装置の製造方
法においては、通常の熱酸化法またはCVD法を使用し
て形成した膜厚が均一な酸化シリコン膜、窒化シリコン
膜、または、酸窒化シリコン膜上に半導体層を形成し、
フッ素イオン、塩素イオン、または、臭素イオンをイオ
ン注入して熱処理を施すことによって、膜厚が均一であ
る酸化シリコン膜、窒化シリコン膜、または、#窒化シ
リコン膜中にフッ素、塩素、または、臭素が十分拡散し
、そのゲッタリング効果によってそれらの膜の欠陥が除
去されるため、膜厚が均一で欠陥の少ない絶縁膜が形成
される。この絶縁膜をMO3型トランジスタのゲート絶
縁膜として使用すれば、トランジスタの特性は安定化し
、信頼性が著しく向上する。
As explained above, in the method for manufacturing a semiconductor device according to the present invention, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film having a uniform thickness formed using a normal thermal oxidation method or a CVD method is used. forming a semiconductor layer on top;
By implanting fluorine ions, chlorine ions, or bromine ions and performing heat treatment, fluorine, chlorine, or bromine can be added to a silicon oxide film, silicon nitride film, or #silicon nitride film with a uniform film thickness. is sufficiently diffused and the defects in those films are removed by the gettering effect, so that an insulating film with a uniform thickness and few defects is formed. If this insulating film is used as a gate insulating film of an MO3 type transistor, the characteristics of the transistor will be stabilized and reliability will be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)(b)(c)(d)は、本発明の一実施例
に係るMOSダイオードの製造工程図である。 第2図は、絶縁膜中のヒ素とフッ素と酸素との二次イオ
ンカウント数とエツチング時間との関係を示すグラフで
ある。 第3図は、フラットバンド電圧のシフト量とフッ素イオ
ン注入量との関係を示す図である。 l・・・シリコン基板、 2・・・酸化シリコン膜、窒化シリコン膜または酸窒化
シリコン膜、 3・・・多結晶シリコン層。
1(a), (b), (c), and (d) are manufacturing process diagrams of a MOS diode according to an embodiment of the present invention. FIG. 2 is a graph showing the relationship between the secondary ion counts of arsenic, fluorine, and oxygen in the insulating film and the etching time. FIG. 3 is a diagram showing the relationship between the shift amount of flat band voltage and the amount of fluorine ion implanted. l...Silicon substrate, 2...Silicon oxide film, silicon nitride film, or silicon oxynitride film, 3...Polycrystalline silicon layer.

Claims (1)

【特許請求の範囲】 酸化シリコン膜、窒化シリコン膜、または、酸窒化シリ
コン膜(2)上に半導体層(3)を形成し、 該半導体層(3)にフッ素イオン、塩素イオン、または
、臭素イオンをイオン注入し、熱処理を施し、 前記フッ素、塩素、または、臭素を前記酸化シリコン膜
、窒化シリコン膜、または、酸窒化シリコン膜(2)中
に拡散する 工程を有することを特徴とする半導体装置の製造方法。
[Claims] A semiconductor layer (3) is formed on a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (2), and the semiconductor layer (3) contains fluorine ions, chlorine ions, or bromine ions. A semiconductor characterized by comprising a step of implanting ions, performing heat treatment, and diffusing the fluorine, chlorine, or bromine into the silicon oxide film, silicon nitride film, or silicon oxynitride film (2). Method of manufacturing the device.
JP6272690A 1990-03-15 1990-03-15 Manufacture of semiconductor device Pending JPH03265172A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6272690A JPH03265172A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6272690A JPH03265172A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03265172A true JPH03265172A (en) 1991-11-26

Family

ID=13208657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6272690A Pending JPH03265172A (en) 1990-03-15 1990-03-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03265172A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157765A (en) * 1990-10-20 1992-05-29 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor and manufacture thereof
JPH1140803A (en) * 1997-07-15 1999-02-12 Toshiba Corp Semiconductor device and its manufacture
WO2012062791A1 (en) * 2010-11-11 2012-05-18 International Business Machines Corporation Creating anisotrpically diffused junctions in field effect transistor devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04157765A (en) * 1990-10-20 1992-05-29 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field effect transistor and manufacture thereof
JPH1140803A (en) * 1997-07-15 1999-02-12 Toshiba Corp Semiconductor device and its manufacture
WO2012062791A1 (en) * 2010-11-11 2012-05-18 International Business Machines Corporation Creating anisotrpically diffused junctions in field effect transistor devices
US8633096B2 (en) 2010-11-11 2014-01-21 International Business Machines Corporation Creating anisotropically diffused junctions in field effect transistor devices
US8796771B2 (en) 2010-11-11 2014-08-05 International Business Machines Corporation Creating anisotropically diffused junctions in field effect transistor devices

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