JPH1140803A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, in which the reliability of a gate insulating film regarding its dielectric breakdown resistance or the like is enhanced by a method, wherein the gate insulating film is constituted so as to contain silicon, oxygen or nitrogen and a halogen element, and the maximum element concentration of the halogen element is specified. SOLUTION: A silicon thermal oxide film 2 and n-type source-drain diffused layers 7a, 7b are formed on a P-type silicon substrate 1. A gate insulating film 3 is composed mainly of silicon, oxygen or nitrogen, and halogen atoms such as fluorine atoms or the like are introduced. A CVD silicon oxide film 6 is formed on a polycrystalline silicon film 4 which is to be used as a gate electrode. A silicon nitride film 8 is formed on the sidewall of the gate electrode. In addition, a silicide layer 9 is formed in a source-drain region. In addition, a contact hole is opened in a CVD silicon oxide film 10. An Al electrode 11 which is to be used as an interconnection is formed so as to be patterned. In this case, when the maximum element concentration of a halogen element is set at 10<20> per/cm<3> to 10<21> per cm<3> or lower, the reliability of the gate insulating film 3 can be increased, and the reliability of an element can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of improving the reliability of a gate insulating film of a MOS type semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, an element in which a gate oxide film is used as a tunnel oxide film, such as a non-volatile semiconductor memory (EEPROM) capable of electrically writing and erasing, has been used in writing and erasing. A high electric field of more than 10 MV / cm is applied to the gate oxide. Further, in the gate oxide film of the logical operation element, a higher electric field is applied as the size is reduced in order to maintain the performance. When a high electric field as described above is applied to the gate oxide film, electrons that have obtained high energy from the electric field pass through the gate oxide film, so that a high dielectric breakdown resistance is required for the gate oxide film. You.

Conventionally, an empirical method has been employed in which various oxide films are formed by changing parameters such as a forming temperature and a forming atmosphere, and their electrical characteristics are evaluated to use conditions satisfying specifications. Have been. However, under the current situation where the gate oxide film becomes increasingly thin, it is becoming difficult to satisfy the above specifications. Furthermore, in the current situation where the types of products are diversified and the generations are changed rapidly, it is extremely inefficient to determine the conditions by the empirical method as described above, and it is important to increase the product cost. There are drawbacks.

[0004]

As described above, the EEPR
High dielectric breakdown resistance is required for the tunnel oxide film of the OM and the gate oxide film of the logical operation element, but it is extremely difficult to satisfy such specifications, which leads to a decrease in element reliability and an increase in manufacturing cost. Was a factor inviting.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to improve the reliability of a gate insulating film, such as an improvement in dielectric breakdown resistance, and to improve the reliability of an element. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same.

[0006]

According to a semiconductor device of the present invention, a gate insulating film includes at least one of silicon, oxygen, and nitrogen and a halogen element, and the gate insulating film contains a halogen element (particularly, fluorine) in the gate insulating film. The maximum element concentration is not less than 10 ²⁰ / cm ^{3 and not} more than 10 ²¹ / cm ³ .

A method for manufacturing a semiconductor device according to the present invention comprises:
Forming a gate insulating film including at least one of silicon and oxygen or nitrogen on the semiconductor substrate (especially silicon substrate), the largest element concentration in the gate insulating film 10 ²⁰
Characterized by a step of introducing a halogen element (especially fluorine) as in number / cm ³ or more is 10 ²¹ / cm ³ or less.

[0008] The maximum element concentration refers to a concentration at which the concentration of the halogen element becomes maximum in the thickness direction of the gate insulating film.

In the interfacial transition layer existing at the interface between the gate insulating film and the silicon substrate, fluorine is terminated at dangling bonds of silicon, or hydrogen of Si—H bond having small binding energy is replaced by fluorine. It is possible to form a Si—F bond having a large binding energy. Further, fluorine acts on the distorted Si—O—Si bond, and S
By separating into i-O bonds and Si-F bonds, stress can be relaxed. By introducing fluorine into the gate insulating film in this way, the characteristics when a high electric field is applied to the gate insulating film for a long time (Time-Dependence-Dielectric
-Breakdown (TDDB) characteristics) can be improved.

FIG. 19 shows the effect when fluorine is introduced into the gate oxide film. The horizontal axis indicates the charge in the gate oxide film until the dielectric breakdown occurs when a constant electric field is continuously applied. The injection amount (Charge-to-Breakdown: Qbd) is shown, and the vertical axis shows the cumulative failure rate P of dielectric breakdown as ln (-ln (1-P)). When fluorine is not introduced, the distribution shape is often broken at a low Qbd, but when fluorine is introduced, the distribution shape becomes sharp, and the oxide film quality is homogenized by introducing fluorine. It can be seen that a MOS type semiconductor device can be obtained.

FIG. 20 shows 50% Qbd (average value of Qbd) and Qbdex defect rate (rate of a chip which causes dielectric breakdown in a short time) with respect to the maximum fluorine concentration in the gate oxide film. As can be seen from the figure, when the maximum fluorine concentration exceeds 10 ²¹ atoms / cm ³ , 50% Qbd drops sharply, and when the maximum fluorine concentration becomes less than 10 ²⁰ atoms / cm ³ , the Qbdex defect rate sharply increases. It increases to a defect rate of 10% or more.

FIG. 21 shows the relationship between SiF / Si (ie, the ratio of Si—F bonds) and SiF ₂ / Si (ie, the ratio of Si—F ₂ bonds) with respect to the maximum fluorine concentration in the gate oxide film. From this figure, it can be seen that the Si—F ₂ bond, which lowers the reliability of the gate oxide film, sharply increases when the maximum fluorine concentration in the gate oxide film exceeds 10 ²¹ atoms / cm ³ .

The above description is for the case where a silicon oxide film is used as the gate insulating film. The same applies to the case where a silicon nitride film or an oxynitride film containing silicon, oxygen and nitrogen is used for the gate insulating film. is there.

From the above, in order to obtain a highly reliable gate insulating film, the maximum fluorine concentration in the gate insulating film should be set to 10 ²⁰ atoms / cm ³ to 10 ²¹ atoms / cm ^3. preferable. In this way, even when the thickness of the gate insulating film is small (for example, 8 nm or less), it is possible to improve the dielectric breakdown characteristics and the low electric field leakage current characteristics of the gate insulating film.
The reliability of the gate insulating film can be improved, and the reliability of the device can be improved.

The step of introducing a halogen element such as fluorine into the gate insulating film or a step thereafter is 850 steps.
It is preferable not to perform the heat treatment step at a temperature of not lower than 30 ° C. for 30 minutes or more. By performing such a heat treatment step,
The halogen element is further introduced into the gate insulating film from the supply source of the halogen element, and as a result, 10 ²¹ / c
This is because there is a possibility that a halogen element of m ³ or more is contained in the gate insulating film.

As a high-temperature and long-time heat treatment step such as a heat treatment at 850 ° C. or more and for 30 minutes or more, there is a heat treatment step for activating impurities in a semiconductor film to be a gate electrode.

Therefore, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate insulating film containing at least one of silicon and oxygen or nitrogen on a semiconductor substrate (particularly, a silicon substrate), and forming an active layer on the gate insulating film. Forming a semiconductor film for forming a gate electrode (especially a silicon film) containing a converted impurity element (group 3 or 5 group element), and then introducing a halogen element (especially fluorine) into the gate insulating film And a step of performing In this case, in the step of introducing the halogen element into the gate insulating film or a step thereafter, it is preferable that the heat treatment step at 850 ° C. or more and for 30 minutes or more is not performed.

However, the step of forming the semiconductor film for forming the gate electrode containing the activated impurity element on the gate insulating film is performed at a high temperature and a long time such as a heat treatment at 850 ° C. or more and 30 minutes or more. In the case where the step can be performed without the heat treatment step, the step of introducing a halogen element into the gate insulating film can be performed before the step.

In the present invention, when the halogen element is introduced into the gate insulating film, the halogen element contained in the semiconductor film for forming the gate electrode or the peripheral region of the gate insulating film is introduced into the gate insulating film by heat treatment. Is preferred. Specifically, a halogen element can be introduced into the gate insulating film as described below.

(A) A halogen element contained in a semiconductor film for forming a gate electrode is introduced into a gate insulating film by heat treatment.

(B) A halogen element formed on the side wall of the gate electrode and contained in the side wall insulating film (such as a silicon nitride film) is introduced into the gate insulating film by heat treatment.

(C) A halogen element contained in an element isolation insulating film (such as a silicon oxide film) is introduced into the gate insulating film by heat treatment.

(D) The halogen element contained in the insulating film formed on the gate electrode is introduced into the gate insulating film by heat treatment.

(E) A halogen element contained in a film serving as a wiring (for example, a metal film connected to the source / drain) is introduced into the gate insulating film by heat treatment.

(F) In the case where the semiconductor substrate is a so-called SOI substrate, a halogen element contained in an insulating layer (such as a silicon oxide film) buried under a semiconductor layer on which an element is formed is subjected to heat treatment to form a gate insulating film. To be introduced.

(G) After adsorbing a gaseous or liquid halogen element or halide on the surface of the gate insulating film,
A semiconductor film for forming a gate electrode is formed over the gate insulating film, and the halogen element adsorbed by the heat treatment is introduced into the gate insulating film. In this case, the step of adsorbing a halogen element or the like on the surface of the gate insulating film and the step of forming a semiconductor film on the gate insulating film are preferably performed continuously in a vacuum or in a non-oxidizing atmosphere.

(H) A halogen element is introduced into the semiconductor substrate from the back side of the semiconductor substrate, and the halogen element contained in the semiconductor substrate is introduced into the gate insulating film by heat treatment.

(I) An amorphous silicon film containing a halogen element is formed between a silicon film for a gate electrode and a gate insulating film, and the halogen element contained in the amorphous silicon film is introduced into the gate insulating film by heat treatment. .

In the present invention, the introduction of the halogen element contained in the semiconductor film (silicon film) for forming the gate electrode into the gate insulating film can be performed, for example, as follows.

(A) A silicon film is formed on a gate insulating film, an impurity element belonging to Group 3 or Group 5 or ions containing them are introduced into the silicon film, and the impurity element is activated by heat treatment. After that, a halogen element or ions containing them are introduced into the silicon film, and the halogen element is diffused into the gate insulating film by heat treatment.

(B) A silicon film is formed on the gate insulating film, a halogen element or ions containing them are introduced into the silicon film, and the halogen element is diffused into the gate insulating film by heat treatment. After that, an impurity element belonging to Group 3 or Group 5 or ions containing them are introduced into the silicon film, and the impurity element is activated by heat treatment. In this case, the heat treatment step for activating the impurity element is performed at 850 ° C.
It is preferable not to perform the above for 30 minutes or more.

(C) A silicon film containing a Group 3 or Group 5 impurity element is formed on the gate insulating film (for example, using a gas containing silicon and a gas containing an impurity element), and thereafter. Then, a halogen element or ions containing them are introduced into the silicon film, and the halogen element is diffused into the gate insulating film by heat treatment.

(D) A silicon film containing a Group 3 or Group 5 impurity element and a halogen element is formed on the gate insulating film (for example, using a gas containing silicon and a gas containing an impurity element, At least one of these gases contains a halogen element.) Then, the heat treatment diffuses the halogen element in the silicon film into the gate insulating film.

(E) A silicon film is formed on the gate insulating film, halide ions of a Group 3 or 5 impurity element are introduced into the silicon film, and a Group 3 or Group 5 impurity is further introduced into the silicon film. Impurity element ions are introduced, and a halogen element is diffused into the gate insulating film by heat treatment.

It should be noted that the present invention is not limited to a conventional MOS transistor having a gate electrode formed on a semiconductor substrate via a gate insulating film, but also a first insulating film (tunnel oxide film), Electrode (floating gate), second
The present invention can also be applied to a nonvolatile memory cell in which an insulating film and a second electrode (control gate) are stacked. In this case, a halogen element is introduced into the first and second insulating films (for example, after the halogen element is introduced into the second electrode, the first and second halogen elements contained in the second electrode are subjected to a heat treatment. Is introduced into the insulating film.).

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described.

FIG. 1 is a structural sectional view of an n-channel transistor according to the present embodiment. A silicon thermal oxide film 2 for element isolation is formed on a p-type silicon substrate 1. On the surface of the silicon substrate, n-type source / drain diffusion layers 7a and 7b are formed by ion implantation of phosphorus. In addition, a gate insulating film 3 is formed on the surface of the silicon substrate.
An insulating film containing silicon, oxygen and nitrogen as main components is formed, and fluorine atoms are introduced into the gate insulating film 3. A CVD silicon oxide film 6 is formed on polycrystalline silicon film 4 serving as a gate electrode, and a silicon nitride film 8 is formed on a side wall of the gate electrode. Further, silicide 9 is formed in the source / drain region. A contact hole is opened in the CVD silicon oxide film 10, and an Al electrode 11 serving as a wiring is formed by sputtering and patterned.

FIG. 2 is a process sectional view showing a method of manufacturing the n-channel MOS transistor shown in FIG.

First, as shown in FIG. 2A, for example,
A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and an element isolation insulating film 2 having a thickness of about 0.6 μm is formed on the surface of the p-type silicon substrate 1 by a normal selective oxidation method. I do.

Next, as shown in FIG. 2B, a gate oxide film 3 having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen, and subsequently a gate electrode having a thickness of 200 nm is formed on the gate oxide film 3. A polycrystalline silicon film 4 is deposited. Next, for example, phosphorus ions are implanted into the polycrystalline silicon at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after ion implantation is
A peak concentration is formed in polycrystalline silicon. Subsequently, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus and reduce the resistance of the polycrystalline silicon.

Next, as shown in FIG. 2C, fluorine is ion-implanted over the entire surface at, for example, an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . At this time, the distribution of fluorine immediately after ion implantation is such that a peak concentration is formed in the polycrystalline silicon film 4 and fluorine is not implanted into the gate oxide film 3. Subsequently, by performing a heat treatment that is not “850 ° C. or more and 30 minutes or more”, for example, a heat treatment at 800 ° C. for 30 minutes in a nitrogen atmosphere, the implanted fluorine is diffused into the gate oxide film 3.

Next, as shown in FIG. 1D, a CVD silicon oxide film 6 is deposited on the polycrystalline silicon film 4. Subsequently, after patterning using a resist mask, the polycrystalline silicon film 4 and the CVD silicon oxide film 6 are etched by a reactive ion etching method to form a gate portion.

Next, as shown in FIG. 3E, for example, phosphorus is ion-implanted at 1 × 10 ¹⁵ cm ⁻² to form source / drain regions. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. After that, a heat treatment is performed at 950 ° C. for 30 seconds, for example, to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG. 2F, a 100-nm-thick silicon nitride film 8, for example, is deposited on the entire surface by a CVD method to form a sidewall insulating film on the sidewall of the gate portion.

Subsequently, as shown in FIG. 2G, the silicon nitride film is etched by a reactive ion etching method to form a gate sidewall 8.

Next, as shown in FIG. 1H, phosphorus ions are implanted using the gate electrode as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. Thereafter, a heat treatment is performed, for example, at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. further,
By performing a heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, the titanium thin film is entirely reacted with the silicon substrate, and a titanium silicide film 9 is formed only on the source / drain regions. Thereafter, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively peeled off with, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 3J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 2K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a thickness of 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

FIG. 3 shows the Weibull distribution of Qbd in the case where the heat step after fluorine introduction in the n-channel MOSFET is 850 ° C. for 30 minutes and in the case where it is 900 ° C. for 30 minutes. According to this, when heat treatment at 900 ° C. for 30 minutes is performed, not only does the average Qbd decrease, but also a point showing a Qbd value lower than the average value appears, as compared with the heat treatment at 850 ° C. for 30 minutes. It can be seen that long-term reliability against dielectric breakdown is deteriorated. Therefore, after the step of introducing fluorine, it is important not to perform heat treatment at 850 ° C. or more for 30 minutes or more.

Next, a second embodiment of the present invention will be described.

In this embodiment, the salicide (Self-Aligned
The present invention is applied to a semiconductor device using a -Silicide) process, and FIG. 4 is a process sectional view of a manufacturing method thereof.

First, as shown in FIG. 4A, for example, a p-type silicon substrate having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface of the p-type silicon substrate 1 is subjected to a normal selective oxidation method. Thereby, an element isolation insulating film 2 having a thickness of about 0.6 μm is formed. Further, a gate oxide film 3 having a thickness of 8 nm is formed by thermal oxidation using dry oxygen.

Next, as shown in FIG. 2B, a polycrystalline silicon film 4 having a thickness of 200 nm is deposited on the gate oxide film 3 as a gate electrode.

Next, as shown in FIG. 3C, the polycrystalline silicon film 4 is etched by a reactive ion etching method using a resist mask to form a gate portion.

Next, as shown in FIG. 3D, for example, phosphorus ions are implanted into the polycrystalline silicon film 4 and the silicon substrate 1 at an acceleration voltage of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . Subsequently, this is subjected to 950 in a nitrogen atmosphere.
Heat treatment at 30 ° C. for 30 seconds activates phosphorus in the polycrystalline silicon film 4 and forms the source / drain diffusion layers 7a.

Next, as shown in FIG. 9E, a 50-n thick film is formed on the entire surface to form a sidewall insulating film on the sidewall of the gate portion.
m silicon nitride film 8 is deposited by the CVD method.

Subsequently, as shown in FIG. 2F, the silicon nitride film is etched by a reactive ion etching method to form a gate sidewall 8.

Next, as shown in FIG. 2G, phosphorus ions are implanted at 5 × 10 ¹⁵ cm ⁻² using the gate electrode as a mask. Thereafter, a heat treatment is performed, for example, at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 1H, fluorine is ion-implanted over the entire surface at, for example, an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . At this time, the distribution of fluorine immediately after ion implantation is such that peak concentrations are formed in the polycrystalline silicon film 4 and the source / drain diffusion layers 7b, and fluorine is not implanted into the gate oxide film 3. . Subsequently, this is, for example, 800 ° C. in a nitrogen atmosphere,
By performing a heat treatment for 30 minutes, the implanted fluorine is diffused into the gate oxide film 3.

Next, as shown in FIG. 3I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. Further, the titanium thin film is entirely reacted with the polycrystalline silicon film 4 and the silicon substrate 1 by heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, and titanium silicide is formed only on the polycrystalline silicon film serving as a gate electrode and on the source / drain regions. Membranes 5 and 9
To form Thereafter, for example, an aqueous solution of hydrofluoric acid,
An unreacted titanium thin film on the titanium nitride film and the insulating film is selectively removed by a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 1J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 9K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a thickness 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

In the above embodiment, the fluorine ion implantation is performed before the salicide step. However, the present invention is not limited to this. For example, after the salicide step is completed, fluorine ion implantation is performed on the entire surface to perform the heat treatment. The same effect can be obtained even if it is performed.

FIG. 5 is a characteristic diagram of the reliability of the gate oxide film in the first embodiment, for example, and shows Qbd (Charge).
-to-Breakdown).
The black circles in the figure indicate that fluorine is implanted into the polycrystalline silicon film serving as the gate electrode by 1 × 10 ¹⁵ cm ⁻² ions.
This is the case where the amount of fluorine introduced into the oxide film is smaller than the number of silicon atoms in the oxide film. The white squares in the figure indicate the case where the amount of fluorine introduced into the oxide film is made larger than the number of silicon atoms in the oxide film by implanting fluorine at 5 × 10 ¹⁵ cm ⁻² .

When the amount of fluorine introduced into the oxide film is larger than the number of silicon atoms in the oxide film, the average Qbd decreases. This is because, by introducing excessive fluorine, not only the film quality of the interface transition layer is improved, but also fluorine acts on the Si—O—Si network in the oxide film other than the interface transition layer, and the Si—F bond and the Si—O This is because they are separated into bonds. Therefore, the amount of electron traps in the gate oxide film increases rapidly, and Qbd decreases. Therefore, it is necessary to select the amount of fluorine introduced into the gate oxide film so that the number of fluorine atoms in the gate oxide film becomes smaller than the number of silicon atoms in the gate oxide film.

FIG. 6 shows a third embodiment of the present invention, and is a sectional view of the structure of a nonvolatile semiconductor memory (EEPROM) which can be electrically written and erased.
A silicon thermal oxide film 2 for element isolation is formed on a p-type silicon substrate 1, and n-type source / drain diffusion layers 7 are formed on the surface of the silicon substrate by ion implantation of phosphorus.
a and 7b are formed. Further, a first gate insulating film 3a is formed on the surface of the silicon substrate, and fluorine atoms are introduced into the gate insulating film 3a by using a heat process at 850 ° C. or more and not more than 30 minutes. ing. A first polysilicon film 4a is formed on the first gate insulating film 3a.
On b, a second polysilicon film 4b is formed.
A CVD insulating film 6a is formed on the polycrystalline silicon film 4b in the gate electrode portion, and a sidewall insulating film 6b is formed on a side wall of the gate electrode portion. Further, a contact hole is opened in the CVD insulating film 10 serving as an interlayer insulating film, and a wiring 11 is formed.

FIG. 7 is a process sectional view showing a method for manufacturing the nonvolatile semiconductor memory shown in FIG.

First, for example, as shown in FIG.
A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and an element isolation insulating film 2 having a thickness of about 0.6 μm is formed on the surface of the p-type silicon substrate 1 by a normal selective oxidation method. I do. Further, a gate oxide film 3a having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen.

Next, as shown in FIG. 3B, a 200 nm-thick polycrystalline silicon film 4a is deposited as a gate electrode on the gate oxide film 3a. Next, for example, phosphorus ions are implanted into the polycrystalline silicon at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is such that a peak concentration is formed in the polycrystalline silicon 4a. Then, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere,
The implanted phosphor is activated to lower the resistance of the polycrystalline silicon.

Next, as shown in FIG.
An m-thick CVD silicon oxide film 3b and a polycrystalline silicon film 4b having a thickness of 200 nm are continuously deposited. Next, for example, phosphorus is ion-implanted into the entire surface at 5 × 10 ¹⁵ cm ⁻² . The implanted phosphorus ions distribute around the peak depth depending on the acceleration energy in the polycrystalline silicon film 4b. Thereafter, for example, a heat treatment is performed at 950 ° C. for 30 seconds to diffuse and activate phosphorus in the polycrystalline silicon film 4b and the silicon substrate 1.

Next, as shown in FIG. 4D, an acceleration voltage of 20 keV and a dose of 1 are applied to the polycrystalline silicon film 4b.
Fluorine is ion-implanted at × 10 ¹⁵ cm ^-2 . At this time,
The distribution immediately after ion implantation is such that fluorine does not reach the CVD silicon oxide film 3b. Subsequently, this is heat-treated at 800 ° C. for 30 minutes in, for example, a nitrogen atmosphere, so that the implanted fluorine is removed by the gate oxide film 3a and the CVD.
Simultaneously diffuse into the silicon oxide film 3b.

Next, as shown in FIG.
A VD oxide film 6a is deposited.

Next, as shown in FIG. 2F, the gate oxide film 3a, the CVD oxide film 3b, and the polycrystalline silicon film 4 are formed.
a and 4b, the CVD oxide film 6a is patterned by a reactive ion etching method. Subsequently, an oxide film 6b is formed on the side wall of the gate electrode by using a combustion oxidation method using a mixed gas of hydrogen and oxygen.

Next, as shown in FIG. 7G, for example, phosphorus is implanted into the entire surface at 5 × 10 ¹⁵ cm ⁻² . afterwards,
For example, heat treatment is performed at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate 1 and activate it, thereby forming a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG. 1H, a 300 nm thick silicon oxide film 10 is deposited on the entire surface by CVD.

Next, as shown in FIG. 2I, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 9J, a thickness of 80% containing, for example, 0.5% of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

In the above embodiment, fluorine ions are implanted into the second polycrystalline silicon film 4b. However, the present invention is not limited to this. For example, the first polycrystalline silicon film 4a is The same effect can be obtained by performing ion implantation on each of the second polycrystalline silicon films 4b.
However, in this case, it is preferable not to perform the heat treatment at 850 ° C. or more for more than 30 minutes in the step after the introduction of fluorine.

FIG. 8 is a circuit diagram showing the structure of n according to the fourth embodiment of the present invention.
FIG. 9 is a process sectional view illustrating the method for manufacturing the channel MOS transistor.

First, for example, as shown in FIG.
A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and an element isolation insulating film 2 having a thickness of about 0.6 μm is formed on the surface of the p-type silicon substrate by a normal selective oxidation method. .

Next, as shown in FIG. 2B, for example, dichlorosilane (SiH ₂ Cl ₂ ) and nitrous oxide (N
₂ O) is used to form a gate oxide film 3 having a thickness of 8 nm at 850 ° C.
A 0 nm polycrystalline silicon film 4 is formed. Next, for example, phosphorus ions are introduced into the polycrystalline silicon film 4 at an acceleration voltage of 30 ke.
V ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heat-treated in a nitrogen atmosphere at 900 ° C. for 30 minutes to activate the implanted phosphorus, and the polycrystalline silicon film 4 is formed.
Lower the specific resistance.

Next, as shown in FIG. 4C, for example, fluorine is ion-implanted into the polycrystalline silicon film 4 at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . At this time,
The distribution of fluorine immediately after ion implantation is such that a peak concentration is formed in the polysilicon 4 and fluorine is not implanted into the gate oxide film 3. Subsequently, this is heat-treated at 800 ° C. for 30 minutes in a nitrogen atmosphere, for example, to diffuse the implanted fluorine into the gate oxide film 3.

Next, as shown in FIG.
After a silicon oxide film 6 having a thickness of 100 nm is formed by the P-CVD method, a gate film is formed by etching the laminated film including the silicon oxide film 6 and the polycrystalline silicon 4 by a reactive ion etching method.

Subsequently, as shown in FIG. 8E, for example, phosphorus is ion-implanted at 1 × 10 ¹⁵ cm ⁻² to form source / drain regions 7a.

Next, as shown in FIG. 9F, a silicon nitride film 8 having a thickness of about 100 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 1G, the silicon nitride film is etched by anisotropic dry etching to form a sidewall insulating film 8.

Next, as shown in FIG. 1H, phosphorus ions are implanted into the silicon substrate using the gate electrode portion as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon base. Thereafter, for example, a heat treatment is performed at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. continue,
By performing a heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, the titanium thin film is entirely reacted with the silicon substrate, and a titanium silicide film 9 is formed only on the source / drain regions. Thereafter, the titanium nitride film and the unreacted titanium film on the insulating film are selectively peeled off with, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Thereafter, as shown in FIG. 9J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Thereafter, as shown in FIG. 9K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Next, as shown in FIG.
800n thickness containing 0.5% each of copper
After the formation of the m-th aluminum film, the aluminum film is patterned to form the source / drain electrodes 11. After this, 4
Heat treatment is performed at 50 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

Usually, as in the above embodiment, for example, dichlorosilane (SiH ₂ Cl ₂ ) and nitrous oxide (N ₂ O)
When a gate oxide film having a thickness of 5 nm is formed at 850 ° C. by using GaN, the interface level at the silicon / oxide film interface is large, and the film has many electron traps and the like. However, by introducing fluorine, the dangling bonds of silicon in the vicinity of the interface or in the film are terminated, whereby the interface state density can be reduced.

As the gate insulating film, for example, an oxynitride film in which nitrogen atoms are introduced by exposing a silicon oxide film in an ammonia (NH ₃ ) gas atmosphere may be used, and fluorine atoms may be introduced into the oxynitride film. Thus, it is possible to reduce an increase in low electric field leakage current after applying a high electric field stress to the gate insulating film, and to suppress a defect density by using fluorine to obtain a uniform film quality.

Further, as the gate insulating film, an oxide film formed by burning and oxidizing deuterium (D ₂ ) gas and oxygen gas, or an oxide film formed using heavy water (D ₂ O) may be used. In this case, deuterium is taken into the gate oxide film, thereby replacing Si-H having a weak bonding force with deuterium to form a Si-D bond having a strong bonding force, and distorting the interface transition layer by introducing fluorine. In this case, stress relaxation of the Si—O—Si bond occurs, and the gate insulating film can be made stronger against high electric field stress.

Similar effects can be obtained when a silicon oxide film using active oxygen is used as the gate oxide film. In this case, an oxide film is formed by activating oxygen by microwave discharge or ultraviolet irradiation and supplying the activated oxygen to the substrate. The oxide film thus obtained is dense and has few traps, and the interface between the oxide film and the silicon substrate is flat. However, also in this case, an interface transition layer exists near the interface between the oxide film and the silicon substrate, and stress relaxation of the interface transition layer by fluorine enables further improvement in reliability such as further improvement in dielectric breakdown resistance.

Further, as a gate insulating film, SiH ₂ Cl
₂ and and SiCl ₄ and NH ₃ silicon nitride film using such, even in the case of using the silicon nitride film by directly nitriding the silicon substrate due to NH _3, the same effect can be obtained.

FIG. 9 shows an n-type semiconductor device according to a fifth embodiment of the present invention.
FIG. 9 is a process sectional view illustrating the method for manufacturing the channel MOS transistor.

First, as shown in FIG. 9A, for example,
A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and an element isolation insulating film 2 having a thickness of about 0.6 μm is formed on the surface of the p-type silicon substrate 1 by a normal selective oxidation method. I do.

Next, as shown in FIG. 13B, a gate oxide film 3 having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen, and a 200 nm-thick gate electrode is formed thereon.
Is formed. Next, for example, phosphorus ions are implanted into the polycrystalline silicon at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus and reduce the resistance of the polycrystalline silicon film 4.

Next, as shown in FIG. 4C, for example, fluorine is ion-implanted into the polycrystalline silicon film 4 at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . At this time,
The distribution of fluorine immediately after ion implantation indicates that the polycrystalline silicon film 4
A gate oxide film 3 is formed so that a peak concentration is formed therein.
Ensure that no fluorine is implanted inside. Subsequently, this is heat-treated at 800 ° C. for 30 minutes in a nitrogen atmosphere, for example, to diffuse the implanted fluorine into the gate oxide film 3.

Next, as shown in FIG.
After forming a silicon oxide film 6 having a thickness of 150 nm by the P-CVD method, a gate film is formed by etching the laminated film including the polycrystalline silicon film 4 and the silicon oxide film 6 by a reactive ion etching method.

Subsequently, as shown in FIG. 11E, for example, phosphorus is ion-implanted at 1 × 10 ¹⁵ cm ⁻² to form a diffusion layer 7a to be a source / drain region.

Next, as shown in FIG. 1F, a silicon nitride film 8 having a thickness of about 100 nm for forming a side wall insulating film is deposited by a CVD method.

Next, as shown in FIG. 9G, the entire surface of the silicon nitride film is etched by anisotropic dry etching to form a sidewall insulating film 8.

Next, as shown in FIG. 11H, phosphorus ions are implanted using the gate electrode portion as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. Thereafter, for example, a heat treatment is performed at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. continue,
The titanium thin film is entirely reacted with the silicon substrate by heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, and a titanium silicide film 9 is formed only on the source / drain regions. Thereafter, the titanium nitride film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Thereafter, as shown in FIG. 13J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 7K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Next, as shown in FIG. 1 (l), a thickness of 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing hydrogen.

In the above embodiment, phosphorus as a dopant is ion-implanted and activated in the polycrystalline silicon film 4 as a gate electrode, and then fluorine is ion-implanted and diffused into the gate oxide film 3. However, it is also possible to ion implant phosphorus after ion implantation of fluorine. For example, first, fluorine is ion-implanted into the polycrystalline silicon film at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² so that a peak concentration is formed in the polycrystalline silicon film. By performing a heat treatment that does not exceed this, the implanted fluorine is diffused into the gate oxide film. Thereafter, for example, phosphorus ions are implanted into the polycrystalline silicon film at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and a heat treatment (for example, 850 ° C., 20 For example, the implanted phosphorus may be activated by performing a heat treatment for about one minute.

Further, the polycrystalline silicon film serving as the gate electrode can be made of polycrystalline silicon containing phosphorus by using a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ) as a source gas, for example. . in this case,
For example, fluorine is accelerated in polycrystalline silicon at an acceleration voltage of 20 ke.
V, a dose of 1 × 10 ¹⁵ cm ⁻² ions are implanted, followed by a heat treatment at 800 ° C. for 30 minutes in a nitrogen atmosphere to diffuse the implanted fluorine into the gate oxide film. Similar effects can be obtained.

As a method for forming polycrystalline silicon containing phosphorus, silane difluoride (S
By using a mixed gas of iH ₂ F ₂ ) and phosphine (PH ₃ ), polycrystalline silicon containing phosphorus and fluorine can be obtained. This is placed in a nitrogen atmosphere at 800 ° C., 3
A similar effect can be obtained even if fluorine in polycrystalline silicon is diffused into the insulating film by heat treatment for 0 minutes.

In the case of a p-channel MOSFET, for example, BF ₂ ions are implanted into the polycrystalline silicon film at an acceleration voltage of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² , For example, boron ions are accelerated at 10 keV and the dose is 4 × 10 ¹⁵ cm.
Ion implantation at ^-2 . At this time, since the surface layer of the polycrystalline silicon is made amorphous by BF ₂ ion implantation, the implanted boron can be distributed only in the polycrystalline silicon film without causing channeling. Subsequently, this is heat-treated at 800 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted boron and, at the same time, diffuse fluorine into the gate oxide film, thereby obtaining the same effect. It is also possible to prevent excessive introduction of fluorine by BF ₂ .

FIG. 10 is a process sectional view showing a method for manufacturing an n-channel MOS transistor according to the sixth embodiment of the present invention.

First, as shown in FIG. 10A, for example, a p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and a normal selection is made on the surface of the p-type silicon substrate 1. An element isolation insulating film 2 having a thickness of about 0.6 μm is formed by an oxidation method. Further, a gate oxide film 3 having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen.

Next, a polycrystalline silicon film 4 having a thickness of 200 nm is deposited on the gate oxide film 3 as a gate electrode, as shown in FIG. Next, for example, phosphorus ions are implanted into the polycrystalline silicon at an acceleration voltage of 30 keV and a dose of 5
X 10 ¹⁵ cm ^-2 ions are implanted. At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus, thereby lowering the resistance of the polycrystalline silicon film 4.

Next, as shown in FIG. 13C, after depositing a CVD silicon oxide film 6, the polycrystalline silicon film 4, C
The VD silicon oxide film 6 is etched by a reactive ion etching method to form a gate.

Next, as shown in FIG. 1D, for example, phosphorus ions are implanted at 1 × 10 ¹⁵ cm ⁻² . Thereafter, a heat treatment is performed at 900 ° C. for 30 seconds, for example, to diffuse and activate phosphorus in the silicon substrate, thereby forming a diffusion layer 7a to be a source / drain region.

Next, as shown in FIG. 13E, a silicon nitride film having a thickness of 50 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 11F, fluorine ions are implanted at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ⁻² , for example. At this time, the distribution of fluorine immediately after ion implantation is set so that a peak concentration is formed in the silicon nitride film 8.

Next, as shown in FIG. 1G, the silicon nitride film is etched by a reactive ion etching method to form a gate side wall portion 8 containing fluorine. Subsequently, by performing a heat treatment at 800 ° C. for 30 minutes in, for example, a nitrogen atmosphere, the fluorine implanted in the gate sidewall 8 is diffused into the gate oxide film 3.

Next, as shown in FIG. 17H, phosphorus ions are implanted into the silicon substrate using the gate electrode portion as a mask. Thereafter, a heat treatment is performed, for example, at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. further,
By performing a heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, the titanium thin film is entirely reacted with the silicon substrate, and a titanium silicide film 9 is formed only on the source / drain regions. Thereafter, the titanium nitride film and the unreacted titanium thin film on the insulating film are selectively peeled off by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 9J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 9K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a thickness of 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes. After this, 4
Heat treatment is performed at 50 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

Here, the sidewall insulating film 8 made of the silicon nitride film is usually made of dichlorosilane (SiH ₂ Cl).
₂ ) It is formed by an LP-CVD method using ammonia (NH ₃ ) or the like. In this case, a large amount of hydrogen is contained in the nitride film, and this hydrogen diffuses in the oxide film in a large amount. Then, for example, the Si—O—Si network is cut to reduce the dielectric breakdown life. Therefore, in the present embodiment, an insulating film having a low hydrogen content is formed using SiCl ₄ and N ₂ O. Then, fluorine is applied to this insulating film at an acceleration voltage of 5 keV, a dose of 1 × 10 ¹⁵ cm ⁻² ,
Injection is performed at an injection angle of 7 degrees so that fluorine is contained.

In addition to the ion implantation of fluorine into the side wall insulating film having a small hydrogen content as described above, for example, SiF ₄ gas may be used at the time of forming the side wall insulating film, or fluorine radicals generated by microwave discharge or the like may be used. Similar effects can be obtained by mixing.

According to the example described above, fluorine entering the gate oxide film from the side wall insulating film not only improves the reliability of the entire oxide film but also reduces the edge of the gate electrode directly in contact with the side wall insulating film. Improve the reliability of hot carriers at the drain end where impact ionization is likely to occur, and efficiently correct the damaged region of the oxide film with low dielectric breakdown voltage introduced by reactive ion etching or phosphorus ion implantation with fluorine. Can be.

FIG. 11 is a process sectional view showing a method for manufacturing an n-channel MOS transistor according to the seventh embodiment of the present invention.

First, as shown in FIG. 1A, for example,
A p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and an element isolation insulating film 2 having a thickness of about 0.6 μm is formed on the surface of the p-type silicon substrate 1 by a normal selective oxidation method. Form. Further, a gate oxide film 3 having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen.

Next, a polycrystalline silicon film 4 having a thickness of 200 nm is deposited on the gate oxide film 3 as a gate electrode, as shown in FIG. Next, fluorine ions are implanted into the polycrystalline silicon film 4 with, for example, phosphorus ions at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus and lower the resistance of the polycrystalline silicon.

Next, as shown in FIG. 14C, after depositing a CVD silicon oxide film 6, the polycrystalline silicon film 4, C
The VD silicon oxide film 6 is etched by a reactive ion etching method to form a gate.

Next, as shown in FIG. 15D, after phosphorus ions are implanted at 1 × 10 ¹⁵ cm ⁻² , for example, 950 ions are implanted.
A heat treatment is performed at 30 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG.
A silicon nitride film 8 of about 0 nm is deposited by a CVD method.

Next, as shown in FIG. 13F, the silicon nitride film is etched by a reactive ion etching method to form a gate side wall portion 8.

Next, as shown in FIG. 14G, phosphorus ions are implanted using the gate electrode as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. Thereafter, a heat treatment is performed, for example, at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 14H, only the element isolation silicon oxide film 2 is exposed using the resist mask 15. Subsequently, for example, an acceleration voltage of 20 ke
V. Fluorine is ion-implanted at a dose of 1 × 10 ¹⁵ cm ⁻² . At this time, the distribution of fluorine immediately after ion implantation is set so that a peak concentration is formed on the surface of the element isolation oxide film 2. Subsequently, this is, for example, 800 ° C. in a nitrogen atmosphere,
By performing a heat treatment for 30 minutes, the implanted fluorine is diffused into the gate oxide film 3.

Next, as shown in FIG. 14I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. further,
The titanium thin film is entirely reacted with the silicon substrate by heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, and a titanium silicide film 9 is formed only on the source / drain regions.
Thereafter, for example, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively peeled off using an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 13J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 9K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a thickness of 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

FIG. 12 is a process sectional view showing a method for manufacturing an n-channel MOS transistor according to the eighth embodiment of the present invention.

First, as shown in FIG. 12A, for example, a p-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface of the p-type silicon substrate 1 is subjected to normal selective oxidation. The element isolation insulating film 2 having a thickness of about 0.6 μm is formed by the method. Further, a gate oxide film 3 having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen.

Next, as shown in FIG. 14B, a polycrystalline silicon film 4 having a thickness of 200 nm is deposited on the gate oxide film 3 as a gate electrode. Next, for example, phosphorus ions are implanted into the polycrystalline silicon film 4 at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus and reduce the resistance of the polycrystalline silicon. Further, a CVD silicon oxide film 6 is deposited.

Subsequently, as shown in FIG. 15C, for example, an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁵ cm ^{−2 are} applied to the entire surface.
Is used to implant fluorine ions. At this time, the distribution of fluorine immediately after the ion implantation is such that a peak concentration is formed on the surface of the CVD oxide film 6. Subsequently, this is heat-treated at 800 ° C. for 30 minutes in a nitrogen atmosphere, so that the fluorine injected into the CVD silicon oxide film 6 is diffused into the gate oxide film 3.

Next, as shown in FIG. 13D, the polycrystalline silicon film 4 and the CVD silicon oxide film 6 are etched by a reactive ion etching method to form a gate.

Next, as shown in FIG. 14E, after phosphorus ions are implanted at 1 × 10 ¹⁵ cm ⁻² , for example, 950 ions are implanted.
A heat treatment is performed at 30 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG.
A silicon nitride film 8 of about 0 nm is formed by a CVD method.

Next, as shown in FIG. 1G, the silicon nitride film is etched by a reactive ion etching method to form a gate sidewall 8.

Next, as shown in FIG. 17H, phosphorus ions are implanted using the gate electrode as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the substrate. Then, for example, 950
A heat treatment at 30 ° C. for 30 seconds is performed to diffuse and activate phosphorus in the silicon substrate, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. further,
By performing a heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, the titanium thin film is entirely reacted with the silicon substrate, and a titanium silicide film 9 is formed only on the source / drain regions. Thereafter, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively peeled off by using, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 13J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method. At this time, the silicon oxide film 1 serving as an interlayer insulating film is formed.
The same effect can be obtained even if fluorine is introduced in the atmosphere. The introduction of fluorine into the silicon oxide film 10 serving as an interlayer insulating film may be performed by, for example, ion-implanting fluorine into the interlayer insulating film. Further, an oxide film containing fluorine may be formed by a low-pressure plasma CVD method using a mixed gas of silicon fluoride, for example, silicon tetrafluoride (SiH ₄ ) and oxygen, and this may be used as an interlayer insulating film. After forming the interlayer insulating film containing fluorine in this manner, the interlayer insulating film is
The implanted fluorine may be diffused into the gate oxide film 3 by performing a heat treatment at 00 ° C. for 30 minutes.

Next, as shown in FIG. 17K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a silicon and copper having a thickness of 8% containing, for example, 0.5% each.
After forming a 00 nm aluminum film, it is patterned to form source / drain electrodes. After this,
Heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

Note that as a diffusion source for diffusing fluorine into the gate oxide film 3, fluorine may be introduced into a metal to be a wiring. In this case, in the step of FIG. 12 (k), after forming the aluminum film, fluorine may be ion-implanted over the entire surface, and fluorine may be diffused from the fluorine-containing aluminum film into the gate oxide film 3.

Next, a ninth embodiment of the present invention will be described.

FIG. 13 is a structural sectional view of an n-channel transistor fabricated on an SOI substrate according to the ninth embodiment. On the silicon substrate 1, p is interposed via an insulating layer 1a.
A semiconductor layer 1b is formed, and a silicon thermal oxide film 2 for element isolation is formed. On the surface of the semiconductor layer 1b, n-type source / drain diffusion layers 7a and 7b are formed by ion implantation of phosphorus. In addition, the semiconductor layer 1
b, silicon, oxygen,
An insulating film containing nitrogen as a main component is formed. Fluorine atoms are introduced into the gate insulating film 3 from the insulating layer 1a of the SOI substrate by diffusion. A CVD silicon oxide film 6 is formed on a polycrystalline silicon film 4 serving as a gate electrode, and a silicon nitride film 8 is formed on a side wall of the gate electrode.
Are formed. Further, silicide 9 is formed in the source / drain region. A contact hole is opened in the CVD silicon oxide film 10, and an Al electrode 11 serving as a wiring is formed by sputtering and patterned.

FIG. 14 is a process sectional view showing a method for manufacturing an n-channel MOS transistor according to the ninth embodiment.

First, as shown in FIG. 14A, an SOI substrate having a p-type silicon layer 1b formed on a silicon substrate 1 via an insulating layer 1a as a surface layer is prepared, and the p-type silicon layer 1b is formed. An element isolation insulating film 2 having a thickness of about 0.6 .mu.m is formed on the surface of the substrate by a normal selective oxidation method.

Next, as shown in FIG.
For example, an acceleration voltage of 100 keV and a dose of 5 × 10 ¹⁵ cm
Ion implantation of fluorine at ^-2 . At this time, the distribution of fluorine immediately after ion implantation is set so that a peak concentration is formed in the insulating layer 1a of the SOI substrate.

Next, as shown in FIG. 14C, an 8 nm-thick gate oxide film 3 is formed by, for example, thermal oxidation using dry oxygen. At this time, the ion-implanted fluorine is diffused and introduced into the gate oxide film 3, and at the same time, stress existing in the SOI substrate and crystal defects existing at the interface of the insulating layer 1a are simultaneously improved. Subsequently, using a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ), a 200 nm-thick phosphorus-doped polycrystalline silicon film 4 is deposited on the gate oxide film 3 as a gate electrode.

Next, a CVD silicon oxide film 6 is deposited on the polycrystalline silicon film 4 as shown in FIG. Subsequently, the polycrystalline silicon film 4 and the CVD silicon oxide film 6 are etched by a reactive ion etching method to form a gate portion.

Next, as shown in FIG. 17E, for example, phosphorus ions are implanted at 1 × 10 ¹⁵ cm ⁻² . The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon layer 1b. After that, a heat treatment is performed at 950 ° C. for 30 seconds, for example, to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG.
A silicon nitride film 8 of about 0 nm is formed by a CVD method.

Subsequently, as shown in FIG. 15G, the silicon nitride film is etched by a reactive ion etching method to form a gate side wall portion 8.

Next, phosphorus ions are implanted using the gate electrode as a mask, as shown in FIG. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon layer 1b. Thereafter, a heat treatment is performed at, for example, 950 ° C. for 30 seconds to diffuse and activate phosphorus in the silicon layer 1b, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG. 17I, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. further,
By heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere, all of the titanium thin film reacts with the silicon layer 1b,
The titanium silicide film 9 is formed only on the drain region. Thereafter, for example, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively peeled off using an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG. 17J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method.

Next, as shown in FIG. 17K, a contact hole is opened in the silicon oxide film 10 by anisotropic dry etching.

Thereafter, as shown in FIG. 1 (l), a thickness 80% containing, for example, 0.5% each of silicon and copper, respectively.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing hydrogen.

FIG. 15 shows a MOS transistor according to the tenth embodiment.
It is a process sectional view showing the manufacturing method of the capacitor.

First, as shown in FIG. 15A, for example, an n-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface thereof is formed to a thickness of 8 nm using, for example, dry oxygen. The gate oxide film 3 is formed. Next, as shown in FIG. 3B, for example, fluorine gas is activated by microwave discharge, and the fluorine radicals generated by this are supplied to the surface of the gate oxide film 3 in a vacuum. As a result, fluorine is adsorbed on the surface of the gate oxide film 3.
Subsequently, as shown in FIG.
Using a mixed gas of silane and phosphine, a thickness of 200
A nm-doped polycrystalline silicon film 4 is formed. Next, as shown in FIG. 3D, a MOS capacitor can be formed by patterning the polycrystalline silicon film 4.

In the above example, the fluorine adsorbed on the surface of the gate oxide film 3 can be diffused into the oxide film 3 in a heating step when the polycrystalline silicon film 4 is formed. After the polycrystalline silicon film 4 is formed, the film is
By performing heat treatment at 0 ° C. for 30 minutes, fluorine adsorbed on the surface of the oxide film 3 can be efficiently diffused to the silicon substrate / oxide film interface.

In this embodiment, fluorine ion implantation is not required, so that cost and time can be saved.
However, it is desirable that the step of adsorbing fluorine on the surface of the gate oxide film and the step of depositing a polycrystalline silicon film serving as a gate electrode be continuously performed in a vacuum. This is because, for example, when fluorine is adsorbed on the surface of the gate oxide film and then exposed to the atmosphere, the moisture contained in the air reacts with the fluorine and the fluorine is desorbed, and sufficient fluorine is removed from the gate oxide film in a later step. This is because it cannot be taken inside.

In the above embodiment, fluorine radicals generated by microwave discharge of fluorine gas are supplied to the surface of the gate oxide film. However, the present invention is not limited to this. For example, fluorine trichloride (ClF ₃ ) may be used. A similar effect can be obtained by using a representative halide material.

FIG. 16 is a process sectional view showing a method for manufacturing a MOS capacitor according to the eleventh embodiment of the present invention.

First, as shown in FIG. 16A, for example, an n-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface thereof is formed with a thickness of, for example, using dry oxygen. An 8 nm gate oxide film 3 is formed.

Subsequently, a polycrystalline silicon film 4 having a thickness of 200 nm is formed as a gate electrode as shown in FIG. Next, for example, phosphorus ions are implanted into the polycrystalline silicon film 4 at an acceleration voltage of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. Subsequently, this is heated at 900 ° C. in a nitrogen atmosphere for 3 hours.
The heat treatment performed for 0 minutes activates the implanted phosphorus, thereby lowering the resistance of the polycrystalline silicon.

Next, as shown in FIG. 18C, for example, fluorine is ion-implanted into the back surface of the silicon substrate 1 at an acceleration voltage of 50 keV and a dose of 2 × 10 ¹⁵ cm ⁻² . Subsequently, this is heat-treated at, for example, 800 ° C. for 30 minutes in a nitrogen atmosphere to diffuse the implanted fluorine to the silicon substrate / oxide film interface.

Next, as shown in FIG. 19D, the MOS capacitor is formed by etching the polycrystalline silicon film 4 by a dry etching method.

In this embodiment, fluorine is used for the gate oxide film 3.
It can be introduced only into the interface transition layer existing near the silicon substrate / oxide film interface without diffusing the inside, and the reliability can be improved. Further, in this example, fluorine is ion-implanted from the back surface of the silicon substrate. However, if fluorine is introduced into the polycrystalline silicon film serving as the gate electrode and diffusion from this is used together, both interfaces of the gate oxide film are formed. Fluorine can be introduced, and the reliability can be further improved.

FIG. 17 is a process sectional view showing a method for manufacturing an n-channel MOS transistor according to the twelfth embodiment of the present invention.

First, as shown in FIG. 17A, a p-type silicon substrate 1 having, for example, a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface of the p-type silicon substrate 1 is subjected to normal selective oxidation. The element isolation insulating film 2 having a thickness of about 0.6 μm is formed by the method.

Next, as shown in FIG. 18B, a gate oxide film having a thickness of 8 nm is formed by, for example, thermal oxidation using dry oxygen, and a polycrystalline silicon film 4 having a thickness of 200 nm is formed thereon as a gate electrode. Form. Subsequently, for example, phosphorus ions are introduced into the polycrystalline silicon film 4 at an acceleration voltage of 30 ke.
V ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the distribution of phosphorus immediately after the ion implantation is set so that a peak concentration is formed in the polycrystalline silicon film 4. continue,
This is heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere to activate the implanted phosphorus and reduce the resistance of the polycrystalline silicon.

Next, as shown in FIG.
After forming a silicon oxide film 6 having a thickness of 150 nm by the P-CVD method, a gate film is formed by etching the laminated film including the polycrystalline silicon film 4 and the silicon oxide film 6 by a reactive ion etching method.

Next, as shown in FIG. 19D, for example, phosphorus is ion-implanted at 1 × 10 ¹⁵ cm ⁻² to form a diffusion layer 7 a to be a source / drain region.

Next, as shown in FIG.
A silicon nitride film 8 of about 0 nm is formed by a CVD method.

Next, as shown in FIG. 17F, the silicon nitride film is etched by anisotropic dry etching to form a side wall insulating film 8.

Next, as shown in FIG. 17G, phosphorus ions are implanted using the gate electrode portion as a mask. The implanted phosphorus ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. Thereafter, a heat treatment is performed, for example, at 950 ° C. for 30 seconds to diffuse phosphorus into the silicon substrate and activate it, thereby forming a diffusion layer 7b serving as a source / drain region.

Next, as shown in FIG.
For example, fluorine ions are implanted into the drain region at an acceleration voltage of 10 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . Subsequently, this is heat-treated at 800 ° C. for 10 minutes in, for example, a nitrogen atmosphere to diffuse the implanted fluorine into the gate oxide film 3.

Next, as shown in FIG. 2I, a titanium thin film having a thickness of 25 nm and a thyran nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering. continue,
The titanium thin film is entirely reacted with the silicon substrate by heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere to form a titanium silicide film only on the source / drain regions. Thereafter, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively peeled off with, for example, an aqueous solution of hydrogen fluoride or a mixed solution of sulfuric acid and hydrogen peroxide.

Thereafter, as shown in FIG. 19J, a silicon oxide film 10 having a thickness of 300 nm is deposited on the entire surface by the CVD method, and a contact hole is formed in the silicon oxide film 10 by anisotropic dry etching. I do.

Next, as shown in FIG. 17 (k), a thickness of 80% containing, for example, 0.5% each of silicon and copper.
After a 0 nm aluminum film is formed, it is patterned to form source / drain electrodes 11. Thereafter, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.

In the above embodiment, the case where fluorine is introduced into the source / drain regions has been described. However, fluorine may be introduced into both the gate electrode polycrystalline silicon film and the source / drain regions at the same time. In this case, first, after patterning the polycrystalline silicon film, 1 × 10 ¹⁵ cm ⁻² ions of phosphorus are simultaneously implanted into the polycrystalline silicon film serving as the gate electrode and the source / drain regions.
By performing heat treatment at 30 ° C. for 30 seconds, phosphorus is activated in the polycrystalline silicon film and in both the source and drain diffusion layers. Thereafter, fluorine was applied at 10 keV and 1 × 10 ¹⁵ cm
^-2 ions are implanted, fluorine is simultaneously introduced into the polycrystalline silicon film and the source / drain regions, and then this is heat-treated at 800 ° C. for 10 minutes in a nitrogen atmosphere to introduce fluorine into the gate oxide film.

According to the present embodiment, not only the reliability of the entire gate oxide film is improved, but also the reliability of hot carriers at the edge of the gate electrode and the drain end where impact ionization is likely to occur can be improved. The damaged region of the oxide film having a low dielectric breakdown voltage introduced by the reactive ion etching or the phosphorus ion implantation can be efficiently corrected with fluorine.

FIG. 18 is a process sectional view showing the method for manufacturing the MOS capacitor according to the thirteenth embodiment of the present invention.

First, as shown in FIG. 18A, an n-type silicon substrate 1 having, for example, a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared, and the surface thereof is formed to a thickness of 8 nm using, for example, dry oxygen. A gate oxide film 3 is formed.

Next, as shown in FIG.
At 00 ° C., a boron-doped amorphous silicon film (not shown) is deposited to a thickness of 20 nm on the gate oxide film 3 using a disilane (Si ₂ H ₆ ) gas and a boron trifluoride (BF ₃ ) gas. At this time, since boron trifluoride is used as the deposition gas, the deposited boron-added amorphous silicon contains fluorine. Subsequently, the temperature is continuously raised to 600 ° C. in an inert gas atmosphere or a non-oxidizing atmosphere,
Using a silane gas and a diborane gas, a boron-added polycrystalline silicon film 4 is deposited to a thickness of about 200 nm. During the deposition of the boron-added polycrystalline silicon film, the fluorine in the boron-added amorphous silicon diffuses into the gate oxide film 3 and the oxide film characteristics can be improved.

Next, a MOS capacitor can be formed by patterning the polycrystalline silicon film 4 as shown in FIG.

In the above embodiment, disilane gas and boron trifluoride gas have been described as examples of the boron-added amorphous silicon deposition gas. However, the present invention is not limited to this, and silicon gas such as SiH ₂ F ₂ may be used. A similar effect can be obtained by combining a halide gas and diborane gas, or by mixing a small amount of a halogen-based gas with disilane gas and diborane gas. The amount of fluorine introduced into the gate oxide film can be controlled by changing the thickness and the fluorine concentration of the amorphous silicon film sandwiched between the oxide film and the polycrystalline silicon film.

The embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0207]

According to the present invention, the reliability of the gate insulating film can be improved, such as the improvement of the dielectric breakdown characteristics and the low electric field leakage current characteristics of the gate insulating film, and the reliability of the device can be improved. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the manufacturing process of the MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a difference in effect when a heat treatment temperature after fluorine introduction is changed.

FIG. 4 is a sectional view showing a manufacturing process of a MOS transistor according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a difference in effect when a fluorine introduction amount is changed.

FIG. 6 is a structural sectional view of a nonvolatile memory cell according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of the nonvolatile memory cell according to the third embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a MOS transistor according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing the manufacturing process of the MOS transistor according to the fifth embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process of a MOS transistor according to a sixth embodiment of the present invention.

FIG. 11 is a sectional view showing the manufacturing process of the MOS transistor according to the seventh embodiment of the present invention.

FIG. 12 is a sectional view showing the manufacturing process of the MOS transistor according to the eighth embodiment of the present invention.

FIG. 13 is a structural sectional view of a MOS transistor using an SOI substrate according to a ninth embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of a MOS transistor using an SOI substrate according to a ninth embodiment of the present invention.

FIG. 15 is a sectional view showing the manufacturing process of the MOS capacitor portion of the MOS transistor according to the tenth embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing process of the MOS capacitor portion of the MOS transistor according to the eleventh embodiment of the present invention.

FIG. 17 is a sectional view showing the manufacturing process of the MOS transistor according to the twelfth embodiment of the present invention.

FIG. 18 is a sectional view showing the manufacturing process of the MOS capacitor portion of the MOS transistor according to the thirteenth embodiment of the present invention.

FIG. 19 is a diagram showing a difference in effect depending on whether fluorine is introduced or not.

FIG. 20 is a graph showing the relationship between the maximum fluorine concentration in a gate oxide film and 5
The figure which showed the relationship between 0% Qbd and Qbdex defect rate.

FIG. 21 shows the relationship between the maximum fluorine concentration in the gate oxide film and S
diagram showing the relationship iF / Si and SiF ₂ / Si.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1: Semiconductor substrate 3: Gate insulating film 4: Semiconductor film (gate electrode)

Claims (6)

[Claims] A gate insulating film containing at least one of silicon, oxygen and nitrogen and a halogen element;
The maximum element concentration of the halogen element in the gate insulating film is 1
A semiconductor device, wherein the number is from 0 ²⁰ / cm ³ to 10 ²¹ / cm ³ . 2. The semiconductor device according to claim 1, wherein said halogen element is fluorine. 3. A step of forming a gate insulating film containing silicon and at least one of oxygen and nitrogen on a semiconductor substrate, and forming a gate insulating film having a maximum element concentration of 10 ²⁰ / c.
a step of introducing a halogen element so as to be at least m ^{3 and} at most 10 ²¹ / cm ³ . 4. A step of forming a gate insulating film containing silicon and at least one of oxygen and nitrogen on a semiconductor substrate, and a semiconductor for forming a gate electrode containing an activated impurity element on the gate insulating film. A method for manufacturing a semiconductor device, comprising: forming a film; and thereafter, introducing a halogen element into the gate insulating film. 5. The step of introducing a halogen element into a gate insulating film includes introducing a halogen element contained in the semiconductor film or a peripheral region of the gate insulating film into the gate insulating film by heat treatment. The method for manufacturing a semiconductor device according to claim 4, wherein: 6. The method of manufacturing a semiconductor device according to claim 3, wherein said halogen element is fluorine.