JP2006108425A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006108425A
JP2006108425A JP2004293606A JP2004293606A JP2006108425A JP 2006108425 A JP2006108425 A JP 2006108425A JP 2004293606 A JP2004293606 A JP 2004293606A JP 2004293606 A JP2004293606 A JP 2004293606A JP 2006108425 A JP2006108425 A JP 2006108425A
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layer
semiconductor
semiconductor device
fluorine
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Teruo Takizawa
照夫 瀧澤
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Seiko Epson Corp
セイコーエプソン株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having low parasitic resistance and good properties and a method for manufacturing the same.
A method of manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a gate insulating layer 20 above a semiconductor layer 10 provided on an insulating layer 8; and (b) the gate insulating layer. A step of forming a gate electrode 22 above 20, (c) forming a source region 26 and a drain region 14 by introducing impurities into the semiconductor layer 10, and (d) fluorine in the semiconductor layer 10. And (e) forming the low resistance semiconductor metal alloy layers 32 and 34 by reacting the semiconductor of the semiconductor layer 10 with a transition metal. And a process.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device having a MOS field effect transistor formed on an insulating substrate and a method for manufacturing the same.

  An insulated gate transistor formed on an SOI (Silicon On Insulator) layer in which a semiconductor layer is provided on an insulating layer achieves lower power consumption and higher speed operation than when formed on a bulk semiconductor layer. As a device that can be used, research and development have been promoted in recent years.

  In such an insulated gate transistor, since the semiconductor layer is thinned, an increase in parasitic resistance of the source region and the gate region becomes a problem. According to Japanese Patent Laid-Open No. 5-36632, it is known to provide a silicide layer on the surface of the source region and the drain region in order to reduce the parasitic resistance described above.

  When a silicide layer is provided on the surface of the source region and the gate region, silicon is sucked into the silicide layer, so that vacancies are generated and defects and voids may occur. This is presumably because when forming an alloy layer of a semiconductor and a metal such as a silicide layer, atoms constituting the semiconductor layer are sucked into the alloy layer in order to react with the metal. In particular, in an insulated gate transistor provided in an SOI layer, since a semiconductor layer is formed on the insulating layer, silicon constituting the semiconductor layer is limited to a limited number, and this problem becomes significant.

In order to solve this problem, a technique for thinning the silicide layer to the limit has been reported (K. Imai, et al, Symp. On VLSI Tech. Dig., P.116 (1998)). However, when the silicide layer is thinned to the limit, the pattern-dependent resistance value may increase, or an aggregation phenomenon may be caused by the fine line effect.
JP-A-5-36632 K. Imai, et al, Symp. On VLSI Tech. Dig., P.116 (1998)

  An object of the present invention is to solve such problems, and to provide a semiconductor device having low parasitic resistance and good characteristics and a method for manufacturing the same.

A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a source region and a drain region by introducing impurities into the semiconductor layer;
(D) introducing fluorine into the semiconductor layer;
(E) forming a low resistance semiconductor metal alloy layer by reacting the semiconductor of the semiconductor layer with a transition metal;
including.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (d),
The fluorine can be introduced into a region including a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (d),
According to the film thickness of the low resistance semiconductor metal alloy layer formed in the step (e),
The amount of fluorine introduced into the semiconductor layer can be determined.

In the method for manufacturing a semiconductor device according to the present invention,
The semiconductor layer is made of silicon,
The low resistance semiconductor metal alloy layer may be made of a silicide compound.

A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a source region and a drain region by introducing impurities into the semiconductor layer;
(D) forming a low resistance semiconductor metal alloy layer by reacting the semiconductor of the semiconductor layer with a transition metal;
(E) introducing fluorine into the semiconductor layer;
including.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (e),
The fluorine can be introduced into a region including a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (e),
According to the film thickness of the low resistance semiconductor metal alloy layer formed in the step (d),
The amount of fluorine introduced into the semiconductor layer can be determined.

In the method for manufacturing a semiconductor device according to the present invention,
After step (e)
Heat treatment can be performed.

In the method for manufacturing a semiconductor device according to the present invention,
The semiconductor layer is made of silicon,
The low resistance semiconductor metal alloy layer may be made of a silicide compound.

The semiconductor device according to the present invention is
An insulating layer;
A semiconductor layer formed above the insulating layer;
A gate insulating layer formed above the semiconductor layer;
A gate electrode formed above the gate insulating layer;
A source region and a drain region formed in the semiconductor layer;
A low resistance semiconductor metal alloy layer formed above the source region or the drain region;
A fluorine-containing region containing fluorine formed in the semiconductor layer;
including.

In the semiconductor device according to the present invention,
The fluorine-containing region may be a region including a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.

  Hereinafter, an example of the present embodiment will be described.

1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment.

  The semiconductor device 100 includes an insulating layer 8 formed on the support substrate 6, a semiconductor layer 10 formed on the insulating layer 8, a gate insulating layer 20 formed on the semiconductor layer 10, and a gate insulating layer 20 And a sidewall insulating layer 24 formed on the sidewall of the gate electrode 22.

  The semiconductor layer 10 has a drain region 14, a source region 26, and a body region 12 formed between the drain region 14 and the source region 26.

  Further, the semiconductor device 100 includes a first silicide layer 32 formed above the source region 26, a first fluorine-containing region 50 formed between the source region 26 and the first silicide layer 32, and a drain. The second silicide layer 34 formed above the region 14, the second fluorine-containing region 52 formed between the drain region 14 and the second silicide layer 34, and the gate electrode 22 are formed. And a third silicide layer 36 and a third fluorine-containing region 38 formed between the gate electrode 22 and the third silicide layer 36. In the present embodiment, the first silicide layer 32 and the second silicide layer 34 are examples of a low resistance semiconductor metal alloy layer.

  The first fluorine-containing region 50 is formed in a region including the boundary between the first silicide layer 32 and the source region 26. Here, the region including the boundary may be a region including at least a part of the boundary between the first silicide layer 32 and the source region 26.

  The second fluorine-containing region 52 is formed in a region including the boundary between the second silicide layer 34 and the drain region 14. Here, the region including the boundary may be a region including at least a part of the boundary between the second silicide layer 34 and the drain region 14.

  The third fluorine-containing region 38 is formed in a region including the boundary between the third silicide layer 36 and the gate electrode 22. Here, the region including the boundary may be a region including at least a part of the boundary between the third silicide layer 36 and the gate electrode 22.

  The first fluorine-containing region 50, the second fluorine-containing region 52, and the third fluorine-containing region 38 may be any region containing fluorine, and the semiconductor layer includes a region containing fluorine and the silicide layer includes One or both of the regions containing fluorine can be included.

  In addition, the fluorine is not limited to the regions indicated by the first fluorine-containing region 50, the second fluorine-containing region 52, and the third fluorine-containing region 38 in FIG. The silicide layer may also be included in the source region 26, the drain region 14, or the gate electrode 22.

  The features of the semiconductor device 100 according to the present embodiment are as follows.

  Since the first fluorine-containing region 50 and the second fluorine-containing region 52 contain fluorine, silicon (vacant lattice) sucked into the first silicide layer 32 and the second silicide layer 34 is removed. Can be supplemented by fluorine. Thereby, defects and voids generated in the vicinity of the first silicide layer 32 and the second silicide layer 34 can be reduced. Accordingly, it is possible to provide a semiconductor device with reduced parasitic resistance and good characteristics.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. In the manufacturing method described below, the numerical values described as specific examples describe an example in the case of forming an n-channel MOS transistor.

  (1) First, as shown in FIG. 2, an SOI substrate having a support substrate 6, an insulating layer 8 on the support base 6, and a semiconductor layer 10 provided on the insulating layer 8 is prepared. As an SOI substrate, a case where a substrate in which an insulating layer 8 and a semiconductor layer 10 are stacked on a support substrate 6 is used will be described as an example. However, the SOI substrate is not limited to this, and a SIMOX (Separation by Implanted Oxgen) substrate, pasted A laminated substrate or the like can be used. As the semiconductor layer 10, for example, Si, SiGe, GaAs, InP, GaP, GaN, or the like can be used. When the thickness of the semiconductor layer 10 of the prepared SOI substrate is different from a desired thickness, the thickness can be adjusted by performing sacrificial oxidation or wet etching with hydrofluoric acid.

  Instead of the SOI substrate, a substrate in which a silicon layer is formed on sapphire, a substrate in which a silicon layer recrystallized by laser annealing or the like is formed on a quartz substrate or a glass substrate, or the like may be used.

Next, as shown in FIG. 2, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 in order to adjust the threshold value. This impurity can be introduced by an ion implantation method. For example, in the case where an n-channel MOS transistor is formed using a single crystal silicon layer having a thickness of 50 nm as the semiconductor layer 10, BF 2 is used as an impurity and the energy of 30 keV is 1 to 5 × 10 12 / About 2 cm 2 can be driven.

  (2) Next, as shown in FIG. 3, the gate insulating layer 20 and the gate electrode 22 are formed. As the gate insulating layer 20, for example, a silicon oxide film can be formed by a thermal oxidation method. Next, a conductive layer (not shown) for the gate electrode 22 is formed on the gate insulating layer 20. As the conductive layer, for example, a polycrystalline silicon layer can be deposited to a thickness of about 200 nm. Then, the gate electrode 22 is formed by patterning this conductive layer by a known lithography and etching technique.

  (3) Next, as shown in FIG. 4, a sidewall insulating layer 24 is formed on the side surface of the gate electrode 22. The sidewall insulating layer 24 can be formed, for example, as follows. An insulating layer (not shown) is formed over the entire surface of the semiconductor layer 10. As the insulating layer, a silicon nitride film, a silicon oxide film, or a stacked film thereof can be used. Thereafter, the sidewall insulating layer 24 can be formed on the side surface of the gate electrode 22 by performing anisotropic etching on the insulating layer.

  (4) Next, as shown in FIG. 4, the source region 26 and the drain region 14 are formed.

  An impurity of a predetermined conductivity type is introduced into the semiconductor layer 10 by a known method in a region for forming the source region 26 and the drain region 14. For example, P is used as an impurity. When the impurity is introduced by ion implantation, the oblique ion implantation method can be used to introduce the impurity into the semiconductor layer 10 covered with the sidewall insulating layer 24. Thereafter, heat treatment is performed to activate the introduced impurities.

  (5) Next, the first silicide layer 32, the second silicide layer 34, and the third silicide layer 36 are formed. These are made of a silicide compound such as titanium silicide, cobalt silicide, nickel silicide, and molybdenum silicide.

  First, as shown in FIG. 5, a metal layer 32 a is formed on the entire upper surface of the semiconductor layer 10. As the metal layer 32a, for example, about 20 nm of Ti is deposited by sputtering. The metal layer 32a may be Co, Ni, Mo, Pt, or Rb. Note that the metal layer 32 a is also formed above the gate electrode 22.

(6) Next, a first heat treatment is performed to cause the metal layer 32a, the semiconductor layer 10 and the gate electrode 22 to undergo a silicidation reaction. As a result, as shown in FIG. 6, a first silicide layer 32, a second silicide layer 34, and a third silicide layer 36 are formed. This first stage heat treatment can be performed, for example, using the RTA method at a processing temperature of 500 ° C. to 700 ° C. Next, the unreacted metal layer 32a is removed. The unreacted metal layer 32a can be removed by wet etching using a mixed solution of NH 4 OH, H 2 O 2 , and H 2 O.

  Thereafter, a second heat treatment is performed to make the first silicide layer 32, the second silicide layer 34, and the third silicide layer 36 more stable, and the low resistance first silicide layer. 32, a second silicide layer 34, and a third silicide layer 36 are formed. The second-stage heat treatment can be performed under a condition where the treatment temperature is 800 ° C. or higher.

  (7) Next, the first fluorine-containing region 50, the second fluorine-containing region 52, and the third fluorine-containing region 38 are formed.

First, as shown in FIG. 6, fluorine is introduced using a known method such as an ion implantation method. When introducing fluorine by an ion implantation method, for example, BF 2 is plasma ionized and only fluorine ions are selectively implanted. With respect to the depth at which fluorine is implanted, the implantation energy is adjusted so that fluorine is implanted at the boundary between the first silicide layer 32 and the source region 26 and the boundary between the second silicide layer 34 and the drain region 14.

  The amount of fluorine to be implanted is determined according to the amount of vacancies generated when the first silicide layer 32 and the second silicide layer 34 are formed. The generation of vacancies leads to the generation of the above-described defects and voids. The amount of vacancies generated can be determined, for example, by observing the cross section of the semiconductor device 100 with a transmission electron microscope. Further, the amount of vacancies generated depends on the composition of the first silicide layer 32 and the second silicide layer 34 and the lattice constant, so the type and supply amount of the metal layer (that is, the thickness of the deposited metal layer). Depending on the above, the amount of fluorine to be injected can be determined. Furthermore, since the film thicknesses of the first silicide layer 32 and the second silicide layer 34 vary depending on the conditions at the time of forming these silicide layers, the amount of fluorine to be implanted can be determined according to the conditions. Here, the conditions include the type of metal used for the metal layer 32a, the temperature of heat treatment, the time of heat treatment, and the like.

As specific ion implantation conditions, the implantation energy is about 10 to 20 keV, and the dose is about 1 × 10 12 to 1 × 10 15 cm −2 . As a result, the fluorine concentration in the first fluorine-containing region 50 and the second fluorine-containing region 52 is about 1 × 10 17 to 1 × 10 20 cm −3 .

  (8) Next, heat treatment is performed to react fluorine, and as shown in FIG. 1, the first fluorine-containing region 50, the second fluorine-containing region 52, and the third fluorine-containing region 38 are formed. . The heat treatment temperature here is 400 to 800 ° C., for example.

  The semiconductor device 100 according to this embodiment can be formed by the above steps.

3. Modifications The present invention is not limited to the above-described embodiments, and can be modified within the scope of the gist of the present invention. An example of a modification will be described below.

3.1. First Modification In the method for manufacturing the semiconductor device 100 described above, the first silicide layer 32, the second silicide layer 34, and the third silicide layer 36 are formed in the steps (5) and (6). Later, in the step (7) and the step (8), the first fluorine-containing region 50, the second fluorine-containing region 52, and the third fluorine-containing region 38 are formed. Instead, in the first modification, after the step (4) described above, the step (7) of introducing fluorine into the semiconductor layer 10 is performed, and then the step (5) and the step (6) are performed. A first silicide layer 32, a second silicide layer 34, and a third silicide layer 36 are formed. In the first modification, since the heat treatment is performed in the step (6), the step (8) that is a heat treatment step after the introduction of fluorine can be omitted. The other manufacturing processes are the same as the manufacturing processes described above, and thus the description thereof is omitted.

  Thus, by introducing fluorine before the formation of the silicide layer, it is easier and more reliable at the boundary between the silicide layer and the drain region 14 or the source region 26, which is a position where defects and voids are frequently generated. Fluorine can be introduced.

3.2. Second Modification Next, a semiconductor device 200 according to a second modification will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a semiconductor device 200 according to the second modification.

  The source region and drain region of the semiconductor device 200 are different from the semiconductor device 100 in that they have an elevated structure. The semiconductor device 200 includes a first drain region 16 and a first source region 28 formed in the semiconductor layer 10, a second drain region 17 and a second source region 27 formed above the semiconductor layer 10, including.

  In the second modification, the first source region 28 and the first drain region 16 are not in contact with the insulating layer 8, but are not limited thereto, and may have a structure in contact with the insulating layer 8. Good. The second source region 27 and the second drain region 17 are formed above the semiconductor layer 10 by the following method after forming the first source region 28 and the first drain region 16 by the above-described step (4). The semiconductor layer can be formed by further selective growth.

  First, a single crystal silicon film is epitaxially grown above the semiconductor layer 10 by an ultrahigh vacuum CVD method. At this time, growth may be performed while mixing impurities of a predetermined conductivity type, or impurities may be introduced by ion implantation or the like after the semiconductor layer is deposited.

  Further, the semiconductor device 200 includes a first silicide layer 33 formed above the second source region 27, a second silicide layer 35 formed above the second drain region 17, and a first silicide layer. A first fluorine-containing region 54 formed between the layer 33 and the second source region 27, and a second fluorine-containing region formed between the second silicide layer 35 and the second drain region 17. Region 56.

  Since the configuration and manufacturing process of the other semiconductor device 200 are the same as those described above, the description thereof will be omitted.

3.3. Third Modification Next, a semiconductor device 300 according to a third modification will be described with reference to FIG. FIG. 8 is a cross-sectional view schematically showing a semiconductor device 300 according to the third modification.

  The semiconductor device 300 is different from the semiconductor device 100 in that the first silicide layer 42 and the second silicide layer 44 are in contact with the insulating layer 8 and that the semiconductor device 300 further includes an extension region 19 and an extension region 30.

  Since the first silicide layer 42 and the second silicide layer 44 are in contact with the insulating layer 8, voids that are vacancies or aggregates are likely to be generated in the vicinity of the silicide layer 42 and the second silicide layer 44. . The fluorine-containing regions 58 and 60 according to the present invention are particularly effective in the third modification because they suppress vacancies and voids. On the other hand, since the silicide film thickness can be increased to the film thickness of the semiconductor layer 10, the parasitic resistance of the semiconductor device 300 can be further reduced.

The manufacturing method of the semiconductor device 300 is different from the manufacturing method of the semiconductor device 100 in the following points. The manufacturing method of the semiconductor device 300 further includes a step of forming the extension region 19 and the extension region 30 by introducing impurities into the semiconductor layer 10 after the step (2) of the manufacturing method of the semiconductor device 100 described above. Specifically, P is implanted at a dose of about 1 × 10 13 to 1 × 10 15 cm −2 by ion implantation. As or the like may be used as an impurity. The depths of the extension region 19 and the extension region 30 can be determined by changing the tilt angle from 7 ° to 45 ° or setting the value of the implantation energy by the oblique ion implantation method.

  Further, in the method for manufacturing the semiconductor device 300, the thickness of the metal layer 32a in FIG. 5 is adjusted so that the first silicide layer 42 and the second silicide layer 44 are in contact with the insulating layer 8. The thickness of the metal layer 32 a in the manufacturing process of the semiconductor device 300 is adjusted to be thicker than that of the metal layer 32 a in the manufacturing process of the semiconductor device 100. Specifically, when forming titanium silicide, if a titanium film thickness 1 is deposited, the formed titanium silicide film thickness is approximately 2.6. Therefore, the titanium film thickness is adjusted so that the film thickness of the semiconductor layer 10 is about 2.6 times the titanium film thickness. For example, if a titanium layer is deposited to a thickness of 20 nm or more (for example, 25 nm) as a metal layer 32a with respect to a thickness of 50 nm of the semiconductor layer 10, the first silicide layer 42 and the second silicide layer 44 are formed as the insulating layer 8. It can be formed in contact. When forming cobalt silicide, nickel silicide, or the like instead of titanium silicide, it is necessary to set the thickness of the metal layer 32a in consideration of the ratio of the metal thickness to the silicide thickness. Fluorine may be introduced in the same manner as in the step (7). However, if it is performed after the step (4), that is, before the silicide formation in the step (5), the fluorine is converted into the silicide and the semiconductor layer at the time of silicide formation. Since the segregation phenomenon that precipitates at the interface can be used, it is convenient to form the fluorine-containing regions 58 and 60. Thus, the semiconductor device 300 according to the third modification can be formed.

  Since the configuration and manufacturing process of the other semiconductor device 300 are the same as those described above, the description thereof will be omitted.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the semiconductor device concerning a 2nd modification. Sectional drawing which shows typically the semiconductor device concerning a 3rd modification.

Explanation of symbols

  6 support base, 8 insulating layer, 10 semiconductor layer, 12 body region, 14 drain region, 20 gate insulating layer, 22 gate electrode, 24 sidewall insulating layer, 26 source region, 32 first silicide layer, 34 second silicide Layer, 36 third silicide layer, 38 third fluorine-containing region, 100 semiconductor device 200 semiconductor device, 300 semiconductor device

Claims (11)

  1. (A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
    (B) forming a gate electrode above the gate insulating layer;
    (C) forming a source region and a drain region by introducing impurities into the semiconductor layer;
    (D) introducing fluorine into the semiconductor layer;
    (E) forming a low resistance semiconductor metal alloy layer by reacting the semiconductor of the semiconductor layer with a transition metal;
    A method for manufacturing a semiconductor device, comprising:
  2. In claim 1,
    In the step (d),
    A method for manufacturing a semiconductor device, wherein the fluorine is introduced into a region including a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.
  3. In claim 1 or 2,
    In the step (d),
    According to the composition of the low resistance semiconductor metal alloy layer formed in the step (e) and the supply amount of the transition metal,
    A method for manufacturing a semiconductor device, wherein an amount of fluorine introduced into the semiconductor layer is determined.
  4. In any one of Claims 1 thru | or 3,
    The semiconductor layer is made of silicon,
    The method of manufacturing a semiconductor device, wherein the low-resistance semiconductor metal alloy layer is made of a silicide compound.
  5. (A) forming a gate insulating layer above the semiconductor layer provided on the insulating layer;
    (B) forming a gate electrode above the gate insulating layer;
    (C) forming a source region and a drain region by introducing impurities into the semiconductor layer;
    (D) forming a low resistance semiconductor metal alloy layer by reacting the semiconductor of the semiconductor layer with a transition metal;
    (E) introducing fluorine into the semiconductor layer;
    A method for manufacturing a semiconductor device, comprising:
  6. In claim 5,
    In the step (e),
    A method for manufacturing a semiconductor device, wherein the fluorine is introduced into a region including a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.
  7. In claim 5 or 6,
    In the step (e),
    According to the composition of the low resistance semiconductor metal alloy layer formed in the step (d) and the supply amount of the transition metal,
    A method for manufacturing a semiconductor device, wherein an amount of fluorine introduced into the semiconductor layer is determined.
  8. In any of claims 5 to 7,
    After step (e)
    A method for manufacturing a semiconductor device, wherein heat treatment is performed.
  9. In any one of claims 5 to 8,
    The semiconductor layer is made of silicon,
    The method of manufacturing a semiconductor device, wherein the low-resistance semiconductor metal alloy layer is made of a silicide compound.
  10. An insulating layer;
    A semiconductor layer formed above the insulating layer;
    A gate insulating layer formed above the semiconductor layer;
    A gate electrode formed above the gate insulating layer;
    A source region and a drain region formed in the semiconductor layer;
    A low resistance semiconductor metal alloy layer formed above the source region or the drain region;
    A fluorine-containing region containing fluorine formed in the semiconductor layer;
    Including a semiconductor device.
  11. In claim 10,
    The fluorine-containing region is a semiconductor device that includes a boundary between the source region or the drain region and the low-resistance semiconductor metal alloy layer.
JP2004293606A 2004-10-06 2004-10-06 Semiconductor device and its manufacturing method Withdrawn JP2006108425A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009537975A (en) * 2006-05-16 2009-10-29 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Dual wiring type integrated circuit chip
WO2012062791A1 (en) * 2010-11-11 2012-05-18 International Business Machines Corporation Creating anisotrpically diffused junctions in field effect transistor devices
JP2013251526A (en) * 2012-06-04 2013-12-12 Samsung Display Co Ltd Thin film transistor, thin film transistor display board equipped with the same and manufacturing method of the same

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Publication number Priority date Publication date Assignee Title
JPH10261588A (en) * 1997-03-19 1998-09-29 Mitsubishi Electric Corp Semiconductor device
JPH1140803A (en) * 1997-07-15 1999-02-12 Toshiba Corp Semiconductor device and its manufacture
JP2000183355A (en) * 1998-12-18 2000-06-30 Hitachi Ltd Manufacture of semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261588A (en) * 1997-03-19 1998-09-29 Mitsubishi Electric Corp Semiconductor device
JPH1140803A (en) * 1997-07-15 1999-02-12 Toshiba Corp Semiconductor device and its manufacture
JP2000183355A (en) * 1998-12-18 2000-06-30 Hitachi Ltd Manufacture of semiconductor integrated circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009537975A (en) * 2006-05-16 2009-10-29 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Dual wiring type integrated circuit chip
WO2012062791A1 (en) * 2010-11-11 2012-05-18 International Business Machines Corporation Creating anisotrpically diffused junctions in field effect transistor devices
US8633096B2 (en) 2010-11-11 2014-01-21 International Business Machines Corporation Creating anisotropically diffused junctions in field effect transistor devices
US8796771B2 (en) 2010-11-11 2014-08-05 International Business Machines Corporation Creating anisotropically diffused junctions in field effect transistor devices
JP2013251526A (en) * 2012-06-04 2013-12-12 Samsung Display Co Ltd Thin film transistor, thin film transistor display board equipped with the same and manufacturing method of the same
US9793377B2 (en) 2012-06-04 2017-10-17 Samsung Display Co., Ltd. Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof

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