JP2006114747A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize improvements in MISFET characteristics by increasing the quality of an interface between a high-dielectric gate insulated film and a silicon substrate. <P>SOLUTION: In a method for manufacturing a semiconductor device having a high-k film 21 and a gate electrode 24 formed on a silicon substrate 11, annealing treatment 23 is applied to the substrate after formation of the high-k film in a fluorine atmosphere, and thereafter, the process temperature is set to be lower than 600°C. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a high dielectric constant film (High-k film) is applied to a gate insulating film for an insulated gate field effect transistor (MISFET). .

Patent Document 1 discloses that in a semiconductor device in which an insulating film and a gate electrode are formed on a silicon substrate, dangling bonds existing at the interface with the silicon substrate are terminated by adding fluorine to the insulating film. However, it does not show that fluorine annealing is performed at a low temperature before electrode formation.
JP 2001-257344 A

  A metal gate is usually a material advantageous for a high-k film, but the film-forming temperature of a high-k film is often low, and it is normal that it does not go through a thermal process that improves the silicon substrate interface state. is there. Further, in the process of forming the source / drain in the silicon substrate (gate retrofitting process such as damascene gate), the original insulating film is often formed after the salicide is formed (for example, less than 500 ° C. for NiSi). This is another factor that cannot be applied at high temperatures.

  As described above, it is inevitable that the interface state of the silicon substrate is not recovered by the thermal process as the temperature is lowered, and there are many interface states. As a method for reducing this, it is possible to perform a hydrogen annealing step. However, in hydrogen and deuterium, the degree of recovery is limited by temperature. For example, a sintering step performed after wiring formation is less than about 500 ° C., A big effect cannot be expected.

  Further, when hydrogen is present in the vicinity of the interface, it is said that NBTI (Negative Bias Temperature Instability) is further deteriorated, which greatly affects reliability. As for the method of introducing fluorine by ion implantation, it is difficult to sufficiently introduce fluorine to the interface when, for example, a gate post-attachment process (damascene gate process or the like) is performed.

  As described above, it is impossible to introduce the high temperature required for the modification of the interface of the silicon substrate, and there is a limit of the sinter, so the influence on the device is immeasurable. As the interface state increases, there are serious problems such as deterioration of mobility and reduction of resistance to BT stress.

  The present invention has been made in view of the above-described circumstances. In a MISFET, fluorine is introduced into a gate insulating film (high dielectric gate insulating film) including a high-k film at a low temperature, thereby enabling a high-performance MISFET. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  In order to solve the above problems, a first invention according to a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a high-k film and a gate electrode are formed on a silicon substrate. An annealing process is performed, and the subsequent process temperature is 600 ° C. or lower and about 500 ° C.

  According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a high-k film and a gate electrode are formed on a silicon substrate, wherein the electrode is stacked on the high-k film after the high-k film is formed. A thin insulating film is formed, and fluorine is contained in the interface region between the high-k film and the ultrathin insulating film.

  The present invention can improve the characteristics of the MISFET by modifying the interface between the silicon substrate and the high dielectric gate insulating film and the film quality of the high dielectric gate insulating film.

Hereinafter, some of the embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
First, Embodiment 1 of the present invention will be described with reference to FIGS. First, as shown in FIG. 1, an STI (shallow trench isolation) 12 is formed on a silicon substrate 11, and a sacrificial oxide film 13 is further formed. Well implantation 14 is performed through the sacrificial oxide film 13. Next, the sacrificial oxide film 13 is removed by etching, and then a cleaning process before forming the oxide film is performed.

  Next, as shown in FIG. 2, a dummy gate insulating film 15 having an arbitrary thickness is formed on the surface of the silicon substrate 11, and then a dummy gate electrode 16 made of an amorphous or poly-silicon film or a silicon germanium film is deposited.

  Next, as shown in FIG. 3, after processing the dummy gate electrode 16, the extension layer 111a and halo impurities are ion-implanted, and further, sidewalls 18 are formed, and source-drain impurities are ion-implanted. Activation annealing is performed. The activation annealing is, for example, spike annealing (spike annealing) at about 1050 ° C. for several seconds. In this manner, a shallow junction source / drain diffusion layer 111 is formed. Here, the extension layer 111a and the source / drain diffusion layer 111 are diffusion layers of the same conductivity type, and the halo is a diffusion layer of opposite conductivity type.

  The activation annealing for forming the source / drain diffusion layer 111 and the like in a shallow junction includes heat treatment by a low thermal budget such as flash lamp annealing and laser annealing. Here, in flash lamp annealing, a white light xenon (Xe) flash lamp having a light emission wavelength in a wide range from the visible region to the near infrared region may be used. This Xe flash lamp is a light source capable of emitting light for a very short time of several hundred microseconds to several tens of milliseconds, and the activation annealing can be performed at a processing temperature of 450 to 600 ° C. and a processing time of about 10 milliseconds.

  Thereafter, as shown in FIG. 4, a metal film such as Co or Ni is formed by sputtering, and a silicide layer 19 is formed on the surface of the source / drain diffusion layer 111 at a low temperature by a known salicide technique.

  Next, as shown in FIG. 5, an interlayer film 20 of a nitride film 201 and an oxide film 202 is formed. CMP (Chemical Mechanical Polishing) is performed using the underlying nitride film 201 as a stopper to expose the dummy gate electrode 16 of an amorphous or poly-silicon film or silicon germanium film, and the dummy gate electrode 16 is removed by etching. 11 is exposed.

Thereafter, as shown in FIG. 6, a high-k material such as HfO ₂ is deposited by ALD (Atomic Layer Deposition) or MOCVD (Metal Organic Chemical Vapor Deposition), and the exposed silicon substrate 11 surface and interlayer film 20 surface. A high-k film 21 is formed. In this way, the high-k film 21 is formed directly on the silicon substrate 11 as an insulating film constituting the high dielectric gate insulating film.

Here, as the high-k film 21, in addition to the above-described HfO _2, a metal oxide such as ZrO ₂ , a metal silicate such as HfSiOx and ZrSiOx, a metal aluminate such as HfAlOx and ZrAlOx, La ₂ O ₃ , Y ₂ It is preferable to use a high dielectric constant film material mainly composed of an oxide of a lanthanoid element such as O ₃ . An insulating film having a laminated structure in which two or more kinds of insulating films are selected from the high-k films made of the high dielectric constant film material and stacked may be used.

Thereafter, as shown in FIG. 7, plasma treatment is performed in an oxygen atmosphere to compensate for oxygen vacancies in the high-k film 21. By this process, an SiO ₂ interface forming film 22 is formed at the interface between the silicon substrate 11 and the high-k film 21 at the same time. This SiO ₂ interface forming film 22 is formed to a thickness of about sub-nanometers at about 400 ° C.

After forming the high-k film 21 and the SiO ₂ interface forming film 22 constituting the high dielectric gate insulating film as described above, an F ₂ atmosphere (mixing ratio with nitrogen) is introduced for the purpose of introducing fluorine into the interface. In an atmosphere diluted to a concentration of about 1 vol.% To 10 vol.%), The temperature is raised from 100 ° C. to 400 ° C., and F ₂ annealing 23 is performed through a process of holding for about 1 to 10 minutes. By taking this process, no special annealing treatment is performed when fluorine is added. By this treatment, it is possible to realize a state in which a large amount of fluorine is localized in the high-k film 21, the SiO ₂ interface formation film 22, and particularly in the vicinity of the interface with the silicon substrate 11 (see FIG. 11). This interface has fluorine in an amount of 10 ²⁰ / cm ³ or more.

It has been mentioned the _{F 2} as the gas atmosphere introducing fluorine, this example fluorocarbon-based gas containing fluorine _{(CF 4, C 2 F 6} , C 3 F 8, C 4 F 8, C 4 F 4, C 4 _{F 6, C} 5 F ₈₎ and trifluoromethane _(CHF 3), difluoromethane _{(CH 2 F} 2), sulfur hexafluoride _(SF 6), nitrogen trifluoride _(NF 3), chlorine trifluoride (ClF ₃ ), The same effect has been confirmed. However, F ₂ is desirable for realizing at a low temperature of 400 ° C. or lower.

Alternatively, the NF ₃ gas and the F ₂ gas are plasma-excited, the ionic species are removed from the active species of fluorine generated by the plasma excitation, and the surface of the high-k film 21 is irradiated with fluorine neutral radicals. So-called remote plasma treatment of fluorine may be performed. Also in this case, a large amount of fluorine can be introduced into the high-k film 21, the SiO ₂ interface forming film 22, and in the vicinity of the interface with the silicon substrate 11 at a low temperature of 400 ° C. or lower.

  Thereafter, as shown in FIG. 8, a metal film such as TiN or W is formed by a CVD method or the like, processed by a known dry etching technique to form a gate electrode 24, and a source / drain contact 25 is formed. Through the wiring material process, for example, an arbitrary circuit is configured using W or Al. Processes after the formation of the high-k film 21 such as formation of a metal gate electrode are performed at a low temperature of 600 ° C. or lower. Thus, by using a low temperature process of 600 ° C. or lower, activation of fluorine contained in the high dielectric gate insulating film is suppressed and stabilized, and a high quality high dielectric gate insulating film and interface can be obtained. It becomes like this. In addition, by using the low temperature process in this way, problems such as film quality deterioration of the high-k film 21 and aggregation of the silicide layer 19 are eliminated.

  As the gate electrode 24, in addition to TiN, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or TiSixNy, ZrSixNy, HfSixNy, VSixNy, NbSixNy, TaSixNy, MoSixNy, or a conductive material such as WSixNy. The laminated material can be used. Alternatively, metals such as Ti, Zr, Hf, V, Nb, Ta, Mo, W, TiSix, ZrSix, HfSix, VSix, NbSix, TaSix, MoSix, WSix, NiSix, CoSix, and other metal silicides, TiCx, ZrCx, A conductive film material made of a metal carbide such as HfCx, VCx, NbCx, TaCx, MoCx, WCx, or a stacked material thereof can be used. Moreover, Al, Al alloy, Cu, Cu alloy, etc. can be used instead of W.

Next, effects in one example of the first embodiment will be described.
With respect to the MISFET subjected to the fluorine treatment, the gate region is formed in a structure of W / TiN / HfO ₂ (film thickness 2.5 nm) / SiO ₂ (film thickness 0.5 nm). It is as FIG. Here, the fluorine distribution in the high dielectric gate insulating film is as shown in FIG. 11 by the treatment of the fluorine gas. The activation annealing of the source / drain diffusion layer at the time of the dummy gate is 1000 ° C. for about 3 seconds, and the final sintering is 400 ° C. In addition, the MISFET that is not subjected to the fluorine treatment does not perform only the fluorine annealing process, and the other processes are the same.

FIG. 9 shows the mobility of the MISFET with and without the fluorine treatment. The horizontal axis indicates the electric field strength (Eeff (MV / cm)), and the vertical axis indicates the mobility (μ (cm ² / Vs)). FIG. 9A shows the mobility of the N-type MISFET, and FIG. 9B shows the mobility of the P-type MISFET. Both N-type and P-type have improved mobility by fluorine treatment. The N-type MISFET has improved mobility over the entire electric field (horizontal axis) as compared with the P-type MISFET, indicating that more effects are obtained by the fluorine treatment.

In FIG. 10, the right part of the horizontal axis shows the case where the fluorine-based gas treatment is performed, and the left part shows the case where the fluorine-based gas treatment is not performed. The vertical axis on the right side shows the interface state (Dit (cm ⁻² eV ⁻¹ )), and the vertical axis on the left side shows NBTI (Negative Bias Temperature Instability) (ΔVth (V)). White circles indicate N-type MISFETs, and black circles indicate P-type MISFETs. The line graph shows the difference in the interface state between the N-type and P-type MISFETs using the right vertical axis. The bar graph uses the vertical axis on the left side to show the variation of the threshold value due to the fluorine-based gas treatment.

  As shown in FIG. 10, it can be seen that both the N-type and P-type have greatly improved since the interface state is lowered by the fluorine-based gas treatment. In particular, it can be seen that the N-type interface state is smaller than the P-type. Moreover, it is shown that the fluctuation of the threshold value is reduced by the fluorine-based gas treatment. As a result, when BT stress is applied, the difference in device reliability is also clear, and it is confirmed that both device characteristics and reliability can be satisfied simultaneously.

FIG. 11 shows the amount of fluorine introduced in the vicinity of the interface between the silicon substrate 11 and the gate insulating films 21 and 22, and the amount of fluorine introduced in the vicinity of the interface shows 1 × 10 ²⁰ / cm ³ or more. Thereby, it is known that the effect is more obtained when the amount of fluorine introduced is 1 × 10 ²⁰ / cm ³ or more near the interface.

(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIGS. 1 to 6 and FIGS. The feature of this embodiment resides in that after the ultra-thin insulating film is further formed on the high-k film described in the first embodiment, fluorine is introduced as described above. Alternatively, an ultra-thin insulating film containing fluorine is stacked on the high-k film. By doing so, a larger amount of fluorine can be easily introduced into the interface region between the high-k film and the ultrathin insulating film.

  In the case of the second embodiment, as in the case of the first embodiment, the high-k film 21 constituting the damascene gate shown in FIG. 6 is formed through the steps of FIGS.

Thereafter, as shown in FIG. 12, plasma treatment is performed in an oxygen atmosphere to compensate for oxygen vacancies in the high-k film 21. At the same time, the SiO ₂ interface forming film 22 is formed at the interface between the silicon substrate 11 and the high-k film 21 by this process. The SiO ₂ interface formation film 22 is formed at a temperature of about 400 ° C., for example, with a thickness of about 0.5 nm.

Thereafter, as shown in FIG. 13, an ultrathin insulating film 26 having a thickness of about 0.5 nm to 1.5 nm is formed by, for example, ALD. In the ALD method, for example, dichlorosilane gas (SiH ₂ Cl ₂ ), water (H ₂ O) or the like is used as a precursor of a film forming material, and a silicon oxide film is deposited at a film forming temperature of about 200 to 300 ° C. In this case, the ALD film forming apparatus for forming the high-k film 21 and the film forming apparatus for forming the ultrathin insulating film 26 have a multi-chamber structure, and the high-k film 21 and the ultrathin insulating film 26 It is preferable to form a film continuously in the apparatus. Here, a silicon nitride film, a silicon oxynitride film, or the like may be formed as the ultrathin insulating film 26. In the formation of a silicon nitride film, dichlorosilane gas (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) may be used as a precursor for film formation, and dichlorosilane gas (SiH) is used as a precursor in the formation of a silicon oxynitride film. ₂ Cl _2), using a water _(H 2 O) and ammonia (NH _3).

As described above, after forming the high-k film 21, the SiO ₂ interface forming film 22 and the ultrathin insulating film 26 constituting the high dielectric gate insulating film, as in the case of the first embodiment, FIG. As shown, the temperature was raised from 100 ° C. to 400 ° C. in an atmosphere of F ₂ gas (atmosphere diluted to a concentration of about 1 vol.% To 10 vol.% As a mixing ratio with nitrogen) and held for about 1 to 10 minutes. F ₂ annealing 23 is performed through the process. By taking this process, no special annealing treatment is performed when fluorine is added. By this treatment, a state in which a large amount of fluorine is localized at the interface between the ultrathin insulating film 26 and the high-k film 21, in the high-k film 21, in the SiO ₂ interface forming film 22, and in the vicinity of the interface with the silicon substrate 11 This can be realized (see FIG. 17). These interface regions each contain a fluorine amount of about 3 × 10 ²¹ / cm ³ and 1 × 10 ²⁰ / cm ³ or more. Moreover, as is clear from comparison with FIG. 11, the high dielectric gate insulating film composed of the ultrathin insulating film 26, the high-k film 21 and the SiO ₂ interface forming film 22 is made more than in the case of the first embodiment. It becomes possible to introduce a large amount of fluorine by one digit or more.

Also in this case, as in the first embodiment, fluorine gas is contained instead of F ₂ gas as a gas atmosphere for introducing fluorine. For example, fluorocarbon-based gas (CF ₄ , C ₂ F ₆ , C ₃ F ₈ , _{C 4 F 8, C 4 F} 4, C 4 F 6, C 5 F 8) and trifluoromethane _(CHF 3), difluoromethane _{(CH 2 F} 2), sulfur hexafluoride _(SF 6), nitrogen trifluoride (NF ₃ ) and chlorine trifluoride (ClF ₃ ) produce similar effects. Alternatively, so-called remote plasma treatment of fluorine in which the NF ₃ gas and F ₂ gas are plasma-excited, ion species are removed from the active species of fluorine, and the surface of the high-k film 21 is irradiated with fluorine neutral radicals. May be applied. Also in this case, a large amount of fluorine can be introduced into the high-k film 21, the SiO ₂ interface forming film 22, and in the vicinity of the interface with the silicon substrate 11 at a low temperature of 400 ° C. or lower.

Further, fluorine may be doped in the film formation of the ultrathin insulating film 26. For example, an F ₂ gas (mixing ratio with nitrogen of about 0.1 vol.% To 5 vol.%), NF ₃ gas, or SF ₆ gas diluted with the precursor as a doping gas at the time of film formation by the ALD method, film formation chamber ( The fluorine-doped ultrathin insulating film 26 is formed. Also in this method, a high dielectric gate insulating film having a concentration distribution similar to that shown in FIG. 17 and containing a large amount of fluorine can be formed.

  Thereafter, as shown in FIG. 15, in the same manner as in the first embodiment, a gate electrode 24 made of a metal film such as TiN or W is formed, a source / drain contact 25 is further formed, and a wiring material process is performed. For example, an arbitrary circuit is configured using W or Al. Processes after the formation of the high-k film 21 such as formation of a metal gate electrode are preferably performed at a low temperature of 600 ° C. or lower. By using this low temperature process of 600 ° C. or less, a large amount of fluorine contained in the high dielectric gate insulating film remains inactive and stable, and a high quality high dielectric gate insulating film and interface can be obtained. . Here, when a process exceeding a temperature of 600 ° C. is used, the fluorine contained therein is activated and tends to damage the interface with the silicon substrate.

Hereinafter, effects in one example of the second embodiment will be described.
In the MISFET subjected to the fluorine treatment by F ₂ annealing described above, the gate region has a structure of W / TiN / SiN (film thickness 0.5 nm) / HfSiOx (film thickness 2.0 nm) / SiO ₂ (film thickness 0.5 nm). The order of the forming steps is as shown in FIGS. 1 to 6 and 12 to 15. Here, the fluorine distribution in the high dielectric gate insulating film is as shown in FIG. 17 by the F ₂ annealing. The activation annealing at the time of the dummy gate is about 1000 ° C. for about 3 seconds, and the final sintering is 400 ° C. In addition, the MISFET not subjected to the foot treatment does not perform only the F ₂ annealing process, and the other processes are the same.

  FIG. 16 shows the amount of charge traps in the high-dielectric gate insulating film of the n-channel MISFET with and without the fluorine treatment, and the interface state at the high-dielectric gate insulating film / silicon substrate interface. The result of evaluating is shown. This evaluation was performed by measuring the MISFET by a known charge pumping method. Here, FIG. 16A shows an evaluation result of the charge trap amount, and FIG. 16B shows an evaluation result of the interface state. In FIG. 16A and FIG. 16B, the horizontal axis represents the amount of charge injected into the high dielectric gate insulating film, and the vertical axis in FIG. 16A represents the charge trap by charge injection into the high dielectric gate insulating film. The number of charge carriers trapped in (corresponding to the increased amount of trapped charges) is shown per unit area. The vertical axis in FIG. 16B shows the amount of increase in interface state density due to charge injection stress (corresponding to BT stress) into the high dielectric gate insulating film.

  As shown in FIG. 16A, in the case of a MISFET that is not subjected to fluorine treatment of black circles, there are at least one digit more charge traps than in the case of a MISFET that is subjected to fluorine treatment of white circles. This is because the amount of charge traps in the film, particularly in the high-k film, is reduced by one digit or more by containing fluorine in the high dielectric gate insulating film of the MISFET as described in the second embodiment. Is shown.

  As shown in FIG. 16B, in the case of a MISFET that is not subjected to the fluorine treatment of black circles, the amount of interface state generated by the stress is at least one digit higher than that of the MISFET that is subjected to fluorine treatment of white circles. This indicates that, as described in the second embodiment, the coupling state of the high dielectric gate insulating film / silicon substrate interface is stabilized by containing fluorine in the high dielectric gate insulating film of the MISFET. ing. In addition, the interface state is lowered as described in FIG. 10 by the fluorine treatment, which is exactly the same as in the first embodiment. The effect of the fluorine treatment described with reference to FIG. 16 similarly occurs in the case of the p-channel MISFET.

FIG. 17 shows the amount of fluorine introduced into the high dielectric gate insulating film having a three-layer structure unique to the second embodiment. As can be seen from comparison with FIG. 11, in this case, the interface region between the silicon substrate 11 and the SiO ₂ interface forming film 22 and the high-k film 21, and the interface region between the high-k film 21 and the ultrathin insulating film 26. A large amount of fluorine is contained in a form that accumulates (pile-up). The amount of fluorine introduced in the vicinity of the silicon interface is 1 × 10 ²⁰ / cm ³ or more, and the amount of fluorine introduced in the vicinity of the high-k film 21, the ultrathin insulating film 26 and the interface is more than one digit more. It becomes about 3 × 10 ²¹ / cm ³ .

  As described above, since the fluorine is contained in the two interface regions sandwiching the high-k film 21, a large amount of fluorine is usually contained even in the high-k film 21 having a small fluorine solid solubility. Accordingly, it is possible to easily reduce the interface state on the surface of the silicon substrate and the charge traps in the film. Further, it is possible to form a high dielectric gate insulating film with high quality and high reliability.

  Further, in the case of the second embodiment, the high-k film 21 can be made to contain a sufficient amount of fluorine by the above mechanism, and the process margin for fluorine introduction becomes very high, and the amount of introduced fluorine is reduced. Adjustment / control is facilitated.

  The present invention is not limited to the embodiment described above, and various modifications can be made without departing from the spirit of the invention. For example, instead of the damascene gate electrode MISFET as described above, the present invention can be similarly applied to the formation of a MISFET having a flat gate electrode which is a normal structure. In this case, a diffusion layer such as a source / drain of the MISFET is formed after the high dielectric gate insulating film is formed. Therefore, in order to increase the heat resistance of the high-k film, a method of incorporating nitrogen into the film may be used in combination. Alternatively, in order to reduce the annealing temperature of the diffusion layer such as the source / drain diffusion layer, flash lamp annealing as described above or a solid phase growth technique at about 600 ° C. may be used in combination.

In addition, examples of the metal oxide film used for the high-k film include an alumina film (Al ₂ O ₃ film), a tantalum oxide film (Ta ₂ O ₅ film), a strontium titanate film (STO film), and a barium strontium titanate. A metal oxide film such as a film (BST film) or a ferroelectric film such as a lead zirconate titanate film (PZT film) may be used. As a metal silicate film used for the high-k film, a silicate film of a lanthanoid element such as La ₂ O ₃ or Y ₂ O ₃ or a silicate film of a refractory metal, or a composite silicate film of these silicate films is used. A membrane may be used. Moreover, as a metal aluminate film used for the high-k film, an aluminate film of a lanthanoid element such as La ₂ O ₃ or Y ₂ O ₃ or an aluminate film of a refractory metal, and further these aluminate films The composite membrane may be used. Alternatively, a composite film of a silicate film and an aluminate film can be used.

  Further, the ultrathin insulating film 26 may be formed by laminating a high dielectric constant film different from the high-k film 21. Even in this case, the mechanism of the second embodiment works in the same way, and fluorine piles up at the interface between these different types of high-k films, so that a large amount of fluorine can be contained in the high dielectric gate insulating film. become.

Cross-sectional view of semiconductor device during well implantation Cross-sectional view of semiconductor device when forming dummy gate Cross section of semiconductor device during dummy gate processing and ion implantation Cross-sectional view of semiconductor device after salicide formation Cross-sectional view of the semiconductor device during the dummy gate removal process after CMP Sectional view of the semiconductor device when forming a high-k film Sectional view of a semiconductor device when F ₂ annealing step in the first embodiment Sectional drawing of the semiconductor device at the time of contact formation with the metal electrode in Embodiment 1 Graph of an example of mobility improvement by fluorine gas treatment Graph of an example of Vth and interface state improvement by fluorine gas treatment Fluorine distribution near the interface between the silicon substrate and the gate insulating film in the first embodiment Sectional view of a semiconductor device when SiO ₂ interface forming layer formed in the second embodiment Sectional drawing of the semiconductor device at the time of ultra-thin insulating film formation in Embodiment 2 Sectional view of a semiconductor device when F ₂ annealing step in the second embodiment Sectional drawing of the semiconductor device at the time of metal electrode and contact formation in Embodiment 2 Graph of an example of gate insulation film improvement by fluorine gas treatment Fluorine distribution near the interface between the silicon substrate and the gate insulating film in the second embodiment

Explanation of symbols

11... Silicon substrate 111 a .. extension layer, halo layer 111... Source / drain diffusion layer 12... STI (shallow trench isolation)
13 ... Sacrificial oxide film 14 ... Well implantation 15 ... Dummy gate insulating film 16 ... Dummy gate electrode 18 ... Side wall 19 ... Silicide layer 20 ... Interlayer film 201 ... Interlayer film (nitride film)
202 .. Interlayer film (oxide film)
21 ... high-k film 22 ... SiO ₂ interface forming film 23 ... F ₂ annealing 24 ... metal gate electrode 25 ... contact electrode 26 ... ultra-thin insulating film

Claims (8)

  In a method for manufacturing a semiconductor device in which a high dielectric constant film and a gate electrode are formed on a silicon substrate, annealing is performed in a fluorine atmosphere after the formation of the high dielectric constant film, and the subsequent process temperature is 600 ° C. or lower. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing treatment includes a gas containing fluorine as a component. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of fluorine in the vicinity of the interface between the high dielectric constant film and the semiconductor substrate is 10 ²⁰ / cm ³ or more.   In a method of manufacturing a semiconductor device in which a high dielectric constant film and a gate electrode are formed on a silicon substrate, annealing is performed in a fluorine atmosphere after forming a thin film different from the high dielectric constant film stacked on the high dielectric constant film. A method of manufacturing a semiconductor device.   In a method of manufacturing a semiconductor device in which a high dielectric constant film and a gate electrode are formed on a silicon substrate, a thin film of fluorine dope different from the high dielectric constant film laminated on the high dielectric constant film is formed Device manufacturing method.   6. The method of manufacturing a semiconductor device according to claim 1, wherein an oxygen plasma treatment is performed after the high dielectric constant film is formed, and then an annealing treatment in a fluorine atmosphere or the thin film is formed. Manufacturing method.   6. The method of manufacturing a semiconductor device according to claim 4, wherein the thin film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.   6. The method of manufacturing a semiconductor device according to claim 4, wherein a process temperature after annealing in the fluorine atmosphere or after formation of the fluorine-doped thin film is 600 ° C. or less. .

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