JP2010212376A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a PMISFET (P Channel Metal Insulator Field Effect Transistor) in a metal gate electrode having a low threshold voltage. <P>SOLUTION: The method of manufacturing the PMISFET on a semiconductor substrate 10 includes the processes of: forming an insulating film 20 on the semiconductor substrate 10; forming an adsorption layer 110 on the insulating film 20 by exposing the semiconductor substrate 10 and insulating film 20 to gas containing a halogen compound; forming a gate electrode 40 containing metal on the adsorption layer 110 and subjecting the adsorption layer 110 and gate electrode 40 to reaction with each other to convert the adsorption layer 110 into a halogen-containing metal layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  High performance of CMISFETs (Complementary Metal Insulator Semiconductor Field Effect Transistor) has been realized by miniaturizing devices. However, the improvement in performance by reducing the physical size of the element has reached its limit, and the application of new materials is inevitable.

For example, in the gate insulating film, the conventional silicon oxide film and silicon oxynitride film have a problem of increasing leakage current due to an increase in the probability of electron-hole tunneling between the substrate and the electrode due to thinning. I have done it. For this reason, development of an insulating film having a high dielectric constant such as ZrO ₂ , HfO ₂ , HfZrO, and HfSiON has been underway.

In addition, in the gate electrode, the effective work function equivalent to the valence band edge and the conduction band edge of Si, such as the B / P · As-doped polycrystalline silicon film used so far, is reduced in order to reduce the capacitance due to the silicon depletion layer. A metal material having high heat resistance that can be adapted to a semiconductor element manufacturing process is not known. For example, materials having a low vacuum work function such as Al and Ti are generally highly reactive, and noble metals (platinum, etc.) having a high vacuum work function are not sufficiently high in melting point. Therefore, these materials are used as an electrode on the gate insulating film. If formed and subjected to a high-temperature heat treatment for activating the impurities in the channel diffusion layer, the insulating properties of the gate insulating film are likely to deteriorate. Further, a B / P · As-added polycrystalline silicon film or a metal film having an effective work function close to the valence band edge and the conduction band edge of Si is formed on a high dielectric constant insulating film such as HfO ₂ or HfSiON. It is known that when high-temperature heat treatment is performed, the effective work function changes to a value close to the Si mid gap. As described above, when the effective work function of the gate electrode deviates from the effective work function close to the valence band edge and the conduction band edge of Si, the threshold value of the FET (Field Effect Transistor) increases and the device performance deteriorates.

  Therefore, a compound material (for example, TiN or TaC) whose vacuum work function is located in the vicinity of the silicon midgap and has a high melting point is selected from NMISFET (N Channel Metal Insulator Transistor) and PMISFET (P Channel Metal Insulator Transistor Element). Attempts have been made to change the flat band voltage of the FET by using a common metal electrode and devising an insulating film and a channel. As an example, for NMISFET, introduction of rare earth / alkaline earth elements into the gate insulating film, and for PMISFET, introduction of aluminum into the gate insulating film can be mentioned. This is a technique based on the decrease in which the flat band voltage shifts to negative / positive when a rare earth / alkaline earth element / aluminum is present between the high dielectric constant insulating film and the silicon interface layer. Even when rare earth elements are introduced into the gate insulating film, the device performance does not deteriorate so much, and studies for practical use are underway. However, when aluminum is introduced into an insulating film, negative fixed charges are generated, and the carrier mobility in the channel is likely to be lowered.

  On the other hand, oxygen elements, nitrogen elements, and halogen elements have a higher electronegativity than metal elements, so that generally the work function increases when a metal is oxidized, nitrided, or halogenated. Therefore, a method has been proposed in which oxygen, nitrogen, or halogen is introduced only into the metal electrode of the PMISFET by ion implantation (see, for example, Patent Document 1). However, since the work function of the metal electrode is determined by the film composition in the vicinity of the interface with the gate insulating film, in order to greatly increase the work function, a large amount of oxygen / nitrogen / halogen is added to the vicinity of the gate insulating film interface. It is necessary to introduce into the metal film.

  However, ion implantation cannot introduce an element only into a specific region. In other words, when oxygen, nitrogen, or halogen is introduced into the metal film near the interface with the gate insulating film, some oxygen ions, nitrogen ions, or halogen ions are also introduced into the gate insulating film or the metal film that is away from the insulating film interface. As a result, there arises a problem that the insulating property of the gate insulating film is reduced by ion irradiation and the resistance of the metal electrode is increased.

JP 2003-273350 A

  As described above, in the conventional MISFET, when the metal film is used as the gate electrode, there is a problem that the work function of the metal electrode and the work function of Si deviate and the threshold voltage is likely to increase.

  Accordingly, an object of the present invention is to provide a method of manufacturing a metal gate electrode PMISFET having a low threshold voltage without using ion implantation.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a PMISFET on a semiconductor substrate, and a step of forming an insulating film on the semiconductor substrate;
Exposing the semiconductor substrate and the insulating film to a gas containing a halogen compound to form an adsorption layer on the insulating film; forming a gate electrode containing a metal on the adsorption layer; and And reacting the gate electrode to make the adsorption layer a halogen-containing metal layer.

  The method for manufacturing a semiconductor device according to the present invention is a method for producing a PMISFET and an NMISFET on a semiconductor substrate, the step of forming an insulating film on the semiconductor substrate, and the step of forming the semiconductor substrate and the insulating film with a halogen compound. Forming an adsorption layer on the insulating film by exposing to a gas comprising: forming a resist on the adsorption layer formed in the region for forming the PMISFET; and forming in the region for forming the NMISFET. A step of removing the adsorbed layer formed; a step of removing the resist formed in a region for forming the PMISFET; and a region on the adsorbing layer formed in the region for forming the PMISFET and a region for forming the NMISFET. A gate electrode is formed on the insulating film formed on the substrate, and the region for forming the PMISFET is formed. Said gate electrode is reacted with adhesive layer, characterized in that a step of the halogen-containing metal layer using the adsorption layer in the region for forming the PMISFET.

  According to the semiconductor device manufacturing method of the present invention, a metal gate electrode PMISFET having a low threshold voltage can be manufactured without using ion implantation in manufacturing the PMISFET.

1 is a cross-sectional view illustrating a schematic configuration diagram of a semiconductor device according to a first embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the schematic of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment. Sectional drawing which shows the schematic of the semiconductor device concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment. 1 is an evaluation diagram of a semiconductor device according to a first embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 to 5 show a first embodiment relating to a method of manufacturing a semiconductor device of the present invention.

  FIG. 1 shows a cross-sectional view of the PMISFET of the first embodiment.

  In the PMISFET according to this embodiment, a gate electrode 40 is formed on an insulating film 20 formed on a semiconductor substrate 10 via a halogen-containing metal layer 30, and the insulating film 20, the halogen-containing metal layer 30, and the gate electrode 40 are formed. The gate side wall 50 is formed on the side wall. Further, an N-type well region 60 is formed under the insulating film 20, and a P-type extension region 70 is formed so as to face the N-type well region 60, and outside the P-type extension region 70. The P-type diffusion region 80 is formed by extending.

  The P type extension region 70 has a lower impurity concentration than the P type diffusion region 80. The insulating film 20 is formed of a laminated structure of the interface layer 90 and the high dielectric constant insulating film 100.

  The semiconductor substrate 10 is generally single crystal Si, but may be composed of polycrystalline Si, amorphous Si, Ge, graphene, a compound semiconductor, SOI (Silicon On Insulator), an organic polymer, or the like.

The interface layer 90 is made of, for example, a silicon oxide film. Further, the high dielectric constant insulating film 100 is composed of, for example, a Hf insulating film such as HfSiON or HfO ₂ , a rare earth insulating film such as LaAlO, a laminated film of a Hf insulating film such as LaOx / HfSiON or HfSiON / LaOx and a rare earth insulating film, or the like. Is done. When a rare earth insulating film is used as the high dielectric constant insulating film 100, which is difficult to form a silicon oxide film even if formed on Si, the interface layer 90 may not be formed.

  Next, a method for manufacturing the PMISFET according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 2, an interfacial layer 90 mainly made of silicon oxide and a high dielectric constant insulating film 100 mainly made of HfSiON are formed on an N-type well region 60 formed on the semiconductor substrate 10. . Thereafter, for the purpose of modifying the insulating film 20, a high temperature heat treatment (PDA (Post Deposition Anneal)) is performed in an inert gas atmosphere to which an inert gas such as nitrogen or a small amount of oxygen is added.

Next, as shown in FIG. 3, an adsorption layer 110 made of a halogen compound is formed on the high dielectric constant insulating film 100. The adsorption layer 110 can be formed, for example, by exposing NH ₄ F solid powder composed of HF and NH ₃ to a sublimation gas generated by heating. At this time, an adsorption layer 110 of NH ₄ F is formed on the surface of the high dielectric constant insulating film 100. The film thickness of the adsorption layer 110 is 0.2 nm to 1.0 nm.

  Thereafter, as shown in FIG. 4, a metal M is deposited on the adsorption layer 110 to form the gate electrode 40. Examples of the gate electrode 40 include Mo, Ru, W, Ta, Nb, Ti, Hf, Zr, rare earth carbide, nitride, silicide, silicide nitride, and boride. Hereinafter, Mo will be described as an example.

  As shown in FIG. 5, when the gate electrode 40 is deposited, the halogen compound constituting the adsorption layer 110 and the metal constituting the gate electrode 40 react to form the halogen-containing metal layer 30. This reaction can also proceed even after heat treatment. The halogen-containing metal layer 30 has a thickness of 0.2 nm to 1.0 nm.

At this time, as the adsorption layer 110, a halogen-containing metal layer produced by the reaction between the halogen compound and the metal constituting the gate electrode 40 rather than the bonding force between the halogen of the halogen compound constituting the adsorption layer 110 and other atoms. 30 is used which has a stronger bonding force between the halogen and the metal. For example, NH ₄ F solid powder composed of HF and NH ₃ may be used for the halogen compound that forms the adsorption layer 110, and Mo may be used for the metal that constitutes the gate electrode 40. In this case, the halogen-containing metal layer 30 is MoF.

  This is because the Mo—F bond energy value is 6.15 eV, the Mo—N bond energy value is 0.77 eV, the F—H bond energy value is 3.17 eV, and the N—H bond bond. This is because the energy is 0.71 eV, and the Mo—F bond or the MoN bond has a higher bond energy than the F—H bond or the N—H bond.

In general, the binding energy E AB between the two elements A and _B is proportional to the difference between the electronegativity χ (A) and χ (B) of the element A and the element B, and the following equation 1 is used. Represented.

It becomes. Note that k = 1 when the binding energy is expressed in units of electron volts (eV).

  Since the electronegativity of F, H, Mo, and N is 3.98, 2.20, 2.16, and 3.04 in this order, the above binding energy value is derived from Equation 1.

  Thereafter, gate sidewalls 50 are formed on the sidewalls of the interface layer 90, the high dielectric constant insulating film 100, the halogen-containing metal layer 30, and the metal gate electrode 40, and B ions are implanted using the metal gate electrode 40 and the gate sidewall 50 as a mask. The active heat treatment is performed to form the P-type diffusion region 80, and the PMISFET shown in FIG. 1 is manufactured.

(Second Embodiment)
6 to 11 show a second embodiment relating to a method for manufacturing a semiconductor device of the present invention.

  FIG. 6 shows a cross-sectional view of the CMISFET according to this embodiment.

As shown in FIG. 6, the CMISFET according to the present embodiment is provided on a semiconductor substrate 10, and element isolation regions 120 are selectively formed in the surface layer portion of the semiconductor substrate 10. An insulating film such as SiO ₂ is embedded in the element isolation region 120, and a PMISFET formation region 130 and an NMISFET formation region 140 are formed across the element isolation region 120. Since the configurations of the PMISFET formation region 130 and the NMISFET formation region 140 are the same as those in the first embodiment, description thereof will be omitted.

  Next, a method for manufacturing the CMISFET according to this embodiment will be described.

  First, as shown in FIG. 7, an N-type well region 60 and a P-type well region 150 separated by an element isolation region 120 having an STI structure (Shallow Trench Isolation) are formed on a semiconductor substrate 10. Thereafter, an interface layer 90 is formed on the N-type well region 60 and the P-type well region 150, and a high dielectric constant insulating film 100 is further formed on the interface layer 90.

Next, as shown in FIG. 8, the high dielectric constant insulating film 100 is exposed to a sublimation gas of NH ₄ F solid powder, thereby forming the NH ₄ F adsorption layer 110 on the surface of the high dielectric constant insulating film 100. At this time, the thickness of the adsorption layer is 0.2 nm to 1.0 nm. Next, as shown in FIG. 9, the adsorption layer 110 on the N-type well region 60 is covered with a resist 160 and immersed in pure water. By performing the treatment, the adsorption layer 110 formed on the P-type well region 150 is removed.

  Further, as shown in FIG. 10, after removing the resist 160 on the N-type well region 60 side with an organic solvent, a TaSiN film is deposited on the adsorption layer 110 and the high dielectric constant insulating film 100 by sputtering to form a gate electrode. 40 is formed.

The bond energy of Ta—F bond is 6.15 eV, the bond energy of Si—F bond is 4.33 eV, the bond energy of Ta—N bond is 2.37 eV, the bond energy of Si—N bond is 1.3 eV, F− The bond energy of H-bond is 3.17 eV, the bond energy of NH bond is 0.71 eV, and the bond energy of Ta-F bond and Si-F bond is Ta-N bond, Si-N bond, F It is larger than the bond energy of the —H bond or N—H bond. Therefore, when the TaSiN film is deposited, the NH ₄ F adsorption layer 110 reacts with the TaSiN film, and only the gate electrode 40 on the high dielectric constant insulating film 100 on the N-type well region 60 side contains fluorine or nitrogen. The TaSiN film, that is, the halogen-containing metal layer 30 is formed. At this time, the film thickness of the halogen-containing metal layer is 0.2 nm to 1.0 nm. In addition, the value of the said binding energy can be calculated | required from Formula 1 demonstrated in 1st Embodiment, and the electronegativity of Si and Ta is 1.9 and 1.5 in order.

  Next, as shown in FIG. 11, the gate electrode 40 is processed by dry etching using a SiN hard mask. Next, As ions are implanted into the P-type well region 150 and B ions are implanted into the N-type well region 60, and the N-type extension region 170 and the P-type extension region 70 are formed by high-temperature spike annealing. Thereafter, the gate sidewall 50, the N-type diffusion region 180, the P-type diffusion region 80, and the interlayer insulating film 190 are formed and the surface is planarized by CMP (Chemical Mechanical Polishing) in a normal manufacturing process, and the CMISFET shown in FIG. Form.

(Third embodiment)
12 to 17 show a third embodiment relating to a method for manufacturing a semiconductor device of the present invention.

  FIG. 12 shows a cross-sectional view of the CMISFET according to this embodiment.

As shown in FIG. 12, the CMISFET according to this embodiment is provided on a semiconductor substrate 10, and element isolation regions 120 are selectively formed in the surface layer portion of the semiconductor substrate 10. An insulating film such as SiO ₂ is embedded in the element isolation region 120, and a PMISFET formation region 130 and an NMISFET formation region 140 are formed across the element isolation region 120. Since the configurations of the PMISFET formation region 130 and the NMISFET formation region 140 are the same as those in the second embodiment, description thereof is omitted.

  Next, a method for manufacturing the CMISFET according to this embodiment will be described.

  First, as shown in FIG. 13, an N-type well region 60 and a P-type well region 150 separated by an element isolation region 120 having an STI structure are formed on a semiconductor substrate 10. Thereafter, the interface layer 90 is formed on the N-type well region 60 and the P-type well region 150, and the high dielectric constant insulating film 100 is formed on the interface layer 90. Further, a lanthanum oxide layer 200 is deposited and formed on the high dielectric constant insulating film 100.

Next, as shown in FIG. 14, the surface of the lanthanum oxide layer 200 is exposed to a fluorocarbon gas ((-(C _x F _y )-) by exposing the lanthanum oxide layer 200 to a fluorocarbon gas generated by thermal decomposition of polytetrafluoroethylene. ) The _n layer, that is, the adsorption layer 110 is formed, and the film thickness of the adsorption layer 110 at this time is 0.2 nm to 1.0 nm.

  After that, as shown in FIG. 15, the adsorption layer 110 on the N-type well region 60 is covered with a resist 160, and the adsorption layer 110 on the P-type well region 150 side is exposed to ozone gas, whereby the P-type well region 150 side is exposed. The adsorption layer 110 is removed.

  Next, as shown in FIG. 16, after the resist 160 on the N-type well region 60 side is peeled off with an organic solvent, the TiN film 210 is laminated, and then the polycrystalline Si film 220 is laminated to produce the gate electrode 40. .

At this time, fluorocarbon constituting the adsorbing layer _{110 ((- (C x F} y) -) and _n, in the TiN film 210 constituting the gate electrode 40, Ta-F bond binding energy is greater than the C-F bond Therefore, fluorocarbon constituting the adsorbing layer _{110 ((- (C x F} y) -) n reacts with TiN film 210, TiF generates, fluorocarbon _{((- (C x F y} ) -) from _n F Is released, and the carbon remaining in the fluorocarbon ((-(C _x F _y )-) _n is also taken into the TiN film, as described above, the binding energy of the Ta-F bond is 6.15 eV, C The bond energy of the —F bond is 2.04 eV, and the electronegativity of C is 2.55, whereby a halogen-containing metal is present at the interface with the lanthanum oxide layer 200 on the N-type well region 60 side. TiNCF layer is formed is 30. The film thickness of the halogen-containing metal layer 30 at this time is 0.2Nm～1.0Nm.

  Thereafter, as shown in FIG. 17, the gate electrode 40 is processed by dry etching using a SiN hard mask. Next, As ions are implanted into the P-type well region 150 and B ions are implanted into the N-type well region 60, and the N-type extension region 170 and the P-type extension region 70 are formed by high-temperature spike annealing. Thereafter, in a normal manufacturing process, the gate sidewall 50, the N-type diffusion region 180, the P-type diffusion region 80, the PMIS polycrystalline silicon film 230, the NMIS polycrystalline silicon film 240, the interlayer insulating film 190 and the CMP (Chemical) are formed. Surface planarization is performed by Mechanical Polishing to form the CMISFET shown in FIG.

  The present invention is not limited to the first embodiment, the second embodiment, or the third embodiment described above, and appropriate design changes or combinations may be made without departing from the spirit of the invention. good.

  Hereinafter, based on Example 1-3, the effect of this invention is demonstrated concretely.

Example 1
First, a PMISFET was manufactured by the manufacturing method of the first embodiment. NH ₄ F was used for the adsorption layer 110, HfSiON was used for the high dielectric constant insulating film 100, and Mo was used for the gate electrode 40.

The CV characteristics of the sample produced by the manufacturing method of the first embodiment were evaluated. FIG. 18 shows the result. The broken line in FIG. 18 indicates a CV curve that has been subjected to NH ₄ adsorption treatment on the high dielectric constant insulating film 100, and the solid line represents a CV curve that has not undergone NH ₄ adsorption treatment. It has been clarified that the CV curve is shifted by about 0.3 V to the positive voltage side due to the NH ₄ F adsorption treatment on the surface of the HfSiON film. Furthermore, it was confirmed that the threshold voltage in the PMISFET manufactured by applying this treatment was lowered.

Further, when the effective work function of the gate electrode 40 is calculated from the dependence of the flat band voltage on the film thickness of the insulating film 20, it is about 4.7 V in the gate electrode 40 that is not subjected to NH ₄ adsorption treatment, whereas it is NH ₄ F adsorption. What performed electrode formation after a process was about 5V.

  In addition, when XPS and HR-RBS were used to evaluate the PMISFET manufactured by the manufacturing method of the first embodiment, nitrogen and fluorine were localized at the Mo / HfSiON interface, and the Mo spectrum was constrained. It was confirmed that a component with large energy was present.

This, MoF bond, MoN bond larger bonding energy than the F-H bonds and NH bonds in the sample was adsorbed NH ₄ F on HfSiON film, of _{2Mo + NH 4 F → MoF +} MoN + 2H 2 This is because the effective work function of the gate electrode 40 is increased when a reaction occurs and a layer containing F and N having a greater electronegativity than Mo is generated at the interface of the gate electrode 40.

(Example 2)
A CMISFET was manufactured by the manufacturing method of the second embodiment. NH ₄ F was used for the adsorption layer 110, HfSiON was used for the high dielectric constant insulating film 100, and TaSiN was used for the gate electrode 40.

  The effective work functions of the NMISFET and PMISFET gate electrode 40 of the fabricated sample were about 4.2 V and about 4.7 V, respectively, and the threshold voltage of both was about 0.2 V. The effective work function of the PMISFET electrode increased to about 4.7 V because of the formation of the halogen-containing metal layer 30 containing F having an electronegativity higher than that of Ta, Si, and N.

Example 3
A CMISFET was manufactured by the manufacturing method of the third embodiment. Fluorocarbon in the adsorption layer _{110 ((- (C x F} y) -) and _n, and HfO ₂ in the high dielectric constant insulating film 100, the gate electrode 40 with TiN.

  The effective work functions of the NMISFET and PMISFET gate electrodes 40 of the fabricated samples were about 4 V and about 5 V, respectively, and the threshold voltage of both was about 0 V.

  Usually, the vacuum work function of the TiN film is about 4.5V. However, the work function of the NMISFET in the manufacturing method of the third embodiment was about 4V. This is considered to be due to a dipole induced by La diffused to the vicinity of the interface layer 90. On the other hand, PMISET is caused by a TiN layer containing F having a higher electronegativity than Ti and N.

(Comparative Example 1)
A PMISFET was produced by the same production method as in Example 1 except that it was not treated with NH ₄ F. The effective work function of the gate electrode is about 4.7 V and 0. 0 compared with the case where NH ₄ F treatment is performed. The voltage dropped by about 3V.

(Comparative Example 2)
A CMISFET was produced by the same production method as in Example 2 except that it was not treated with NH ₄ F. The effective work function of the gate electrode of the PMISFET was about 4.2 V, which was about 0.5 V lower than that when the NH ₄ F treatment was performed.

(Comparative Example 3)
Fluorocarbon ((-(C _x F _y )-)) A CMISFET was produced by the same production method as in Example 3 except that _n was not treated.The effective work function of the gate electrode of the PMISFET was fluorocarbon (( _{- (C x F y) -} ) was reduced from about 4V and about 1V as compared to the case of applying the _n processing.

  By using the present invention, the effective work function of the PMISFET was increased and the threshold voltage was successfully reduced.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 20 ... Interface layer 30 ... Halogen containing metal layer 40 ... Gate electrode 50 ... Gate side wall 60 ... N-type well region 70 ... P-type extension region 80 ... P-type diffusion region 90 ... Interface layer 100 ... High dielectric constant insulation Layer 110 ... Adsorption layer 120 ... Element isolation region 130 ... PMISFET formation region 140 ... NMISFET formation region 150 ... P-type well region 160 ... Resist 170 ... N-type extension region 180 ... N-type diffusion region 190 ... Interlayer insulating film layer 200 ... Oxidation Lanthanum layer 210 ... TiN film 220 ... polycrystalline silicon film 230 ... PMIS polycrystalline silicon film 240 ... NMIS polycrystalline silicon film

Claims (6)

A method for producing a PMISFET on a semiconductor substrate,
Forming an insulating film on the semiconductor substrate;
Exposing the semiconductor substrate and the insulating film to a gas containing a halogen compound to form an adsorption layer on the insulating film;
Forming a gate electrode containing a metal on the adsorption layer, and reacting the adsorption layer with the gate electrode to make the adsorption layer a halogen-containing metal layer. Method. A method for producing a PMISFET and an NMISFET on a semiconductor substrate,
Forming an insulating film on the semiconductor substrate;
Exposing the semiconductor substrate and the insulating film to a gas comprising a halogen compound to form an adsorption layer on the insulating film;
Forming a resist on the adsorption layer formed in the region for forming the PMISFET;
Removing the adsorption layer formed in the region for forming the NMISFET;
Removing the resist formed in the region for forming the PMISFET;
Forming a gate electrode containing a metal on the adsorption layer formed in the region for forming the PMISFET and the insulating film formed in the region for forming the NMISFET; and the adsorption layer in the region for forming the PMISFET Reacting the gate electrode to make the adsorption layer in the region for forming the PMISFET a halogen-containing metal layer;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 1, wherein the halogen compound is NH ₄ F or fluorocarbon.   2. The gate electrode according to claim 1, wherein the gate electrode is any one of Mo, Ru, W, Ta, Nb, Ti, Hf, Zr, rare earth carbide, nitride, silicide, silicide nitride, and boride. Item 3. A method for manufacturing a semiconductor device according to Item 2.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the bonding force between the halogen and the metal forming the halogen-containing metal layer is stronger than the bonding force of the halogen compound.   The method for manufacturing a semiconductor device according to claim 1, wherein the halogen-containing metal layer has a thickness of 0.2 nm to 1.0 nm.

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