JP2681281B2 - Method for manufacturing MIS field effect semiconductor device - Google Patents

Description

The present invention relates to an improvement in a method for manufacturing a MIS field effect semiconductor device, wherein an impurity diffusion region is formed by solid phase diffusion similar to the case where SOG or the like is used as an impurity diffusion source. For the purpose of maintaining good in-plane uniformity of the sheet resistance in the diffusion region, the impurity diffusion source film and water resistance are formed after forming the impurity diffusion region formation opening in the insulating film on the semiconductor substrate. A step of continuously growing an insulating film sequentially, and then a step of applying a short-time thermal annealing method to solid-phase diffuse impurities from the impurity diffusion source film to the semiconductor substrate to form an impurity diffusion region. Configure as follows.

[Industrial applications]

The present invention is a MIS (metal insulator semiconductor)
The present invention relates to an improvement in a method for manufacturing a field effect semiconductor device.

In general, while higher integration of semiconductor devices is progressing further, individual semiconductor elements tend to be downsized because it is necessary to reduce the size of the entire semiconductor device. For example, in MIS field effect transistors. In this case, the value is reduced over the thickness of the gate insulating film, the thickness of the gate electrode, the depth of the source region and the drain region, and particularly when the size is reduced, If the source region and the drain region are not shallow, the sheet channel effect will occur. That is, when the source region and the drain region are deepened, they are in a state of being close to each other immediately below the gate electrode, and conduction is achieved by applying a voltage much lower than the designed value to the gate electrode. To avoid this, shallow source and drain regions are required.

[Conventional technology]

Conventionally, the following means have been adopted to shallowly form the source region and the drain region.

(1) Low acceleration energy ion implantation technology and RTA (rap
id thermal anneal) technology combined.

(2) Pre-amorphization technology based on silicon (Si) ion implantation, ion implantation technology with low acceleration energy, and
Combined use of RTA technology or FA (furnace anneal) technology.

(3) spin on glass (SO)
G) and other technologies that use impurity diffusion agents and RTA technology together (solid phase diffusion).

[Problems to be solved by the invention]

In each of the means exemplified above, the ion implantation method literally ionizes impurities and implants them into the substrate.
It has depth from the beginning.

In addition, an impurity diffusing agent such as SOG must be applied on the substrate using a photo resist coating device or the like, and then baked to make the impurities effective in diffusing into the substrate. However, when the baking is performed, SOG has a property of absorbing water very easily, and in such a case, it becomes difficult for impurities to diffuse into the substrate. Therefore, in the source region and the drain region formed by the solid phase diffusion, The in-plane uniformity of sheet resistance is significantly deteriorated.

By the way, in the so-called solid phase diffusion for diffusing impurities from SOG, since the depth does not exist as in the case of relying on the ion implantation method, it is effective for forming a shallow source region and a drain region. Therefore, if even the above-mentioned drawbacks regarding water absorption can be eliminated, it will be an effective means for highly integrating the MIS field effect semiconductor device.

The present invention makes it possible to maintain good in-plane uniformity of the sheet resistance in the impurity diffusion region while forming the impurity diffusion region by solid phase diffusion similar to the case of using SOG.

[Means for solving the problem]

FIG. 1 is a sectional side view of a main part of a semiconductor device at a process step for explaining the principle of the present invention.

In the figure, 21 is a silicon semiconductor substrate, 22 is an impurity diffusion source film for performing solid phase diffusion, and 23 is a water resistant insulating film.

In the present invention, the impurity diffusion source film 22 is grown by the chemical vapor deposition (CVD) method, and then the water resistant insulating film 23 is continuously grown thereon.

In the illustrated semiconductor device, a case where a B ₂ O ₃ film is used as the impurity diffusion source film 22 and a silicon dioxide (SiO ₂ ) film is used as the water resistant insulating film 23 will be described.

Here, assuming that there is no SiO ₂ film on the B ₂ O ₃ film, normally, after the B ₂ O ₃ film is formed, before performing a heat treatment for diffusing boron (B) into the silicon semiconductor substrate 21, Once exposed to the atmosphere. This is a means of heat treatment
It depends on adopting the RTA method.

Thus, even if exposed to the air even once, the B ₂ O ₃ film absorbs water and deteriorates, and even if the heat treatment by the RTA method is performed, B is not sufficiently diffused in the silicon semiconductor substrate 21 and impurity diffusion occurs. The sheet resistance of the area increases.

In such a case, as in the present invention, on the B ₂ O ₃ film,
If the SiO ₂ film is formed, no inconvenience will occur even if it is exposed to the atmosphere until it is heat-treated by the RTA method. In other words, if the heat treatment is performed by the RTA method, the silicon semiconductor substrate 21 must be exposed to the atmosphere, and according to the present invention, the RTA method that can achieve both the shallow junction formation and the low resistance of the impurity diffusion region. It became possible for the first time to apply to solid-phase diffusion. Incidentally, when adopting a method of using an ordinary electric furnace or the like instead of the RTA method for the heat treatment, the heat treatment cannot be carried out in a short time, so the heat treatment temperature must be lowered to make the junction shallow, Then, it becomes difficult to reduce the resistance of the impurity diffusion region.

Therefore, in the method of manufacturing the MIS field effect semiconductor device according to the present invention, the impurity diffusion region is formed in the insulating film (for example, the gate insulating film 6) on the semiconductor substrate (for example, the n-type silicon semiconductor substrate 1). A step of continuously growing an impurity diffusion source film (for example, B ₂ O ₃ film 9) and a water resistant insulating film (for example, SiO ₂ film 10) in that order after forming the opening for
Impurities are diffused from the impurity diffusion source film to the semiconductor substrate by applying a short-time thermal annealing method (eg, RTA method) to form impurity diffusion regions (eg, p ⁺ type source region 11 and p ⁺ type drain region 12). And the step of performing.

[Action]

By adopting the above means, even if the substrate is exposed to the atmosphere until the impurity diffusion source film is formed and the impurity diffusion region is formed by heat treatment according to the RTA method, the impurity diffusion source film absorbs water. As a result, the impurity diffusion function is hardly deteriorated, so that it is possible to form a shallow junction, reduce the resistance of the impurity diffusion region, and make the in-plane resistance uniform.

〔Example〕

2 to 10 are sectional side views of the essential part of the MIS field effect semiconductor device in the process steps for explaining one embodiment of the present invention, which will be described below with reference to these figures. .
Note that here, a p-channel transistor is targeted.

See FIG. 2 (1) The SiO ₂ film 2 is formed on the n-type silicon semiconductor substrate 1 by applying the thermal oxidation method. This SiO ₂ film 2 is interposed to relieve the stress between the silicon nitride (Si ₃ N ₄ ) film to be formed next and the n-type silicon semiconductor substrate 1.

(2) By applying the CVD method, for example, 1500
The Si ₃ N ₄ film 3 of about [Å] is formed.

The Si ₃ N ₄ film 3 acts as an oxidation resistant mask when performing selective thermal oxidation.

See FIG. 3 (3) By applying ordinary photolithography technique, the Si ₃ N ₄ film 3 is selectively etched to form an opening 3A corresponding to the field region.

(4) By applying the ion implantation method, the dose amount is, for example, about 2 × 10 ¹² [cm ⁻² ], and the acceleration energy is, for example,
Phosphorus (P) ions are implanted at about 80 [KeV] to form the n ⁺ type channel cut region 4.

See FIG. 4. (5) By applying the selective thermal oxidation method using the Si ₃ N ₄ film 3 as an oxidation resistant mask, the temperature is set to about 1000 ° C. and the time is set to, for example, in a wet oxidizing atmosphere. 120 minutes〕
Then, the field insulating film 5 made of SiO ₂ and having a thickness of about 6000 [Å] is formed.

See FIG. 5 (6) The Si ₃ N ₄ film 3 used as an oxidation resistant mask and the underlying SiO ₂ film 2 are removed to expose the active region of the silicon semiconductor substrate 1.

See Fig. 6 (7) By applying the thermal oxidation method, the thickness, for example, 20
A gate insulating film 6 made of SiO _{2 of} about 0 [Å] is formed.

(8) By applying the ion implantation method, boron (B) ions are implanted with a dose amount of about 4 × 10 ¹¹ [cm ⁻² ] and an acceleration energy of about 50 [KeV]. The p-type channel region 7 is formed.

See Fig. 7 (9) By applying the VCD method, for example, the thickness of 4000
By forming a polycrystalline silicon film of about [Å] and then applying an ion implantation method, the dose amount is set to 4 ×, for example.
By implanting phosphorus (P) ions into the polycrystalline silicon film with an acceleration energy of about 10 ¹⁵ [cm ⁻² ] and an acceleration energy of, for example, about 80 [KeV], and then applying a photolithography technique, The polycrystalline silicon film is patterned to form the gate electrode 8.

See FIG. 8 (10) By applying the dipping method using hydrofluoric acid as an etchant, the gate insulating film 6 on the portions where the source region is to be formed and the drain region is to be formed is removed to remove the silicon semiconductor substrate 1. Display selectively.

(11) Depending on the application of the CVD method, the thickness, for example 500
A B ₂ O ₃ film 9 which is an impurity diffusion source film of about [Å] and a SiO ₂ film 10 which is a water resistant insulating film having a thickness of, for example, about 1000 [Å] are continuously grown.

In order to continuously grow the B ₂ O ₃ film 9 and the SiO ₂ film 10 in the same reaction chamber of the CVD apparatus, the following reaction is caused.

2B ₂ H ₆ ＋ 3O ₂ → 2B ₂ O ₃ ＋ 6H ₂ SiH ₄ ＋ O ₂ → SiO ₂ ＋ 2H ₂ (12) By applying the RTA method, the temperature can be, for example, 100
Heat treatment is performed at 0 ° C for 10 seconds, and
Solid phase diffusion of ₂ O ₃ film 9 to B into the silicon semiconductor substrate 1
^{A +} type source region 11 and ap ⁺ type drain region 12 are formed.

The sheet resistance of the p ⁺ type source region 11 and the p ⁺ type drain region 12 thus formed is 100 [Ω / □] or less, and the junction depth is a shallow depth of about 0.13 [μm] or less. became.

When the RTA method is performed in this step, the following reaction occurs and B is diffused into the silicon semiconductor substrate 1.

2B ₂ O ₃ ＋ 3Si → 4B ＋ 3SiO ₂ See Fig. 9 (13) By applying the CVD method, the thickness is, for example, 5000
[Å] phosphosilicate glass (P)
SG) or boron-containing phosphosilicate glass (borophosphosilicat)
An interlayer insulating film 13 made of e glass (BPSG) or the like is formed.

(14) By applying a normal photolithography technique, the interlayer insulating film 13, the SiO ₂ film 10 and the B ₂ O ₃ film 9 are selectively etched to obtain a source electrode contact window, a drain electrode contact window, and others. An electrode contact window is formed.

(15) Heat treatment for glass reflow is performed to reduce irregularities on the surface of the interlayer insulating film 13 and smooth the surface.

See Fig. 10. (16) By applying the sputtering method, an aluminum (Al) film is formed, and then by applying a normal photolithography technique, the Al film is patterned to form the source electrode. 14 and the drain electrode 15 and other electrodes are formed.

In the MIS field effect semiconductor device manufactured as described above, if the SiO ₂ film 10 exists, the B ₂ O ₃ film 9 hardly absorbs water.

In general, B ₂ O ₃ is highly water-absorbing, but it is not possible to absorb water uniformly in the plane of the semiconductor wafer, and the upper part of the semiconductor wafer is particularly easy to absorb water when the orientation flat is lowered. , And, there is a big difference in the sheet resistance value between the part that absorbs water and the part that avoids it,
This is the main cause of deterioration of the in-plane uniformity of the sheet resistance. According to the above-mentioned embodiment, the in-plane uniformity of the sheet resistance is about 1 to 2%, and due to the conventional technique, it is about 5 to 7%. It should be noted that when B ₂ O ₃ absorbs water, it becomes cloudy, which can be judged at a glance.

In the above embodiment, the case where the B ₂ O ₃ film was used as the impurity diffusion source film was described, but the same applies to the P ₂ O ₅ film and the like, and the water resistant insulating film is formed of SiO 2. _A Si ₃ N ₄ film may be used instead of the _two films.

〔The invention's effect〕

In the method for manufacturing a MIS field effect semiconductor device according to the present invention, a water resistant insulating film such as SiO ₂ or Si ₃ N ₄ is formed on an impurity diffusion source film such as B ₂ O ₃ or P ₂ O ₅ which easily absorbs water. Is formed to prevent moisture in the atmosphere from reaching the impurity diffusion source film.

By adopting the above configuration, even if the substrate is exposed to the atmosphere until the impurity diffusion source film is formed and the impurity diffusion region is formed by the heat treatment according to the RTA method, the impurity diffusion source film absorbs water. As a result, the impurity diffusion function is hardly deteriorated, so that it is possible to form a shallow junction, reduce the resistance of the impurity diffusion region, and make the in-plane resistance uniform.

[Brief description of the drawings]

FIG. 1 is a main part of a process for explaining the principle of the present invention.
2 to 10 are sectional side views of a main part of the MIS field effect semiconductor device, and FIGS. 2 to 10 are sectional side views of the main part of the MIS field effect semiconductor device in a process main part for explaining one embodiment of the present invention. ing. In the figure, 21 is a silicon semiconductor substrate, 22 is an impurity diffusion source film for performing solid phase diffusion, and 23 is a water resistant insulating film.

Claims (1)

(57) [Claims] 1. A step of forming an impurity diffusion region forming opening in an insulating film on a semiconductor substrate and then successively growing an impurity diffusion source film and a water resistant insulating film, and then applying a short-time thermal annealing method. And a step of solid-phase diffusing impurities from the impurity diffusion source film to the semiconductor substrate to form an impurity diffusion region.