KR100250751B1 - Semiconductor device manufacture method - Google Patents

Semiconductor device manufacture method Download PDF

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KR100250751B1
KR100250751B1 KR1019970030103A KR19970030103A KR100250751B1 KR 100250751 B1 KR100250751 B1 KR 100250751B1 KR 1019970030103 A KR1019970030103 A KR 1019970030103A KR 19970030103 A KR19970030103 A KR 19970030103A KR 100250751 B1 KR100250751 B1 KR 100250751B1
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silicon substrate
defect layer
defects
ion implantation
semiconductor device
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Korean (ko)
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KR19990005885A (en
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유창우
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to remove dopants or defects from a silicon substrate and improve the reliability of a semiconductor device by forming the first and the second defect layers on the silicon substrate and performing a heat treatment process. CONSTITUTION: The first defect layer(3) is formed on a silicon substrate(1) formed with a field oxide layer(2) by performing the first ion implanting process. The second defect layer is formed between the first defect layer(3) and the silicon substrate(1) by performing the second ion implanting process. A heat treatment process for the silicon substrate(1) is performed to remove dopants and defects within the second defect layer and the silicon substrate(1).

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 소자의 제조방법에 관한 것으로, 특히 실리콘 기판의 소자 구동영역에 존재하는 결함 및 불순물을 제거할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a device, and more particularly to a method for manufacturing a semiconductor device capable of removing defects and impurities present in a device driving region of a silicon substrate.

일반적으로 반도체 소자의 집적도가 증가함에 따라 실리콘 기판 내부에 존재하는 불순물이나 결함을 제거하는 기술이 요구된다. 격자결함이나 불순물들이 소자 구동영역에 존재하게 되면 소수캐리어 수명(minority carrier lifetime)을 감소시키며 누설전류를 급격히 증가시키는 요인이 된다. 그리고 이러한 격자결함이나 불순물은 산화막의 막질과 CMOS 소자의 문턱전압 균일성을 저하시킨다. 현재 불순물 및 결함 제거기술은 고온, 저온, 고온의 3단계 열공정을 사용하는 방법과 웨이퍼 뒷부분에 기계적 손상을 가한 후 고온 열처리를 하거나, 고 에너지 이온주입에 의해 발생한 격자결함층을 만들어 사용하는 방법이 있다.In general, as the degree of integration of semiconductor devices increases, a technique for removing impurities or defects present in a silicon substrate is required. The presence of lattice defects or impurities in the device driving region reduces the minority carrier lifetime and rapidly increases the leakage current. Such lattice defects and impurities lower the film quality of the oxide film and the threshold voltage uniformity of the CMOS device. Current impurities and defect elimination techniques use high temperature, low temperature, high temperature three-step thermal process, and high temperature heat treatment after mechanical damage on the back of wafer, and lattice defect layer generated by high energy ion implantation. There is this.

MeV 이온주입 기술을 사용한 종래의 방법은 모재의 전기적 성질에 영향이 적은 Si, C 등의 도펀트를 이온주입하여 벌크(bulk)내 깊숙히 결함을 형성한 후 결함간의 상호작용을 유도하여 소자내의 결함을 제거하는 기술로 알려져 있다.The conventional method using MeV ion implantation technology implants dopants, such as Si and C, which have little influence on the electrical properties of the base metal to form defects deep in the bulk, and then induces interactions between the defects to induce defects in the device. Known as a removal technique.

상기 방법중 기계적 손상을 가하여 불순물 및 결함을 제거하는 방법은 고온의 온도 조건에서 장시간의 공정을 요구하며, 또한 공정이 복잡한 단점을 가지고 있고, 특히 불순물의 포획장소(trap site)로 작용하는 전위들이 열공정에 의해 제거된 후 불순물들이 다시 웨이퍼의 구동영역으로 되돌아 오는 문제점이 있다.The method of removing impurities and defects by applying mechanical damage among the above methods requires a long time process at a high temperature condition, and also has a disadvantage in that the process is complicated, and in particular, potentials serving as trap sites of impurities are There is a problem that impurities are returned to the driving region of the wafer after being removed by the thermal process.

따라서 본 발명은 필드산화막이 형성된 실리콘 기판의 트윈 웰 형성시 고에너지 및 고조사량 이온주입기로 웰 하단부의 깊숙한 부분 및 표면부근에 결함층을 형성한 후 열처리 공정으로 실리콘 기판내에 존재하는 불순물 및 결함을 소자구동영역의 표면으로 배출시킴과 동시에 벌크내에 형성된 결함층으로 포획하여 불순물 및 결함을 제거할 수 있는 반도체 소자의 제조방법을 제공하는 것을 그 목적으로 한다.Therefore, the present invention forms a defect layer in the deep part and the lower part of the bottom of the well using a high energy and high dose ion implanter when forming a twin well of a silicon substrate having a field oxide film, and then removes impurities and defects in the silicon substrate by a heat treatment process. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can be discharged to the surface of the device driving region and captured by a defect layer formed in the bulk to remove impurities and defects.

상술한 목적을 실현하기 위한 본 발명에 따른 반도체 소자의 제조방법은 제1이온주입 공정을 실시하여 제1결함층을 필드산화막이 형성된 실리콘 기판 내에 형성하는 단계와, 제2이온주입 공정을 실시하여 상기 제1결함층과 상기 실리콘 기판 표면 사이에 제2결함층을 형성하는 단계와, 상기 제2결함층과 상기 실리콘 기판 내의 불순물 및 결함을 제거하기 위해 상기 실리콘 기판에 열처리 공정을 실시하는 단계로 이루어지며, 상기 제1이온주입 공정은 붕소를 사용하여 1.5 내지 2.4MeV의 에너지 및 2×E14 내지 2×E15 이온/cm2도우즈 조건에서 실시하고, 상기 제2이온주입 공정은 아세닉을 사용하여 40 내지 100KeV의 에너지 및 1×E15 내지 1×E16 이온/cm2도우즈 조건에서 실시한다.A method of manufacturing a semiconductor device according to the present invention for realizing the above object comprises the steps of forming a first defect layer in a silicon substrate on which a field oxide film is formed by performing a first ion implantation process, and performing a second ion implantation process. Forming a second defect layer between the first defect layer and a surface of the silicon substrate, and performing a heat treatment process on the silicon substrate to remove impurities and defects in the second defect layer and the silicon substrate. The first ion implantation process is carried out under boron using energy of 1.5 to 2.4MeV and 2 × E14 to 2 × E15 ion / cm 2 dose conditions, and the second ion implantation process is performed using acenic. And energy at 40 to 100 KeV and 1 × E15 to 1 × E16 ion / cm 2 dose conditions.

도1a 내지 1d는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부회의 설명* Explanation of the sections of the main parts of the drawings

1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film

3 : 제1결함층 4 : 불순물 및 결함3: first defect layer 4: impurities and defects

5 : 제2결함층5: second defect layer

이하, 본 발명에 따른 반도체 소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도1a 내지 1d는 결함 및 불순물 제거방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of the device shown for explaining the method of removing defects and impurities.

도1a는 필드산화막(2)이 형성된 실리콘 기판(1)의 전체 상부면에 제1이온주입 공정을 실시한 상태를 도시한다. 상기 제1이온주입 공정은 붕소(B)를 사용하여 1.5 내지 2.4MeV의 에너지 및 2×E14 내지 2×E15 이온/cm2도우즈 조건에서 실시하며 이때, 실리콘 기판(1)의 표면으로부터 2 내지 2.8㎛의 지점에 최고농도치를 가지는 제1결함층(3)이 형성된다.FIG. 1A shows a state where the first ion implantation process is performed on the entire upper surface of the silicon substrate 1 on which the field oxide film 2 is formed. The first ion implantation process is performed using boron (B) at an energy of 1.5 to 2.4 MeV and 2 × E14 to 2 × E15 ions / cm 2 dose conditions, wherein 2 to 2 from the surface of the silicon substrate 1 are used. The first defect layer 3 having the highest concentration value is formed at a point of 2.8 mu m.

도1b는 실리콘 기판(1)의 전체 상부면에 제2이온주입 공정을 실시한 상태를 도시한다. 상기 제2이온주입 공정은 아세닉(As)을 사용하여 40 내지 100KeV의 에너지 및 1×E15 내지 1×E16 이온/cm2도우즈 조건에서 실시하며 이때, 주입된 이온은 모재내의 원자와 탄성 및 비탄성 충돌로 무수히 많은 결함을 유발하며, 이로인해 실리콘 기판(1)의 표면으로부터 0.3 내지 0.7㎛의 지점인 소자 구동영역에 제 2결함층(5)이 형성된다. 그리고, 상기 제 2결함층(5)에 형성된 농도결함들은 화학적으로 매우 불안정하여 주위의 다른 결함요소와 상호작용을하여 안정화되려고 한다.FIG. 1B shows a state in which the second ion implantation process is performed on the entire upper surface of the silicon substrate 1. The second ion implantation process is carried out under an energy of 40 to 100 KeV and 1 × E15 to 1 × E16 ion / cm 2 dose conditions using an asnic (As), wherein the implanted ions are made of atoms and elasticity and Inelastic collisions cause a myriad of defects, whereby a second defect layer 5 is formed in the element drive region at a point of 0.3 to 0.7 mu m from the surface of the silicon substrate 1. In addition, the concentration defects formed in the second defect layer 5 are chemically very unstable and try to stabilize by interacting with other defects around.

도1c는 상기 실리콘 기판(1)에 열처리 공정을 실시한 상태를 도시한다. 열처리 공정은 1000 내지 1200℃의 온도 조건에서 10 내지 30초간 실시되며, 상기 열처리 공정에 의해 실리콘 기판(1)의 내부에 존재하는 불순물 및 결함(4)과 아세닉(As) 이온주입에 의해 형성된 제 2결함층(5)은 결함농도가 높은 지역으로 게더링(Gettering)되는데, 특히 소자 구동영역에 존재하는 결함들은 실리콘 기판(1)의 표면으로 배출되는 동시에 벌크내의 제 1결함층으로 이동하게 된다.FIG. 1C shows a state in which the heat treatment process is performed on the silicon substrate 1. The heat treatment process is carried out for 10 to 30 seconds at a temperature condition of 1000 to 1200 ℃, by the impurity and defects (4) and the implantation (As) ion implantation existing inside the silicon substrate 1 by the heat treatment process The second defect layer 5 is gettered to a region having a high defect concentration, in particular, defects present in the device driving region are discharged to the surface of the silicon substrate 1 and move to the first defect layer in the bulk. .

도1d는 불순물 및 결함(4)에 완전히 제거된 상태를 도시한다.FIG. 1D shows a state where impurities and defects 4 are completely removed.

상술한 바와같이 본 발명에 의하면 필드산화막이 형성된 실리콘 기판의 트윈 웰 형성시 고에너지 및 고조사량 이온주입기로 웰 하단부의 깊숙한 부분 및 표면부근에 결함층을 형성한 후 실리콘 기판내에 존재하는 불순물 및 결함과 소자 구동영역에 형성된 결함을 소자구동영역의 표면으로 배출시킴과 동시에 벌크내에 형성된 결함층으로 포획하여 불순물 및 결함을 제거하도록 하므로써 시간을 절약할 수 있음은 물론, 웰 형성공정 이전에 열공정을 행하므로써 웰 형성 후 도펀트의 프로파일(Profile)에 영향을 주지않고, 또한 레티클을 사용하지 않으므로 공정의 단순화를 실현할 수 있는 효과가 있다.As described above, according to the present invention, impurities and defects existing in the silicon substrate after forming the defect layer in the deep portion and the surface near the bottom of the well by the high energy and high dose ion implanter are formed during the twin well formation of the silicon substrate on which the field oxide film is formed. And defects formed in the device driving region are discharged to the surface of the device driving region, and captured by the defect layer formed in the bulk to remove impurities and defects, and time can be saved. By doing so, the profile of the dopant after the well formation is not affected, and since the reticle is not used, the process can be simplified.

Claims (6)

제1이온주입 공정을 실시하여 제1결함층을 필드산화막이 형성된 실리콘 기판 내에 형성하는 단계와, 제2이온주입 공정을 실시하여 상기 제1결함층과 상기 실리콘 기판 표면 사이에 제2결함층을 형성하는 단계와, 상기 제2결함층과 상기 실리콘 기판 내의 불순물 및 결함을 제거하기 위해 상기 실리콘 기판에 열처리 공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.Performing a first ion implantation process to form a first defect layer in a silicon substrate having a field oxide film; and performing a second ion implantation process to form a second defect layer between the first defect layer and the silicon substrate surface. And forming a heat treatment process on the silicon substrate to remove impurities and defects in the second defect layer and the silicon substrate. 제1항에 있어서, 상기 제1이온주입 공정은 붕소를 사용하여 1.5 내지 2.4MeV의 에너지 및 2×E14 내지 2×E15 이온/cm2도우즈 조건에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first ion implantation process is performed using boron at an energy of 1.5 to 2.4 MeV and 2 × E14 to 2 × E15 ion / cm 2 dose conditions. . 제1항에 있어서, 상기 제1결함층은 실리콘 기판의 표면으로부터 2 내지 2.8㎛의 지점에 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first defect layer is formed at a point of 2 to 2.8 μm from the surface of the silicon substrate. 제1항에 있어서, 상기 제2이온주입 공정은 아세닉을 사용하여 40 내지 100KeV의 에너지 및 1×E15 내지 1×E16 이온/cm2도우즈 조건에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the second ion implantation process is performed under an energy of 40 to 100 KeV and 1 × E15 to 1 × E16 ion / cm 2 dose using an arsenic. . 제1항에 있어서, 상기 제2결함층은 실리콘 기판의 표면으로부터 0.3 내지 0.7㎛의 지점에 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the second defect layer is formed at a point of 0.3 to 0.7 μm from the surface of the silicon substrate. 제1항에 있어서, 상기 열처리 공정은 1000 내지 1200℃의 온도 조건에서 10 내지 30초간 실시되는 것을 특징으로 하는 반도체 소자의 제조방법The method of claim 1, wherein the heat treatment is performed at a temperature of 1000 to 1200 ° C. for 10 to 30 seconds.
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