KR100203129B1 - Process for removal remnant defects in source/drain junction - Google Patents

Abstract

The present invention relates to a method for removing source / drain junction residual defects during semiconductor device fabrication. The method provides a double buried layer using a high energy ion implantation to remove residual defects required when forming a junction in a shallow junction required in a highly integrated semiconductor device. The present invention relates to a method for removing residual defects by forming a buried layer and causing interaction between a lattice defect in a deep region and a residual defect in a shallow junction.

Description

Source / drain junction residual defect removal method

1A-1C illustrate the steps of making a shallow junction in the prior art.

2A to 2E are cross-sectional views showing steps of forming a source / drain of a semiconductor device according to an embodiment of the present invention.

3 is a graph showing the depth distribution and the concentration distribution of the first buried layer.

4 is a graph showing the depth and concentration distribution of the second buried layer.

5 is a distribution of point defects calculated by the net defect concept of the second buried layer.

* Explanation of symbols for main parts of the drawings

3: amorphous layer 10: wafer

11: metal impurities 12: oxygen

13: first buried layer 14: gate electrode

15; Gate oxide layer 16: source

17: drain 18: residual defect

19: second buried layer 21: secondary defect

22: secondary defect

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing source / drain junction residual defects during semiconductor device fabrication. In particular, the present invention relates to a double buried layer by using high energy ion implantation for residual defects remaining when forming a shallow junction required in a highly integrated semiconductor device. Layer to form a layer, which interacts with the lattice defects in the deep region and the residual defects in the thin joint to remove the residual defects.

As semiconductor devices become more integrated, shallower junctions are required. Residual defects occur when such shallow junctions are formed, which will be described with reference to the related art.

1A-1C illustrate the steps of making a shallow junction by conventional techniques.

FIG. 1A shows that the gate oxide film 2 is formed on the surface of the silicon substrate 10 and the gate electrode 1 is formed thereon. Then, Ge + ions are implanted to prevent channeling phenomenon. It is sectional drawing in which the amorphous layer 3 was formed in the surface.

For reference, when implanting B ⁺ ions, which are a dopant, in order to manufacture a shallow junction, which is required in a highly integrated semiconductor device, a channeling phenomenon in which a boron ion is implanted deeper than a desired depth occurs, making it difficult to form a shallow junction. . In order to prevent such a channeling phenomenon, the surface layer of the silicon substrate 10 is formed of the amorphous layer 3.

The 1b after turning the process as a cross-sectional view by implanting BF ₂ ⁺ ions form a lower side P type ion implantation region (4) of the amorphous layer 3, reference numeral 6 is the amorphous layer 3 and the P-type It is an interface with the ion implantation region 4.

FIG. 1C is a cross-sectional view of the P-type ion implantation region 4 in which the P-type ions are diffused deeper into the silicon substrate 10 to form the P-type source 8 and the drain 9. FIG. It is sectional drawing which shows that the residual defect 7 remains in the said P-type ion implantation area | region 4. As shown in FIG.

The residual defects are essentially generated after ion implantation and are not easy to remove. Residual defects that remain after heat treatment also serve as a source of leakage current in the junction, so residual defects must be removed.

The prior art removes residual defects to some extent by performing heat treatment after ion implantation. In addition, when the heat treatment temperature is high, more residual defects can be removed, but if the temperature is raised to a high temperature or the time is increased, there is a limit because there is a lot of serious adverse effects on the subsequent heat treatment process.

Therefore, the present invention does not rely only on heat treatment, but generates lattice defects in deep layers through high energy ion implantation, causing interaction with residual defects inside the device, or residual defects caused by ion beam heating generated during high energy ion implantation. The object is to provide a method for removing residual defects that can eliminate the

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a first buried layer by performing high energy ion implantation of C ⁺ ions on a silicon substrate;

Forming a purity layer on the surface of the silicon substrate by collecting metal impurities or oxygen using the first buried layer so that secondary defects are formed under the substrate;

Forming a gate oxide layer on the surface of the silicon substrate, forming a gate electrode thereon, implanting Ge ⁺ ions to form an amorphous layer, and implanting BF ₂ ⁺ ions to form a P ⁺ source and a drain; ,

The ion implantation of C ⁺ ions with high energy to form the second buried layer, and the residual defects remaining in the junction using the second buried layer are collected so that only the second defect exists in the second buried layer. It is characterized in that the drain junction residual defect is removed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating steps of forming a source / drain of a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2A is a cross-sectional view illustrating the formation of a first buried layer 13 by high energy ion implantation of C ⁺ ions into the silicon substrate 10.

In this case, the energy for injecting the C ⁺ ions is 2-3 MeV, and the first buried layer is formed to a depth of about 4μm on the silicon substrate 10.

In addition, the silicon substrate 10 includes a metal impurity (1) or oxygen (oxygen) (12), etc. The position of the interstitial by using the metal impurity (11) and oxygen (oxygen) 12 as a nucleus Si atoms deform each other to form a new atomic layer. The atomic layer has a bad effect on the increase of reverse current and leakage current of the P-type junction during semiconductor device fabrication.

FIG. 2B is a cross-sectional view illustrating the formation of a secondary defect 21 by collecting metal impurities 11, oxygen 12, etc. using the first buried layer 13. As a result, a pure layer is formed near the surface of the silicon substrate 10.

In order to collect the residual defects remaining in the junction in the first buried layer, heat treatment is performed at a temperature of 700-1000 ° C. for 30 minutes to 2 hours.

FIG. 2C illustrates that the gate oxide film 15 is formed on the surface of the silicon substrate 10 and the gate electrode 14 is formed thereon. After implanting Ge ⁺ ions to form an amorphous layer (not shown), BF2 is formed. ^{+ Is} implanted to form a P ⁺ -type source 16 and a drain 17. Residual defects 18 are generated when ion implantation is performed to form the amorphous layer and to form the source 16 and the drain 17.

The ion implantation energy of the Ge ⁺ ions is 40KeV or less, the implantation amount is 1 × 10E14-5 × 10E14 / cm 2, and the ion implantation energy of the BF 2+ ion is 20KeV or less, and the implantation amount is 1 × 10E15-5 × 10E15 / cm 2.

FIG. 2D is a cross-sectional view of the second buried layer 19 formed by ion implantation of C ⁺ ions with high energy, and the second buried layer 19 is formed to be shallower than the first buried layer 13.

The second buried layer is formed to a depth of about 3㎛ on the silicon substrate. The energy for injecting the C ⁺ ions into the second buried layer is 1-2 MeV, and the amount of implantation is 1 × 10 E15 -5 × 10 E16 / cm 2.

FIG. 2E is a cross-sectional view showing that only the secondary defects 22 exist in the second buried layer 19 by collecting residual defects 18 remaining in the junction using the second buried layer 19. Therefore, residual defects existing in the junction are eliminated.

In order to collect the residual defects remaining in the junction into the second buried layer, heat treatment is performed at a temperature of 600 to 1000 ° C. for 30 minutes to 2 hours.

3 is a graph showing the depth distribution and the concentration distribution of the first buried layer 13, and schematically shows the expected concentration values of oxygen, Au, Cu, etc. collected by the first buried layer 13.

4 is a graph showing the depth and concentration distribution of the second buried layer 19.

FIG. 5 is a distribution of point defects calculated by the net defect concept of the second buried layer 19, and shows that there are more vacancy at a depth of 10 mu m or less. On the other hand, since the residual defects remaining during the junction formation are interstitial, the residual defects are canceled by counteracting with a plurality of attackers generated in the second buried layer 19.

The prior art relies only on the heat treatment process for residual defect removal. Therefore, although sensitively reacted to the before-and-after heat treatment process, the present invention does not rely only on the heat treatment process but removes residual defects by using ion implanted defects and residual defects or interactions between defects and impurities, or removes defects by ion beam heating. Technology.

Therefore, it is possible to secure and maintain stable process conditions as a technology that is less sensitive to the before and after heat treatment process.

Claims (7)

In the method of manufacturing a semiconductor device, a step of forming a buried layer by the high energy ion implantation of C ⁺ ions on a silicon substrate, and collecting metal impurities or oxygen using the first buried layer 2 Forming a purity layer on the surface of the silicon substrate by forming a difference defect under the substrate; forming a gate oxide film on the surface of the silicon substrate; forming a gate electrode thereon ^; and implanting Ge ⁺ ions to form an amorphous layer, and using the step and a second berry deucheung to form a second berry deucheung to and the stage, and a C + ion implanting BF ₂ ⁺ ions to form a P ⁺ type source and drain ion implantation to the energy A method for removing source / drain junction residual defects comprising collecting residual defects remaining in the junction so that only secondary defects exist in the second buried layer. The method of claim 1 wherein the residual defects remaining in the junction are heat treated at a temperature of 700-1000 ° C. for 30 minutes to 2 hours to collect in the first buried layer. The method of claim 1, wherein the ion implantation energy of the Ge ⁺ ions is 40KeV or less and the implantation amount is 1x10E14-5x10E14 / cm2. The method of claim 1 wherein the BF ₂ ⁺ ion implantation energy of the ions is more than 20KeV, and dose is 1 × × 10E15-5 how the source / drain junction to remove residual defects, characterized in that 10E15 / ㎠. The method of claim 1, wherein the second buried layer is formed at a depth of about 3 μm on a silicon substrate. The method of claim 7, wherein the energy for injecting the C ⁺ ions into the second buried layer is 1-2MeV, and the amount of implantation is 1 × 10E15-5 × 10E16 / cm 2. The method of claim 1, wherein the residual defects remaining in the junction are heat treated at a temperature of 600-1000 ° C. for 30 minutes to 2 hours to collect the residual defects in the second buried layer.