KR970006261B1 - Fabrication method of diffusion region of semiconductor device - Google Patents
Fabrication method of diffusion region of semiconductor device Download PDFInfo
- Publication number
- KR970006261B1 KR970006261B1 KR1019940001937A KR19940001937A KR970006261B1 KR 970006261 B1 KR970006261 B1 KR 970006261B1 KR 1019940001937 A KR1019940001937 A KR 1019940001937A KR 19940001937 A KR19940001937 A KR 19940001937A KR 970006261 B1 KR970006261 B1 KR 970006261B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor substrate
- semiconductor device
- diffusion region
- depth
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000009792 diffusion process Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 20
- 229910052796 boron Inorganic materials 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 239000010703 silicon Substances 0.000 description 5
- -1 boron ions Chemical class 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 235000015241 bacon Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Abstract
Description
제1도는 종래기술의 일실시예에 따른 반도체소자의 소오스/드레인 접합의 단면도.1 is a cross-sectional view of a source / drain junction of a semiconductor device according to one embodiment of the prior art.
제2도는 종래기술의 다른 실시예에 따른 반도체소자의 소오스/드레인 접합의 단면도.2 is a cross-sectional view of a source / drain junction of a semiconductor device in accordance with another embodiment of the prior art.
제3도는 반도체 웨이퍼의 깊이에 따른 이온주입 직후 불순물 분포를 도시한 개략도.3 is a schematic diagram showing impurity distribution immediately after ion implantation according to the depth of a semiconductor wafer.
제4도는 본 발명에 따른 반도체소자의 소오스/드레인 접합의 단면도.4 is a cross-sectional view of a source / drain junction of a semiconductor device according to the present invention.
제5도는 이온주입에 따른 반도체 웨이퍼의 점결합 분포 상태를 도시한 단면도.5 is a cross-sectional view illustrating a point bonding distribution state of a semiconductor wafer caused by ion implantation.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21, 31 : 반도체기판 13, 23, 33 : 게이트 산화막11, 21, 31: semiconductor substrate 13, 23, 33: gate oxide film
15, 25, 35 : 게이트 전극 17, 27, 37 : 소오스/드레인 영역15, 25, 35: gate electrodes 17, 27, 37: source / drain regions
29 : 확장결함 39 : 손상영역29: expansion defect 39: damage area
본 발명은 반도체소자의 확산영역의 제조방법에 관한 것으로서, 특히 접합을 형성하기 위한 불순물이온주입 공정전에 반도체 기판상에 손상영역을 형성하여 열처리 공정시 불순물이온이 확산되어 접합이 깊어지는 것을 방지하고, 확장결함을 감소시켜 면저항이 작은 얕은 접합을 형성할 수 있는 반도체소자의 확산영역 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a diffusion region of a semiconductor device, and in particular, to form a damaged region on a semiconductor substrate before the impurity ion implantation process for forming a junction to prevent the diffusion of impurity ions during the heat treatment process to deepen the junction, A method for manufacturing a diffusion region of a semiconductor device capable of forming a shallow junction with a small sheet resistance by reducing expansion defects.
일반적으로 N형 반도체기판에 P형 불순물로 형성되는 PN 접합은 불순물로 붕소를 이온주입한 후, 열처리하여 활성화시킨다. 반도체소자가 고집적화되어 소자의 밀도 및 스위칭 스피드가 증가되고, 소비전력을 감소시키기 위하여 반도체소자의 디자인룰이 0.5μm 이하로 감소된다. 따라서 확산영역으로부터 측면 확산에 의한 숏채널 효과(short chart effect)를 방지하기 위하여 측면 확산의 정도에 비례하는 접합깊이를 얕게 형성하여야 한다.In general, a PN junction formed of an P-type impurity on an N-type semiconductor substrate is activated by implanting boron as an impurity followed by heat treatment. As the semiconductor device is highly integrated, the density and switching speed of the device are increased, and the design rule of the semiconductor device is reduced to 0.5 μm or less in order to reduce power consumption. Therefore, in order to prevent short chart effects due to side diffusion from the diffusion region, a junction depth proportional to the degree of side diffusion must be formed shallowly.
종래 기술에 따른 반도체소자의 확산영역 제조방법은 제1도에 도시되어 있는 바와 같이, N형 반도체기판(11)상에 게이트 산화막(13)과 게이트전극(15)을 순차적으로 형성한 후, 상기 반도체기판(11)상에 소정깊이, 예를 들어 디자인룰에 상응하는 어떤 Rp' (BF2) 깊이가 되도록 에너지를 조절하여 이온주입하고, 열처리하여 깊이 a의 확산영역인 P+형 소오스/드레인 접합(17)을 형성한다.In the method of manufacturing a diffusion region of a semiconductor device according to the prior art, as shown in FIG. 1, the gate oxide film 13 and the gate electrode 15 are sequentially formed on the N-type semiconductor substrate 11, and then the P + type source / drain, which is a diffusion region of depth a, is implanted with ion by adjusting energy to a predetermined depth, for example, a certain depth of Rp '(BF 2 ) corresponding to the design rule, on the semiconductor substrate 11. The junction 17 is formed.
그러나 상기와 같은 방법의 확산영역은 반도체소자가 고집적화되어 감에 따라 얕아지는 접합 깊이에 대응하기 어려운 문제점이 있다. 즉, 제3도의 선 ①로 표시되어 있는 바와 같이 이온주입된 상태에서 붕소가 채널링으로 인해 깊이 분포하고, 붕소 이온의 높은 확산계수에 의해 열처리시 접합깊이가 더욱 깊어져 숏채널효과가 발생하여 반도체소자의 신뢰성이 떨어지는 문제점이 있다.However, the diffusion region of the method described above has a problem that it is difficult to cope with a shallow junction depth as the semiconductor device is highly integrated. In other words, as indicated by the line ① in FIG. 3, boron is distributed deeply by channeling in the ion implanted state, and a deep channel depth occurs during heat treatment due to the high diffusion coefficient of boron ions, resulting in a short channel effect. There is a problem that the reliability of the device is poor.
상기와 같은 문제점을 해결하기 위하여 종래기술의 다른 실시예로서, 제2도에 도시되어 있는 바와 같이, N형 반도체기판(21)에 게이트 산화막(23)과 게이트 전극(25)을 순차적으로 형성한 후, 상기 반도체기판(21)에 실리콘(Si), 게르마늄(Ge) 또는 아세닉(As)등과 같은 비교적 원자량이 큰 불순물을 소정깊이, 예를 들어 Rp(X)(여기서 X는 Si, Ge 또는 As) 깊이로 충분한 양을 이온주입하여 상기 반도체기판(21)을 비정질화시킨다. 그 다음 상기 비정질화된 반도체기판(21)에 붕소와 같은 P형 불순물을 소정깊이, 예를 들어 Rp(BF2)로 이온주입하고, 열처리하여 깊이 b의 확산 영역인 P+형 소오스/드레인접합(27)을 형성한다.In order to solve the above problems, as shown in FIG. 2, a gate oxide film 23 and a gate electrode 25 are sequentially formed on an N-type semiconductor substrate 21. Afterwards, the semiconductor substrate 21 has a relatively deep atomic weight impurity such as silicon (Si), germanium (Ge), or asic (As). As) a sufficient amount of ion is implanted into the depth to make the semiconductor substrate 21 amorphous. Then, P-type impurities such as boron are ion-implanted into the amorphous semiconductor substrate 21 at a predetermined depth, for example, Rp (BF 2 ), and heat-treated to form a P + source / drain junction which is a diffusion region of depth b. (27) is formed.
여기서 상기 비정질화된 반도체기판(21)에서의 이온주입 직후 붕소이온의 깊이에 대한 분포는 제3도의 선 ②로 표시되어 있는 바와 같이, 비정질화되지 않은 상태의 반도체기판에 비해 초기에 얕은 깊이에 분포하여 열처리후 접합의 깊이 b는 a보다 작은 얕은 접합이 된다.Herein, the distribution of the boron ions depth after the ion implantation in the amorphous semiconductor substrate 21 is initially shallower than the semiconductor substrate in the non-amorphous state, as indicated by the line ② in FIG. After the heat treatment, the depth b of the joint becomes a shallow joint smaller than a.
그러나 상기와 같이, 반도체기판(21)에 비교적 큰 원자로 일차 이온주입하여 표면을 소정깊이까지 비정질화시킨 후, 불순물이온을 주입하여 소오스/드레인 접합(27)을 형성하는 종래의 방법은 비정질화를 위한 이온주입시 높은 주입량에 의해 실리콘 자기격자결함이 Rp(X)와 sRp(X)의 사이에 과잉상태로 존재하며, 여기서 X는 Si, Ge 또는 As이다. 그후, 상기 이온주입된 P형 불순물을 활성화시키기 위한 열처리 공정등과 같은 후속공정의 열에 의해 디스로케이션(dislocation) 등과 같은 확장결함(extended defects, 29)이 된다. 이러한 확장결함(29)들은 접합의 공핍층 근처에 존재할 수 있어 접합누설전류의 원인이 되어 반도체소자의 신뢰성이 떨어지는 문제점이 있다.However, as described above, the conventional method of primary ion implantation into the semiconductor substrate 21 to amorphous the surface to a predetermined depth, and then implant the impurity ions to form the source / drain junction 27, the amorphous Due to the high implantation rate, the silicon magnetic lattice defect is present in excess between Rp (X) and sRp (X), where X is Si, Ge, or As. Thereafter, by the heat of a subsequent process such as a heat treatment process for activating the ion implanted P-type impurity, extended defects such as dislocations 29 are obtained. These expansion defects 29 may be present near the depletion layer of the junction, causing a leakage current of the junction, thereby lowering the reliability of the semiconductor device.
또한 상기 확장결함(29)들을 제거하기 위하여 대략 1000℃ 정도의 온도에서 열처리하여, 이러한 고온열처리 공정시 붕소 원자가 다시 확산되어 접합의 깊이가 더욱 깊어지는 문제점이 있다.In addition, the heat treatment at a temperature of about 1000 ℃ to remove the expansion defects 29, there is a problem in that the boron atoms are diffused again during this high temperature heat treatment process to deepen the depth of the junction.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 반도체기판을 비정질화하기 위한 비교적 원자량이 큰 불순물의 이온주입량을 감소시켜 비정질화되지 않을 정도의 양을 이온주입함으로서, 확산결함을 감소시켜 반도체 소자의 신뢰성을 향상시키고, 얕은 접합을 용이하게 형성할 수 있는 반도체소자의 확산영역 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the ion implantation amount of a relatively large atomic weight impurity for amorphousization of a semiconductor substrate, thereby reducing the amount of non-amorphization, thereby causing diffusion defects. The present invention provides a method for manufacturing a diffusion region of a semiconductor device capable of reducing the reliability of the semiconductor device and improving the reliability of the semiconductor device.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 확산영역 제조방법의 특징은, 반도체기판상에 게이트 산화막과 게이트 전극을 형성하는 공정과, 상기 게이트전극 양측의 반도체기판이 비정질화되지 않을 정도 양의 불순물이온을 소정깊이로 이온주입하여 상기 반도체기판상에 손상영역을 형성하는 공정과, 상기 반도체기판의 손상영역내에 불순물이온주입을 실시한 후 활성화시켜 얕은 접합을 형성함에 있다.According to an aspect of the present invention, there is provided a method of manufacturing a diffusion region of a semiconductor device, the method including forming a gate oxide film and a gate electrode on a semiconductor substrate, and the semiconductor substrates on both sides of the gate electrode may not be amorphous. Forming a damaged region on the semiconductor substrate by implanting an amount of impurity ions to a predetermined depth, and implanting impurity ions into the damaged region of the semiconductor substrate to activate the shallow junction.
이하, 첨부도면을 참조하여 본 발명에 따른 반도체소자의 확산영역 제조방법을 상세히 설명한다.Hereinafter, a method for manufacturing a diffusion region of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제4도는 본 발명에 따른 반도체소자의 확산영역의 단면도이며, 제5도는 반도체기판내의 불순물이온 주입에 따른 점결함분포를 도시한 개략도로서, 서로 연관시켜 설명한다.FIG. 4 is a cross-sectional view of the diffusion region of the semiconductor device according to the present invention, and FIG. 5 is a schematic diagram showing the point defect distribution caused by the implantation of impurity ions in the semiconductor substrate.
먼저, 제4도에 도시되어 있는 바와 같이, N형 반도체기판(31)상에 게이트 산화막(33)과 게이트 전극(35)을 순차적으로 형성한 후, 상기 게이트 전극(35) 양측의 반도체기판(31)에 비교적 원자량이 큰 불순물, 예를 들어 실리콘(Si), 게르마늄(Ge) 또는 아세닉(As)등을 소정깊이, 예를 들어 Rp(X)(여기서 X는 Si, Ge 또는 As) 깊이로 이온주입하여 상기 반도체기판(31) 상에 손상영역(39)을 형성한다. 이때 상기 반도체기판(31)은 이온주입에 따른 손상은 입었으나, 비정질화되지는 않는 정도로 불순물량을 조절한다.First, as shown in FIG. 4, the gate oxide film 33 and the gate electrode 35 are sequentially formed on the N-type semiconductor substrate 31, and then the semiconductor substrates on both sides of the gate electrode 35 are formed. 31) a relatively large atomic weight impurity, such as silicon (Si), germanium (Ge), or asceic (As), to a predetermined depth, for example, Rp (X) where X is Si, Ge or As. Ion implantation to form a damaged region 39 on the semiconductor substrate 31. At this time, the semiconductor substrate 31 is damaged by ion implantation, but controls the amount of impurities to such an extent that it is not amorphous.
여기서 상기 손상영역(39) 형성을 위한 큰원자의 이온주입량이 너무 적으면, 붕소이온의 채널링을 방지하지 못하여 열처리 후 접합이 깊어지고, 너무 많으면, 열처리 공정시 다량의 확장결함이 생성된다.If the ion implantation amount of the large atoms for forming the damage region 39 is too small, the channeling of the boron ions may not be prevented, thereby deepening the bonding after the heat treatment, and if too much, a large amount of expansion defects are generated during the heat treatment process.
본 발명자의 실험결과에 따르면, 실리콘(Si), 게르마늄(Ge) 또는 아세닉(As) 등은 반도체기판(31)을 비정질화시키는 임계량이 각각 5×10E14㎝-2, 9×10E13㎝-2, 2×10E14㎝-2로서 이러한 임계크기의 50% 이하의 량으로 이온주입하면, 상기 반도체기판(31)은 비정질화되지 않으며, 본 발명자는 비정질화되는 량의 약 20% 정도를 이온주입하였다.According to the experimental results of the inventors, the critical amount of amorphous silicon (Si), germanium (Ge), or ashenic (As), etc., the semiconductor substrate 31 is 5 × 10E14cm -2 , 9 × 10E13cm -2 , When ion implantation is performed at an amount of 50% or less of this critical size as 2 × 10 E14 cm −2 , the semiconductor substrate 31 is not amorphous, and the present inventors ion implanted about 20% of the amount to be amorphous.
그 다음 상기 반도체기판(31)의 손상영역(39)상에 붕소와 같은 N형 불순물을 소정깊이, 예를 들어 디자인룰에 상응하는 어떤 Rp(BF2)로 이온주입하면, 제3도의 선 ③으로 표시되어 있는 바와 같은 주입직후(as-implanted) 불순물 분포를 갖는다. 즉, 손상되지 않은 표면에 붕소이온을 주입하는 경우(선 ①)보다는 표면에 가깝게 분포되고, 비정질화된 경우(선 ②)보다는 약간 깊게 위치한다. 그후, 상기 반도체기판(31)을 열처리하여 깊이 c의 P+형 소오스/드레인 접합(37)을 형성한다. 여기서 상기 c는 b보다 작다.Then, when ion implanted N-type impurities such as boron on the damage region 39 of the semiconductor substrate 31 to a predetermined depth, for example, any Rp (BF 2 ) corresponding to the design rule, the line ③ of FIG. It has an as-implanted impurity distribution as indicated by. That is, it is distributed closer to the surface than when boron ions are injected to the intact surface (line ①), and is located slightly deeper than when amorphous (line ②). Thereafter, the semiconductor substrate 31 is heat-treated to form a P + type source / drain junction 37 having a depth of c. Where c is less than b.
또한 상기 이온주입 깊이 Rp에 따른 상기 반도체기판(31) 내부의 수직점결함분포는 제5도에 도시되어 있는 바와 같이 반도체기판(31) 표면에서 0.8Rp까지는 베이컨시(vacancy) 결함이 많이 분포하며, 0.8Rp에서 2Rp까지는 실리콘원자의 자기격자(self interstitia) 결함이 많이 분포한다.In addition, as shown in FIG. 5, the vertical point defect distribution inside the semiconductor substrate 31 according to the ion implantation depth Rp has a lot of vacancy defects distributed from the surface of the semiconductor substrate 31 to 0.8 Rp. There are many self-interstitia defects of silicon atoms from 0.8Rp to 2Rp.
따라서 상기 손상영역(39)을 형성하기 위한 Rp(X)와 P형 불순물이 Rp(BF2)가 Rp(X)≥2Rp'(BF2) 즉 0.8Rp(X)≥2.5Rp(BF2)가 되도록 손상영역(39)을 형성하기 위한 이온주입 에너지를 조절하여 손상영역(39)에서의 베이컨시험결함과 붕소이온주입에 따른 실리콘 자기격자결함이 결합하여 실리콘 격자간 결함의 농도를 낮출 수 있다.Therefore, Rp (X) and P-type impurities for forming the damage region 39 have Rp (BF 2 ) of Rp (X) ≥2Rp '(BF 2 ), that is, 0.8Rp (X) ≥2.5Rp (BF 2 ). By adjusting the ion implantation energy to form the damage region 39 so that the bacon test defect and the silicon magnetic lattice defect due to boron ion implantation in the damage region 39 are combined, the concentration of defects between silicon lattice can be reduced. .
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 확산영역 제조방법은, 게이트 산화막과 게이트 전극이 형성되어 있는 반도체기판을 비정질화시키는 양에 대하여 50% 이하의 양으로 하고 그 주입에너지는 손상화 후 디자인룰에 상응하는 주입하려는 P형 불순물의 Rp' 보다 2.5배가 더 큰 Rp가 되도록 이온주입하여 반도체기판의 표면에 손상영역을 형성한 후, 붕소등과 같은 불순물 원자를 주입하여 확산영역을 형성하였으므로, 손상영역 형성 공정은 비정질화 공정보다 반도체기판의 가기격자결함 발생량이 현저하게 감소되어 자기격자결함을 따라 확산되는 붕소 불순물 원자의 기판으로의 침투 깊이가 작아져 얕은 접합을 용이하게 형성할 수 있으며, 열처리에 따라 점결함들이 결집된 확장 결함의 생성을 방지하여 접합누설전류가 감소되어 소자의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method for manufacturing a diffusion region of a semiconductor device according to the present invention, the amount of the amorphous oxide of the semiconductor substrate on which the gate oxide film and the gate electrode are formed is 50% or less, and the injection energy thereof is damaged after deterioration. Since the damaged region was formed on the surface of the semiconductor substrate by ion implantation so that Rp 'is 2.5 times larger than the Rp' of the P-type impurity to be implanted corresponding to the design rule, an impurity atom such as boron or the like was implanted to form a diffusion region. In the damage region formation process, the occurrence of the top lattice defect of the semiconductor substrate is significantly reduced than the amorphous process, and the penetration depth of the boron impurity atoms diffused along the magnetic lattice defect into the substrate can be easily formed, making it easier to form a shallow junction. In addition, the junction leakage current is reduced by preventing the formation of expansion defects in which point defects are collected by heat treatment. There is an advantage that can improve the reliability of the ruler.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940001937A KR970006261B1 (en) | 1994-02-03 | 1994-02-03 | Fabrication method of diffusion region of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940001937A KR970006261B1 (en) | 1994-02-03 | 1994-02-03 | Fabrication method of diffusion region of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950025922A KR950025922A (en) | 1995-09-18 |
| KR970006261B1 true KR970006261B1 (en) | 1997-04-25 |
Family
ID=19376685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940001937A KR970006261B1 (en) | 1994-02-03 | 1994-02-03 | Fabrication method of diffusion region of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970006261B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100773096B1 (en) * | 2006-01-20 | 2007-11-02 | 삼성전자주식회사 | Methods of forming semiconductor device having dopant doped region |
-
1994
- 1994-02-03 KR KR1019940001937A patent/KR970006261B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950025922A (en) | 1995-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4737471A (en) | Method for fabricating an insulated-gate FET having a narrow channel width | |
| KR100305623B1 (en) | Fabrication method of semiconductor device using ion implantation | |
| KR950000092B1 (en) | Manufacturing method of semiconductor device | |
| EP0543223B1 (en) | Method of forming shallow junctions in field effect transistors | |
| EP0852394B1 (en) | Method for making very shallow junctions in silicon devices | |
| KR0144020B1 (en) | Method of junction forming | |
| US4596068A (en) | Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface | |
| KR970006261B1 (en) | Fabrication method of diffusion region of semiconductor device | |
| US6136672A (en) | Process for device fabrication using a high-energy boron implant | |
| JPH01196818A (en) | Manufacture of semiconductor device | |
| JPS6142855B2 (en) | ||
| US6465332B1 (en) | Method of making MOS transistor with high doping gradient under the gate | |
| EP0762490A2 (en) | Method of manufacturing a LDD-MOSFET | |
| JPH07273121A (en) | Fabrication of semiconductor device | |
| US6767808B2 (en) | Method for fabricating semiconductor device | |
| JP2700320B2 (en) | Method for manufacturing semiconductor device | |
| EP0806794A2 (en) | Method of forming shallow doped regions in a semiconductor substrate, using preamorphization and ion implantation | |
| JPH01235276A (en) | Thin film semiconductor device | |
| KR0144493B1 (en) | Method for forming impurity junction area | |
| EP0720218A2 (en) | Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS | |
| KR100334965B1 (en) | Formation method of device of mos field effect transistor | |
| JPH1041240A (en) | Semiconductor device and its manufacture | |
| KR950013432B1 (en) | P-type source/drain making method | |
| JPH0611034B2 (en) | Method for manufacturing semiconductor device | |
| KR100214065B1 (en) | Method for forming mosfet junction |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100726 Year of fee payment: 14 |
|
| LAPS | Lapse due to unpaid annual fee |