KR0140325B1 - A method rorming shallow junction layer of silicon substrate - Google Patents
A method rorming shallow junction layer of silicon substrateInfo
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- KR0140325B1 KR0140325B1 KR1019940036815A KR19940036815A KR0140325B1 KR 0140325 B1 KR0140325 B1 KR 0140325B1 KR 1019940036815 A KR1019940036815 A KR 1019940036815A KR 19940036815 A KR19940036815 A KR 19940036815A KR 0140325 B1 KR0140325 B1 KR 0140325B1
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- Prior art keywords
- ions
- silicon substrate
- substrate
- forming
- ion implantation
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 22
- 239000010703 silicon Substances 0.000 title claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 26
- -1 germanium ions Chemical class 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 5
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 230000001133 acceleration Effects 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000000052 comparative effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000005465 channeling Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Weting (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 게르마늄이온을 다중이온 주입하여 비정질층을 일정깊이 이상 형성하므로서 저온에서 얕은 접합영역을 형성할 수 있는 실리콘 기판에의 얕은 접합층 저온형성방법을 제공하고자 하는데, 그 목적이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, and to provide a method for forming a shallow bonding layer at a low temperature on a silicon substrate capable of forming a shallow junction region at a low temperature by forming germanium ions by multi-ion implantation to form an amorphous layer more than a predetermined depth. There is a purpose.
본 발명은 반도체 소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계; 상기 이온주입 부위를 통해 불순물 이온을 주입하기 전에 그 불순물의 비정거리보다 2배 이상 깊은 곳까지 비정질층을 형성하기 위하여 임계 도우즈량 이상의 게르마늄 이온을 다중이온주입하는 단계; 상기 이온주입 부위를 통해 기판내에 불순물 이온을 주입하는 단계; 및 질소분위기하에서 700에서 1000℃의 저온에서 급속열처리하여 형성하는 단계를 포함하는 실리콘 기판에의 얕은 접합층 저온형성방법을 그 요지로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: etching away a portion into which ions are implanted after forming an SiO 2 oxide film on a silicon substrate; Before implanting impurity ions through the ion implantation site, multi-ion implantation of germanium ions having a critical dose or more in order to form an amorphous layer up to two times deeper than the specific distance of the impurity; Implanting impurity ions into the substrate through the ion implantation site; And a shallow bonding layer low temperature forming method on a silicon substrate comprising the step of rapid heat treatment at a low temperature of 700 to 1000 ° C. under a nitrogen atmosphere.
Description
제1도 (a) 내지 (d)는 본 발명에 의한 방법을 실시하기 위한 공정의 일예를 단계적으로 나타내는 모식도.1 (a) to (d) are schematic diagrams showing one example of a step for carrying out the method according to the present invention.
제2도는 본 발명에 의한 방법과 종래의 방법으로 붕소이온 주입시 급속열처리 온도에 따른 면저항의 변화를 나타내는 그래프2 is a graph showing the change of sheet resistance with rapid heat treatment temperature during boron ion implantation by the method according to the present invention and the conventional method.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:실리콘기판2:산화막1: silicon substrate 2: oxide film
3:이온주입부위4:게르마늄이온3: ion implantation site 4: germanium ion
5:비정질층6:붕소이온5: amorphous layer 6: boron ion
7:실리콘기판에 주입된 붕소이온8:얕은 접합 영역7: Boron ion implanted in the silicon substrate 8: Shallow junction area
본 발명은 반도체 소자의 제조방법에 관한 것으로써, 보다 상세히는 반도체 소자의 제조시 실리콘 기판에 저온에서 얕은 접합층을 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a shallow bonding layer at a low temperature on a silicon substrate during the manufacture of a semiconductor device.
최근 반도체 소자의 고집적화에 따라 기판의 깊이방향으로도 얕은 접합층의 형성이 요구되고 있으며, 이에따라 기판내에 고농도의 얕은 접합층을 형성하려는 시도가 계속되고 있다.Background Art Recently, with the high integration of semiconductor devices, the formation of a shallow bonding layer in the depth direction of the substrate is required, and accordingly, attempts to form a high concentration of shallow bonding layer in the substrate continue.
즉, 종래에는 기판내에 BF2와 같은 질량이 큰 화합물을 주입하여 이로부터 분해된 붕소(B)이온이 얕게 주입되는 현상을 이용하여 접합층을 형성하는 방법이 있었으나, 이 경우에는 분해된 불소(F)이온이 기판의 표면에 석출하는 문제점이 발생하게 된다.That is, conventionally, there has been a method of forming a bonding layer using a phenomenon in which a large amount of compound such as BF 2 is injected into a substrate and shallowly injected boron (B) ions are injected therefrom, but in this case, decomposed fluorine ( F) A problem that ions precipitate on the surface of the substrate occurs.
이와는 다른 방법으로서, 기판내에 주입되는 불순물 이온의 채널링을 방지하기 위하여 불순물의 주입전에 불활성 이온을 주입하여 비정질층을 형성하는 방법이 있으나, 이 경우에는 채널링을 방지하는 효과는 있으나 후 공정에서 이온주입시 유기되는 결함제거 및 불순물의 전기적 활성화를 위하여 고온에서 열처리를 해야하므로 이때 접합층이 깊어지는 문제점이 있다.As another method, in order to prevent the channeling of the impurity ions implanted in the substrate, there is a method of forming an amorphous layer by implanting inert ions before implanting the impurity. In this case, however, channeling is prevented, but ion implantation is performed in a later process. In order to remove the defects and to electrically activate the impurities, heat treatment must be performed at a high temperature, thereby deepening the bonding layer.
이에, 본 발명자들은 상기한 종래 방법들의 문제점을 해결하기 위하여 연구와 실험을 행하고 그 결과에 근거하여 본 발명을 제안하게 된 것으로서, 본 발명은 게르마늄 이온을 다중 이온주입하여 비정질층을 잎정깊이 이상 형성하므로써 저온에서 얕은 접합영역을 형성할 수 있는 실리콘 기판에의 얕은 접합층 저온형성방법을 제공하고자 하는데, 그 목적이 있다.Accordingly, the present inventors have conducted studies and experiments to solve the problems of the conventional methods described above, and the present invention has been proposed based on the results, and the present invention provides a multi-ion implantation of germanium ions to form an amorphous layer more than leaf depth. Accordingly, an object of the present invention is to provide a method for forming a shallow bonding layer at a low temperature on a silicon substrate capable of forming a shallow bonding region at a low temperature.
이하, 본 발명에 대하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated.
본 발명은 반도체 소자의 제조방법에 있어서, 실리콘 기판에 SiO2산화막을 형성한 후 이온이 주입되는 부위를 에칭제거하는 단계;According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: etching away a portion into which ions are implanted after forming an SiO 2 oxide film on a silicon substrate;
상기 이온주입 부위를 통해 불순물(dopant)이온을 주입하기 전에 그 불순물의 비정거리보다 2배 이상 깊은 곳까지 비정질층을 형성하기 위하여 임계 도우즈량 이상의 게르마늄 이온을 다중이온주입하는 단계;Multi-implanting germanium ions having a critical dose or more in order to form an amorphous layer up to two times deeper than an amorphous distance of the impurity before implanting dopant ions through the ion implantation site;
상기 이온주입 부위를 통해 기판내에 불순물 이온을 주입하는 단계; 및 질소분위기하에서 700℃ 이상에서 금속 열처리하여 접합층을 형성하는 단계를 포함하는 실리콘 기판에의 얕은 저합층 저온형성방법에 관한 것이다.Implanting impurity ions into the substrate through the ion implantation site; And forming a bonding layer by metal heat treatment at 700 ° C. or higher under a nitrogen atmosphere.
이하, 제1도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIG.
본 발명에 따라 실리콘 기판에 얕은 접합층을 저온에서 형성하기 위해서는, 우선, 제1도(a)에 나타난 바와 같이, 실리콘 기판(1)에 통상의 방법으로 SiO2산화막(2)을 형성한 후 불순물이 주입될 부위를 에칭제거하여 이온주입부위(3)을 형성한다.In order to form a shallow bonding layer on a silicon substrate at a low temperature according to the present invention, first, as shown in FIG. 1 (a), the SiO 2 oxide film 2 is formed on the silicon substrate 1 by a conventional method. The ion implantation site 3 is formed by etching away the site where impurities are to be implanted.
다음에, 제1도(b)에 나타난 바와 같이, 상기와 같이 에칭제거된 불순물 주입부위를 통해 불순물을 주입하기 전에 불순물의 비정거리보다 2배 이상 깊은 곳까지 비정질층(5)이 형성되도록 게르마늄이온(4)을 임계 도우즈량 이상을 다중이온주입하여야 한다.Next, as shown in FIG. 1 (b), germanium is formed such that the amorphous layer 5 is formed to a depth two times or more deeper than the impurity specific distance before the impurity is implanted through the impurity implanted portion removed as described above. The ions 4 should be multi-ion injected at least the critical dose amount.
상기 비정질층(5)이 비정거리보다 2배 이상 깊이를 가져야 하는 이유는 접합층이 깊어질 우려가 있기 때문이다.The reason why the amorphous layer 5 should be more than twice the depth of the amorphous distance is because the bonding layer may be deep.
상기와 같이 주입된 게르마늄이온에 의해 형성된 비정질층은 이후에 주입되는 불순물 이온의 채널링을 억제하고, 이후 불순물(dopant) 이온의 전기적 활성화도를 크게 하는데 기여하므로 저온 열처리 공정이 가능하게 한다. 이로서 접합층도 얇아진다.The amorphous layer formed by the implanted germanium ions as described above suppresses the channeling of impurity ions which are subsequently implanted, and subsequently contributes to increasing the electrical activation of the dopant ions, thereby enabling a low temperature heat treatment process. This also makes the bonding layer thinner.
본 발명의 발명에 사용될 수 있는 게르마늄이온은 주입에너지에서 비정질층을 형성할 수 있는 충분한 양으로 다중주입하는 것이 바람직하다.Germanium ions that can be used in the present invention are preferably multi-injected in an amount sufficient to form an amorphous layer in the implantation energy.
다음에, 제1도(c)에서와 같이, 이온주입부위(3)를 통해 기판내에 불순물이온(6)을 주입한다.Next, as shown in FIG. 1C, impurity ions 6 are implanted into the substrate through the ion implantation site 3.
제1도(c)에서 미설명부호 7은 주입된 붕소이온을 나타낸다.In FIG. 1C, reference numeral 7 denotes the implanted boron ion.
다음에, 질소분위기하에서 700℃ 이상의 온도범위에서 급속열처리하므로써, 제1도(d)에서와 같이 저온에서도 실리콘 기판에 얕은 접합영역(8)이 형성되게 된다.Next, by rapid heat treatment in a temperature range of 700 ° C. or higher under a nitrogen atmosphere, a shallow junction region 8 is formed in the silicon substrate even at a low temperature as shown in FIG.
상기 급속열처리온도가 700℃ 이하인 경우에는 면저항은 낮지만, 결함들이 충분히 회복되지 않아 전기적 특성의 신뢰도를 떨어뜨리게 되므로 전기소자로 사용하기 곤란하기 때문에 700℃ 이상이 되어야 하며, 1000℃ 이상에서는 종래의 방법과 거의 동일한 특성이 얻어지므로, 급속열처리온도는 700-1000℃로 선정하는 것이 바람직하다.When the rapid heat treatment temperature is 700 ℃ or less, the sheet resistance is low, but the defects are not fully recovered, so the reliability of the electrical properties is lowered, so it is difficult to use as an electric device, it should be 700 ℃ or more, and the conventional Since almost the same characteristics as the method are obtained, it is preferable to select the rapid heat treatment temperature at 700 to 1000 ° C.
본 발명의 방법에서 실리콘 기판에의 SiO2산화막형성, 불순물이 주입되는 부위의 에칭제거 및 불순물이나 게르마늄이온의 주입은 이 분야에서 공지된 어떠한 방법이라도 이용가능한 것이며, 본 발명의 열처리 역시 램프 가열법 등을 포함하여 이 분야에서 공지된 방법을 이용할 수 있다.In the method of the present invention, the formation of SiO 2 oxide film on the silicon substrate, the etching removal of the site where the impurity is implanted, and the implantation of the impurity or germanium ion can be used by any method known in the art. Methods known in the art can be used, including the like.
제1도에서는 n-형 실리콘 기판을 사용하고, 그리고 불순물로서는 붕소(B)를 사용하였으나, 본 발명은 이에 한정되는 것은 아니다.In FIG. 1, an n-type silicon substrate is used, and boron (B) is used as an impurity, but the present invention is not limited thereto.
이하, 실시예를 통하여 본 발명을 보다 구체적으로 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.
[실시예]EXAMPLE
[발명예]Invention
불순물 농도가 3×1015/cm2인 n형 실리콘 기판에 SiO2산화막을 형성한 후 불순물 주입부위를 에칭으로 제거하여 이온주입 부위를 형성하였다. 이후 상기 이온주입부위를 통해 가속전압 150keV와 50keV에서 게르마늄이온(Ge)을 이온 임프랜테이션(ion implantation)법을 사용하여 주입하였으며, 이때 도우즈량은 각각 2×1015, 1×1015/cm2였다. 이때 형성된 비정질층의 깊이는 불순물이 비정거리의 2.2배였다.After forming an SiO 2 oxide film on an n-type silicon substrate having an impurity concentration of 3 × 10 15 / cm 2 , an impurity implantation site was removed by etching to form an ion implantation site. Thereafter, germanium ions (Ge) were implanted through ion implantation at an acceleration voltage of 150 keV and 50 keV using ion implantation, and the doses were 2 × 10 15 and 1 × 10 15 / cm, respectively. 2 was. At this time, the formed amorphous layer had an impurity of 2.2 times the amorphous distance.
다음에, 붕소이온(b)을 가속전압 20keV의 에너지로 1×1015/cm2도우즈량으로 주입하였으며, 이 역시 이온 임프랜테이션법에 의하였다. 다음에, 붕소이온 주입이 끝난 실리콘 기판을 램프가열방식의 급속열처리장치로 질소분위기하에서 550에서 1100℃의 온도범위에서 10초간 열처리하여 기판내에 얕은 접합영역을 형성한 후, 열처리온도에 따른 면저항(sheet resistance)(ohms/sq.)을 측정하고 그 결과를 제2도에 나타내었다.Next, boron ions (b) were implanted in an amount of 1 × 10 15 / cm 2 dose with an energy of an acceleration voltage of 20 keV, which was also based on the ion implantation method. Next, the boron ion implanted silicon substrate was heat-treated in a temperature range of 550 to 1100 ° C. for 10 seconds under a nitrogen atmosphere using a rapid heating apparatus using a lamp heating method to form a shallow junction region in the substrate, and then the sheet resistance according to the heat treatment temperature ( sheet resistance (ohms / sq.) was measured and the results are shown in FIG.
[비교예 1]Comparative Example 1
게르마늄이온을 가속전압 50keV에서 도우즈량을 1×1015/cm2으로주입하여 기판표면에서부터 비정질층을 형성한 것을 제외하고는 상기 발명예와 동일한 방법으로 실리콘 기판에 얕은 접합층을 형성하고, 열처리온도에 따른 면저항을 측정하고, 그 결과를 제2도에 나타내었다. 이때, 형성된 비정질층 깊이는 불순물의 비정거리의 1배정도였다.A shallow bonding layer was formed on the silicon substrate in the same manner as in the example of the present invention except that an amorphous layer was formed from the surface of the substrate by injecting germanium ions at an acceleration voltage of 50 keV at a dose of 1 × 10 15 / cm 2 . The sheet resistance with temperature was measured, and the result is shown in FIG. At this time, the formed amorphous layer depth was about 1 times the amorphous distance of the impurity.
[비교예 2]Comparative Example 2
실리콘 이온을 상기 비교예 1과 같은 가속전압 및 도우즈량으로 주입하여 기판표면에서부터 비정질층을 형성한 것을 제외하고는 상기 발명예와 동일한 방법으로, 실리콘 기판에 얕은 접합층을 형성하고, 열처리온도에 따른 면저항을 측정하고, 그 결과를 제2도에 나타내었다.A shallow bonding layer was formed on the silicon substrate in the same manner as in the example of the invention, except that silicon ions were implanted at the same acceleration voltage and dose as in Comparative Example 1 to form an amorphous layer from the surface of the substrate. The sheet resistance was measured, and the results are shown in FIG.
이때, 형성된 비정질층의 깊이는 불순물의 비정거리의 1배정도였다.At this time, the depth of the formed amorphous layer was about 1 times the amorphous distance of the impurity.
제2도에 나타난 바와 같이, 본 발명에 부합되는 발명예는 본 발명을 벗어나는 비교예 1 및 2보다 열처리온도 550에서 900℃까지의 온도범위에서 면저항이 낮아서 낮은 온도에서 얕은 접합을 형성할 수 있도록 개선이 이루어짐을 알 수 있다. 또한 비교예 1 및 2의 경우에는 열처리온도가 높아짐에 따라서 저항이 감소하여 결함회복 및 전기적 활성화가 이루어지고 있으며 1000℃ 이후에 낮은 저항값을 가지나, 발명예의 경우에는 700℃ 이후에 거의 일정한 저항값을 가짐을 알 수 있다. 따라서, 이 온도범위에서 얕은 접합을 얻을 수 있다.As shown in FIG. 2, the inventive examples consistent with the present invention have a lower sheet resistance in the temperature range of 550 to 900 ° C. than the Comparative Examples 1 and 2, which deviate from the present invention, so that shallow junctions can be formed at low temperatures. It can be seen that an improvement is made. In addition, in Comparative Examples 1 and 2, as the heat treatment temperature is increased, the resistance decreases, defect recovery and electrical activation are performed, and the resistance value is lower after 1000 ° C. In the case of the invention example, the resistance value is almost constant after 700 ° C. It can be seen that it has. Therefore, a shallow junction can be obtained in this temperature range.
상기한 바와 같이, 본 발명은 기판내에 게르마늄이온을 임계농도 이상 다중주입하여 적정깊이에 비정질층을 형성한 후 불순물이온을 주입함으로써 얕은 접합형성을 위한 열처리온도를 저하시킬 수 있는 효과가 있는 것이다.As described above, the present invention has the effect of lowering the heat treatment temperature for the formation of shallow junctions by implanting impurity ions after forming an amorphous layer at an appropriate depth by injecting germanium ions into the substrate at a critical concentration or more.
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| KR1019940036815A KR0140325B1 (en) | 1994-12-26 | 1994-12-26 | A method rorming shallow junction layer of silicon substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100555488B1 (en) * | 1999-10-05 | 2006-03-03 | 삼성전자주식회사 | Method for controlling a Threshold Voltage by irradiating a E-beam in MOSFET |
| KR100943107B1 (en) * | 2001-11-28 | 2010-02-18 | 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. | Athermal annealing with rapid thermal annealing system and method |
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1994
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100555488B1 (en) * | 1999-10-05 | 2006-03-03 | 삼성전자주식회사 | Method for controlling a Threshold Voltage by irradiating a E-beam in MOSFET |
| KR100943107B1 (en) * | 2001-11-28 | 2010-02-18 | 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. | Athermal annealing with rapid thermal annealing system and method |
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