JP3992211B2 - CMOSFET manufacturing method - Google Patents

CMOSFET manufacturing method Download PDF

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JP3992211B2
JP3992211B2 JP36805898A JP36805898A JP3992211B2 JP 3992211 B2 JP3992211 B2 JP 3992211B2 JP 36805898 A JP36805898 A JP 36805898A JP 36805898 A JP36805898 A JP 36805898A JP 3992211 B2 JP3992211 B2 JP 3992211B2
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nitrogen
oxide layer
oxide
silicon substrate
gate
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オーノ ヨシ
マー ヤンジュン
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

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Description

【０００１】
【発明の属する技術分野】
本発明は、トランジスタ制御用の非常に信頼性のあるゲート酸化物プロセスを必要とするＭＯＳＦＥＴ素子の製造方法に関し、特に、ＣＭＯＳフローのｐＭＯＳ部分用にボロンドープされたゲートポリシリコンを必要とする深さがサブミクロンの素子に関する。
【０００２】
【従来の技術】
０．２５μｍのＣＭＯＳプロセスに組み込まれたゲート酸化物は厚さが３．５ｎｍから４．０ｎｍのオーダーと非常に薄い。このような酸化物は、非常に信頼性のある絶縁体でなくてはならない。これらの薄い酸化物層を成長させる技術は、Ｏ2（酸素）、Ｈ2Ｏ（水蒸気）、Ｎ2Ｏ（亜酸化窒素）およびＮＯ（一酸化窒素）のうちの１つ以上の気体の使用を含む。
【０００３】
公知の先行技術では、ｎＭＯＳ素子およびｐＭＯＳ素子の両方にＮ-ゲートを形成するように、ゲートポリシリコンにリンがドープされる。より短いチャネル長、すなわち、０．２５μｍ以下の場合には、短チャネルによる影響を最小化するために、ボロンを用いてｐ-をドープしたポリシリコンゲートをｐＭＯＳ素子用に形成する必要がある。
【０００４】
【発明が解決しようとする課題】
ゲート酸化物を通ってチャネル領域に入るボロンの拡散は、製造後の閾値電圧の変化および特に素子が古くなるに従って予測不可能な最終的な回路の性能に帰する。よって、ゲートポリシリコンにボロンが存在する素子において、ゲート酸化物がボロン原子の拡散のバリアとして作用する必要性が生じる。
【０００５】
ボロンの拡散を防ぐ公知の方法の１つは、酸化物とシリコン基板との界面に窒素を配置することである。また、ポリシリコン膜自体内に配置された窒素も、ボロンの拡散を防ぐことができる。しかし、この従来技術では、注入エネルギーの精密な制御が必要とされ、例えば、注入エネルギーが高ければ素子の信頼性の低下、注入エネルギーが低ければポリシリコン層の特性の低下を引き起こすという問題があった。
【０００６】
よって、本発明の目的は、ゲートポリシリコンの堆積前に、酸化物層の上表面に窒素を配置することである。
【０００７】
本発明の他の目的は、酸化物層へのボロンの拡散を効果的に遮断するように、酸化物層中への窒素注入を提供することである。
【０００８】
本発明の更なる目的は、本発明によって形成された素子の信頼性を保ち、かつ、ポリシリコン層の所望の特性を維持することである。
【０００９】
【課題を解決するための手段】
本発明は、ＣＭＯＳＦＥＴの製造方法であって、シリコン基板を準備する工程と、１．０ｎｍと１０ｎｍとの間の厚さを有する酸化物層を、準備された前記シリコン基板上に形成する工程と、プラズマイオン注入装置(plasmaimmersion ion implantation apparatus)における真空チャンバ内のチャック上に前記シリコン基板を設置して、該チャックを負電圧パルスによってバイアスした状態で、窒素含有酸化剤を用いて前記真空チャンバ内に形成されるプラズマ放電により、前記酸化物層へ、Ｎ ＋ イオンを、０．１ｋｅＶと２．０ｋｅＶとの間のエネルギーおよび１×１０13ｃｍ-2と１×１０16ｃｍ-2との間のドーズ量で、少なくとも２分間にわたって注入することによって、前記酸化物層の上表面に窒素を配置する工程と、次いで、前記酸化物層上にゲートポリシリコンを堆積する工程と、
堆積された前記ゲートポリシリコンにボロンをドーピングして、アニーリングおよびパターニングを実施する工程とを含む。これにより、上記目的が達成される。
【００１０】
好ましくは、前記窒素を配置する工程の後であって前記ゲートポリシリコンを堆積する工程の前に、前記酸化物層の上表面に窒素が配置された前記シリコン基板を６００℃と１０５０℃との間の温度で１０秒間から１時間にわたってアニーリングする工程を含む。
【００１６】
以下に作用を説明する。本発明によれば、ゲートポリシリコンの堆積前に、酸化物層中へプラズマイオン注入装置を用いて窒素注入することにより、酸化物層の上表面に窒素を配置できる。これにより、素子の信頼性およびポリシリコン層の特性を維持しながら、酸化物層へのボロンの拡散を効果的に遮断できる。
【００１７】
【発明の実施の形態】
ボロンのバリア特性を有する酸化物を成長させる１つの技術は、Ｎ2ＯまたはＮＯといった窒素含有酸化剤を酸化中に用いることである。得られた酸化物は、従来の酸素ガスによる酸化物または発熱性Ｈ2Ｏ酸化物（熱水による酸化物）よりも良質である。なぜなら、酸化物とシリコン基板との界面に窒素を配置するからである。この配置は、ボロンがトランジスタチャネル領域に移動するのを遮断することが公知である。
【００１８】
図１を参照すると、ｐ-Ｓｉ基板１２を形成するためにシリコンウェハ１０に対して、標準的な集積回路処理工程が実施されている。ｎ-ウェル１４がｐ-Ｓｉ基板１２中に従来の手段によって形成される。図２に示すように、１．０ｎｍから１０ｎｍの厚さを有する薄いゲート酸化物層１６がウェハ１０上に成長する。このゲート誘電体層の形成には、任意の標準的な材料および技術が使用され得る。
【００１９】
図３に示される工程において、ウェハ１０がプラズマイオン注入（plasma immersion ion implantation)（ＰＩＩＩ）処理チャンバ２２内に設置される。チャンバ２２では、純Ｎ2プラズマ１８が打たれ、軽いパルスがウェハに印加される。それによって、窒素が、酸化物層１６の上表面近傍で且つＳｉＯ2／Ｓｉ界面１７から離れたゲート誘電体に注入される。好適な実施形態では、Ｎ-およびＮ2 -イオンが酸化物層１６中に０．１ｋｅＶと２．０ｋｅＶとの間のエネルギー、且つ１×１０13ｃｍ-2と１×１０16ｃｍ-2との間のドーズ量で注入される。注入時間は１０秒と３分との間で変化する。
【００２０】
より高い温度でのアニールが、図４に示すように行われ、ゲート絶縁体内のより強い結合の形成を補助し、そして注入中に生じたダメージの一部を回復させる。それによって、所望の濃度の窒素を有する酸化物層（１６＋１８）を形成する。アニーリング工程は、６００℃と１０５０℃との間の温度で１０秒間から１時間の期間行われる。ゲートポリシリコンが堆積され、それに続き、集積回路の製造を完成するのに必要な標準的なドーピング、アニーリング、およびパターニング工程が行われる。
【００２１】
図５は、サンプル内の深さに対する窒素および酸素の原子濃度を測定する、二次イオン質量分析（ＳＩＭＳ）による分析結果の概要を示す。線Ｏは、酸化物層１６の深さに対する酸素原子百分率を示す。線Ｎは、酸化物層１６の深さに対する窒素原子百分率を示す。図５（ａ）に結果が示されている従来技術は、窒素が酸化物層の底部に存在することを可能にし、それによりボロンが酸化物自体に浸透し、そのため、絶縁体の信頼性を低下させる。酸化物と基板との界面にある窒素も、トランジスタ駆動電流および素子速度に悪影響を与える。ＮＭＯＳトランジスタの場合は、図６に示すように、ＳｉＯ2／Ｓｉ界面１７に存在する窒素が多くなると、キャリアの有効移動度μは小さくなる。
【００２２】
界面１７における酸素および窒素の濃度プロファイルが図５（ｂ）に示される。図５（ｂ）は、高速熱酸化または炉を用いて従来の方法で処理された素子において、二次イオン質量分析（ＳＩＭＳ）による窒素濃度プロファイルＮを深さの関数として示し、所望のＯプロファイルとの比較を示している。キャリア移動度に影響を与えることなく酸化物中へのボロンの拡散を阻止するために、酸化物とポリシリコンゲートとの界面に窒素を配置する方法が必要である。
【００２３】
従来の注入技術を用いた窒素のゲートポリシリコンへの注入が、ボロンの拡散特性を改善することを示されている。ポリシリコン膜自体内に配置された窒素もまた、ボロン拡散を阻止する。しかし、この技術の問題点は、注入エネルギーの制御が重要であることにある。高すぎるエネルギーで注入すれば、酸化物にダメージを与え得、よって、信頼性を低減させる。低すぎるエネルギーで注入すれば、窒素をポリシリコン中に残し、それによって抵抗性の増加、および欠陥効果（poly depietion effects)が起こり得る。
【００２４】
前述したように、本発明の目的は、ゲートポリシリコンの堆積前に窒素を酸化物の上表面に配置することである。このことは、ボロンが絶縁体層へ拡散するのを効果的に遮断し、信頼性を保ち、かつ、ポリシリコン層の所望の特性を維持する。
【００２５】
本発明の方法は、プラズマイオン注入（ＰＩＩＩ）によって、窒素を酸化物層１６の上表面に配置するという結果をもたらす。図７において、ＰＩＩＩ装置を概して参照符号２０により示す。ＰＩＩＩ装置２０は、真空チャンバ２２を含む。この場合にはＮ ２ ＋ およびＮ ＋ イオンである、注入を所望される材料を含むプラズマ放電２４が、真空チャンバ２２内に形成される。ウェハ２６がチャック２８上に設置される。チャック２８は、挿入グラフＧに示すように、非常に期間が短く３ｋＶ未満の振幅を有するが高い反復率の負電圧パルスによりバイアスされている。チャック２８上の負電圧パルスは、正に帯電した種（positivecharged species)をウェハ２６の基板へ引き寄せる。プラズマ放電の電力および電圧の振幅、パルス幅、ならびに反復率を調整することによって、イオン化された種は、下部界面、酸化物の大部分、または上表面のいずれかに向かってゲート酸化物層１６に埋め込まれる。本発明の方法の実施において、窒素イオンが酸化物層１６の上表面近くに埋め込まれるように、変数が調整される。
【００２６】
様々な技術および変化するパラメータを使用した実験を行うことにより、本発明の方法の実行可能性を調べ、その結果、図８の窒素プロファイルを得た。図８は、１２０Åのゲート酸化物中にＮ2プラズマ注入を行った結果得られた酸素および窒素のＳＩＭＳプロファイルを示す。従来技術による酸素濃度をトレース３０によって示す。注入パルスを与えずにＮ2プラズマに露出したのみでは、トレース３２に示すように、検出限界をはるかに超える少量の窒素を膜および界面中へ組み込む。トレース３４に示すように、注入パルスを２分間印加すると、１０ｎｍの厚さの酸化物層中の酸化物の大部分で、更に１桁多い窒素が得られた。この時、界面にも窒素が存在するが、その量はおよそ０．１原子％であり、図５より、その結果起こるキャリア移動度の劣化は５％にすぎないことがわかる。トレース３６に示すように、注入パルスを更に長期（５分間）にわたって印加した結果、１．０ｎｍから１０ｎｍの厚さの酸化物層の大部分および界面において更に多くの窒素が検出された。このことは、注入時間によるドーズ量の制御が可能であることを示している。注入条件の最適化は、本明細書中に示すパラメーターを用いて、ゲート酸化物の厚さ毎に行われる必要がある。
【００２７】
よって、トランジスタ制御用の信頼性のあるゲート酸化物プロセスを必要とするＭＯＳＦＥＴ素子の製造方法であって、特に、ＣＭＯＳフローのｐＭＯＳ部分用にボロンドープされたゲートポリシリコンを閾値電圧の制御および素子サイズに対する非感受性のために必要とする、深さがサブミクロンの素子の製造方法を開示した。本発明の好適な実施形態を開示したが、添付の請求の範囲に定義した本発明の範囲を逸脱することなく更なる改変および変更がなされ得ることが理解される。
【００２８】
【発明の効果】
本発明によると、ＭＯＳＦＥＴなどの半導体素子において、ゲートポリシリコンの堆積前に、酸化物層の表面上に窒素が配置されるため、酸化物層へのボロン拡散を効果的に遮断することができる。その結果、素子の信頼性を保ち、かつ、ポリシリコン層の所望の特性を維持することができる。
【図面の簡単な説明】
【図１】本発明によるＣＭＯＳゲート酸化物の形成の一段階を示す図である。
【図２】本発明によるＣＭＯＳゲート酸化物の形成の一段階を示す図である。
【図３】本発明によるＣＭＯＳゲート酸化物の形成の一段階を示す図である。
【図４】本発明によるＣＭＯＳゲート酸化物の形成の一段階を示す図である。
【図５】（ａ）は、従来の方法で処理された素子において、二次イオン質量分析（ＳＩＭＳ）の窒素濃度プロファイルを深さの関数として示す図であり、（ｂ）は、高速熱酸化または炉によって処理された素子における窒素濃度プロファイルと所望の酸素濃度プロファイルとの比較を示す図である。
【図６】ＳｉＯ2/Ｓｉ界面における窒素濃度がｎＭＯＳトランジスタのキャリア移動度に及ぼす影響を示す図である。
【図７】プラズマイオン注入装置の模式図である。
【図８】１２０Åのゲート酸化物に対してＮ2プラズマ注入をした結果生じた酸素および窒素のＳＩＭＳプロファイルを示す図である。
【符号の説明】
１０ シリコンウェハ
１２ ｐ-Ｓｉ基板
１４ ｎ-ウェル
１６ 薄ゲート酸化物層
１７ ＳｉＯ2／Ｓｉ界面
１８ 純Ｎ2プラズマ
２０ ＰＩＩＩ装置
２２ 真空チャンバ
２４ プラズマ放電
２６ ウェハ
２８ チャック[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a MOSFET device that requires a highly reliable gate oxide process for transistor control, and more particularly to a depth requiring boron doped gate polysilicon for the pMOS portion of a CMOS flow. Relates to sub-micron devices.
[0002]
[Prior art]
The gate oxide incorporated in a 0.25 μm CMOS process is very thin, on the order of 3.5 nm to 4.0 nm. Such oxides must be very reliable insulators. The technique for growing these thin oxide layers uses the gas of one or more of O 2 (oxygen), H 2 O (water vapor), N 2 O (nitrous oxide) and NO (nitrogen monoxide). including.
[0003]
In the known prior art, the gate polysilicon is doped with phosphorus so as to form N - gates in both nMOS and pMOS devices. For shorter channel lengths, ie 0.25 μm or less, it is necessary to form a p − doped polysilicon gate for the pMOS device using boron to minimize the effects of the short channel.
[0004]
[Problems to be solved by the invention]
Boron diffusion into the channel region through the gate oxide results in post-fabrication threshold voltage changes and, in particular, unpredictable final circuit performance as the device ages. Therefore, in a device in which boron is present in the gate polysilicon, the gate oxide needs to act as a barrier for boron atom diffusion.
[0005]
One known method of preventing boron diffusion is to place nitrogen at the interface between the oxide and the silicon substrate. Further, nitrogen arranged in the polysilicon film itself can also prevent boron diffusion. However, this conventional technique requires precise control of the implantation energy. For example, if the implantation energy is high, the reliability of the device is lowered, and if the implantation energy is low, the characteristics of the polysilicon layer are degraded. It was.
[0006]
Thus, it is an object of the present invention to place nitrogen on the upper surface of the oxide layer before the gate polysilicon is deposited.
[0007]
Another object of the present invention is to provide nitrogen implantation into the oxide layer so as to effectively block boron diffusion into the oxide layer.
[0008]
A further object of the present invention is to maintain the reliability of the devices formed by the present invention and to maintain the desired properties of the polysilicon layer.
[0009]
[Means for Solving the Problems]
The present invention is a method for manufacturing a CMOSFET, comprising: preparing a silicon substrate; forming an oxide layer having a thickness between 1.0 nm and 10 nm on the prepared silicon substrate; The silicon substrate is installed on a chuck in a vacuum chamber in a plasma ion implantation apparatus , and the chuck is biased by a negative voltage pulse, and a nitrogen-containing oxidant is used in the vacuum chamber. The plasma discharge formed on the oxide layer causes N + ions to enter the energy between 0.1 keV and 2.0 keV and between 1 × 10 13 cm −2 and 1 × 10 16 cm −2. Implanting nitrogen on the top surface of the oxide layer by implanting at a dose of at least 2 minutes, and then gating on the oxide layer. Depositing a polysilicon,
Doping the deposited gate polysilicon with boron to perform annealing and patterning. As a result, the above object is achieved.
[0010]
Preferably, after the step of disposing nitrogen and before the step of depositing the gate polysilicon, the silicon substrate having nitrogen disposed on the upper surface of the oxide layer is heated to 600 ° C. and 1050 ° C. Annealing for 10 seconds to 1 hour at a temperature between.
[0016]
The operation will be described below. According to the present invention, nitrogen can be disposed on the upper surface of the oxide layer by implanting nitrogen into the oxide layer using a plasma ion implantation apparatus before the gate polysilicon is deposited. Thereby, the diffusion of boron to the oxide layer can be effectively blocked while maintaining the reliability of the element and the characteristics of the polysilicon layer.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
One technique for growing oxides with boron barrier properties is to use a nitrogen-containing oxidant such as N 2 O or NO during oxidation. The obtained oxide is better in quality than the conventional oxide by oxygen gas or exothermic H 2 O oxide (oxide by hot water). This is because nitrogen is arranged at the interface between the oxide and the silicon substrate. This arrangement is known to block boron from moving to the transistor channel region.
[0018]
Referring to FIG. 1, standard integrated circuit processing steps are performed on a silicon wafer 10 to form a p - Si substrate 12. An n − well 14 is formed in the p − Si substrate 12 by conventional means. As shown in FIG. 2, a thin gate oxide layer 16 having a thickness of 1.0 nm to 10 nm is grown on the wafer 10. Any standard material and technique may be used to form this gate dielectric layer.
[0019]
In the process shown in FIG. 3, a wafer 10 is placed in a plasma immersion ion implantation (PIII) processing chamber 22. In chamber 22, pure N 2 plasma 18 is struck and a light pulse is applied to the wafer. Thereby, nitrogen is implanted into the gate dielectric near the top surface of the oxide layer 16 and away from the SiO 2 / Si interface 17. In a preferred embodiment, N − and N 2 − ions are present in the oxide layer 16 with an energy between 0.1 keV and 2.0 keV, and between 1 × 10 13 cm −2 and 1 × 10 16 cm −2 . Injected at a dose of between. The infusion time varies between 10 seconds and 3 minutes.
[0020]
A higher temperature anneal is performed as shown in FIG. 4 to assist in the formation of stronger bonds within the gate insulator and to recover some of the damage caused during implantation. Thereby, an oxide layer (16 + 18) having a desired concentration of nitrogen is formed. The annealing process is performed at a temperature between 600 ° C. and 1050 ° C. for a period of 10 seconds to 1 hour. Gate polysilicon is deposited, followed by standard doping, annealing, and patterning steps necessary to complete integrated circuit fabrication.
[0021]
FIG. 5 shows a summary of the results of analysis by secondary ion mass spectrometry (SIMS), which measures the atomic concentration of nitrogen and oxygen with respect to the depth in the sample. Line O represents the oxygen atom percentage with respect to the depth of the oxide layer 16. Line N represents the percentage of nitrogen atoms with respect to the depth of the oxide layer 16. The prior art, the results of which are shown in FIG. 5 (a), allows nitrogen to be present at the bottom of the oxide layer, so that boron penetrates the oxide itself, thus increasing the reliability of the insulator. Reduce. Nitrogen at the interface between the oxide and the substrate also adversely affects transistor drive current and device speed. In the case of an NMOS transistor, as shown in FIG. 6, the effective mobility μ of carriers decreases as the amount of nitrogen present at the SiO 2 / Si interface 17 increases.
[0022]
A concentration profile of oxygen and nitrogen at the interface 17 is shown in FIG. FIG. 5 (b) shows the nitrogen concentration profile N as a function of depth, as a function of depth, in a device processed in a conventional manner using fast thermal oxidation or a furnace, and the desired O profile. Comparison with is shown. In order to prevent boron diffusion into the oxide without affecting the carrier mobility, a method of placing nitrogen at the interface between the oxide and the polysilicon gate is required.
[0023]
Implantation of nitrogen into the gate polysilicon using conventional implantation techniques has been shown to improve boron diffusion properties. Nitrogen located within the polysilicon film itself also prevents boron diffusion. However, the problem with this technique is that it is important to control the implantation energy. Implanting with too high energy can damage the oxide, thus reducing reliability. Implanting with too low energy can leave nitrogen in the polysilicon, which can lead to increased resistance and poly depietion effects.
[0024]
As previously mentioned, an object of the present invention is to place nitrogen on the top surface of the oxide prior to gate polysilicon deposition. This effectively blocks boron from diffusing into the insulator layer, maintains reliability, and maintains the desired characteristics of the polysilicon layer.
[0025]
The method of the invention results in nitrogen being placed on the upper surface of the oxide layer 16 by plasma ion implantation (PIII). In FIG. 7, the PIII device is indicated generally by the reference numeral 20. The PIII device 20 includes a vacuum chamber 22. A plasma discharge 24 is formed in the vacuum chamber 22 containing the material desired to be implanted, in this case N 2 + and N + ions. Wafer 26 is placed on chuck 28. Chuck 28 is biased by a negative voltage pulse with a very short duration and an amplitude of less than 3 kV but with a high repetition rate, as shown in inset graph G. The negative voltage pulse on the chuck 28 attracts positively charged species to the substrate of the wafer 26. By adjusting the power and voltage amplitudes, pulse widths, and repetition rates of the plasma discharge, the ionized species are directed to either the lower interface, the majority of the oxide, or the upper surface of the gate oxide layer 16. Embedded in. In carrying out the method of the present invention, the variables are adjusted so that nitrogen ions are embedded near the top surface of the oxide layer 16.
[0026]
The feasibility of the method of the present invention was examined by conducting experiments using various techniques and changing parameters, resulting in the nitrogen profile of FIG. FIG. 8 shows the SIMS profiles of oxygen and nitrogen obtained as a result of N 2 plasma implantation into 120 Å gate oxide. The oxygen concentration according to the prior art is shown by trace 30. Only being exposed to N 2 plasma without applying an injection pulse will incorporate a small amount of nitrogen into the film and interface, far beyond the detection limit, as shown in trace 32. As shown in trace 34, when the injection pulse was applied for 2 minutes, one more digit of nitrogen was obtained for most of the oxide in the 10 nm thick oxide layer. At this time, nitrogen is also present at the interface, but the amount is about 0.1 atomic%, and FIG. 5 shows that the resulting deterioration in carrier mobility is only 5%. As shown in trace 36, the injection pulse was applied for a longer period (5 minutes) and as a result, more nitrogen was detected at most of the 1.0 nm to 10 nm thick oxide layer and at the interface. This indicates that the dose can be controlled by the implantation time. The optimization of the implantation conditions needs to be done for each gate oxide thickness using the parameters shown herein.
[0027]
Thus, a method of manufacturing a MOSFET device that requires a reliable gate oxide process for transistor control, particularly for boron-doped gate polysilicon for pMOS portion of CMOS flow, threshold voltage control and device size. Disclosed is a method for manufacturing submicron-depth devices required for insensitivity to. While preferred embodiments of the invention have been disclosed, it will be appreciated that further modifications and changes may be made without departing from the scope of the invention as defined in the appended claims.
[0028]
【The invention's effect】
According to the present invention, in a semiconductor device such as a MOSFET, nitrogen is disposed on the surface of the oxide layer before the gate polysilicon is deposited, so that boron diffusion into the oxide layer can be effectively blocked. . As a result, the reliability of the element can be maintained and the desired characteristics of the polysilicon layer can be maintained.
[Brief description of the drawings]
FIG. 1 shows a step in the formation of a CMOS gate oxide according to the present invention.
FIG. 2 shows a step in the formation of a CMOS gate oxide according to the present invention.
FIG. 3 shows a step in the formation of a CMOS gate oxide according to the present invention.
FIG. 4 shows a step in the formation of a CMOS gate oxide according to the present invention.
FIG. 5A is a diagram showing secondary ion mass spectrometry (SIMS) nitrogen concentration profile as a function of depth in a device processed by a conventional method, and FIG. 5B is a diagram showing rapid thermal oxidation. FIG. 6 is a diagram showing a comparison between a nitrogen concentration profile and a desired oxygen concentration profile in an element processed by a furnace.
FIG. 6 is a diagram showing the influence of the nitrogen concentration at the SiO 2 / Si interface on the carrier mobility of an nMOS transistor.
FIG. 7 is a schematic diagram of a plasma ion implantation apparatus.
FIG. 8 shows the SIMS profile of oxygen and nitrogen resulting from N 2 plasma implantation for 120 Å gate oxide.
[Explanation of symbols]
10 silicon wafer 12 p - Si substrate 14 n - well 16 thin gate oxide layer 17 SiO 2 / Si interface 18 Jun N 2 plasma 20 PIII device 22 vacuum chamber 24 plasma discharge 26 wafer 28 chuck

Claims (2)

ＣＭＯＳＦＥＴの製造方法であって、
シリコン基板を準備する工程と、
１．０ｎｍと１０ｎｍとの間の厚さを有する酸化物層を、準備された前記シリコン基板上に形成する工程と、
プラズマイオン注入装置(plasma immersion ion implantation apparatus)における真空チャンバ内のチャック上に前記シリコン基板を設置して、該チャックを負電圧パルスによってバイアスした状態で、窒素含有酸化剤を用いて前記真空チャンバ内に形成されるプラズマ放電により、前記酸化物層へ、Ｎ ＋ イオンを、０．１ｋｅＶと２．０ｋｅＶとの間のエネルギーおよび１×１０13ｃｍ-2と１×１０16ｃｍ-2との間のドーズ量で、少なくとも２分間にわたって注入することによって、前記酸化物層の上表面に窒素を配置する工程と、
次いで、前記酸化物層上にゲートポリシリコンを堆積する工程と、
堆積された前記ゲートポリシリコンにボロンをドーピングして、アニーリングおよびパターニングを実施する工程と、
を含むＣＭＯＳＦＥＴの製造方法。A method of manufacturing a CMOSFET comprising:
Preparing a silicon substrate;
Forming an oxide layer having a thickness between 1.0 nm and 10 nm on the prepared silicon substrate;
A silicon substrate is placed on a chuck in a vacuum chamber in a plasma immersion ion implantation apparatus , and the chuck is biased by a negative voltage pulse, and a nitrogen-containing oxidant is used in the vacuum chamber. The plasma discharge formed on the oxide layer causes N + ions to enter the energy between 0.1 keV and 2.0 keV and between 1 × 10 13 cm −2 and 1 × 10 16 cm −2. Placing nitrogen on the upper surface of the oxide layer by implanting at a dose of
Depositing gate polysilicon on the oxide layer;
Doping the deposited gate polysilicon with boron to perform annealing and patterning;
A method of manufacturing a CMOSFET comprising: 前記窒素を配置する工程の後であって前記ゲートポリシリコンを堆積する工程の前に、前記酸化物層の上表面に窒素が配置された前記シリコン基板を６００℃と１０５０℃との間の温度で１０秒間から１時間にわたってアニーリングする工程を含む、請求項１に記載のＣＭＯＳＦＥＴの製造方法。After the step of placing nitrogen and before the step of depositing the gate polysilicon, the silicon substrate with nitrogen placed on the upper surface of the oxide layer is heated to a temperature between 600 ° C. and 1050 ° C. The method of manufacturing a CMOSFET according to claim 1, further comprising: annealing for 10 seconds to 1 hour.
JP36805898A 1998-04-30 1998-12-24 CMOSFET manufacturing method Expired - Fee Related JP3992211B2 (en)

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