JPH0334649B2 - - Google Patents
Info
- Publication number
- JPH0334649B2 JPH0334649B2 JP15514881A JP15514881A JPH0334649B2 JP H0334649 B2 JPH0334649 B2 JP H0334649B2 JP 15514881 A JP15514881 A JP 15514881A JP 15514881 A JP15514881 A JP 15514881A JP H0334649 B2 JPH0334649 B2 JP H0334649B2
- Authority
- JP
- Japan
- Prior art keywords
- ion
- layer
- ion implantation
- implanted
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052796 boron Inorganic materials 0.000 claims description 46
- 238000005468 ion implantation Methods 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 43
- 239000010703 silicon Substances 0.000 claims description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 36
- 238000010438 heat treatment Methods 0.000 claims description 29
- 238000002513 implantation Methods 0.000 claims description 26
- -1 boron ions Chemical class 0.000 claims description 21
- 238000009826 distribution Methods 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000003213 activating effect Effects 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 31
- 230000004913 activation Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 9
- 239000013078 crystal Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 230000005465 channeling Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910001432 tin ion Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 150000001638 boron Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Description
本発明は、半導体装置の製造方法に係り、特に
シリコン基体のｎ型層に硼素イオンの注入により
ｐ型層を形成する工程の改良に関する。
シリコン集積回路等を中心とする半導体集積回
路は高密度化、高速化する目的で、回路を構成す
る種々の能動素子や受動素子の微細化が進められ
ている。シリコン集積回路の製造工程において
は、種々の熱処理工程（最高温度1000〜1100℃）
を必要とするが、熱処理温度をできるだけ下げて
基体中のドーピング不純物の移動乃至再分布を抑
制することは、上記微細化を図つてゆく場合に重
要である。近年、シリコン等の半導体基体中への
不純物精密ドーピング方法として、イオン注入法
が広範に用いられるようになつた。通常、イオン
注入工程を経た基体には熱処理工程が加えられ、
ドーピング不純物の電気的活性化とイオン注入時
基体結晶中に生じた結晶損傷の回復とが同時に図
られる。この場合の熱処理温度としては、通常、
900〜1000℃程度が必要とされる。このような温
度領域では、硼素(B)をはじめとするドーピング不
純物の殆どはシリコン基体中で拡散してしまい、
より一層の微細素子の製造は困難である。微細素
子実現のためには、イオン注入によつて基体中に
ドーピングされた不純物の再分布が殆ど生じない
様な、低温度領域での不純物の電気的活性化の方
法が強く望まれる。
シリコン基体中にイオン注入された硼素不純物
の低温活性化を図る場合に、従来、硼素イオン注
入とシリコン等のイオン注入とを重畳させる方法
が知られている。この方法によると、硼素イオン
注入層を形成後、シリコン等硼素原子よりも大き
い質量数を有する元素をシリコン基体中に高濃度
に注入して、非晶質シリコン層を硼素イオン注入
層を内包するが如く形成しておくことによつて、
600℃程度の熱処理で硼素イオン注入層を略100％
近く活性化できる。
ところが、シリコン集積回路等の製造工程にお
いては、硼素等の不純物をイオン注入した後、例
えば500℃以下の温度下で熱処理をしなければな
らない場合がしばしばある。斯様な場合に上記従
来の方法を其侭用いると熱処理温度が500℃以下
に制限されるために、硼素イオン注入後のシリコ
ンイオン注入によつて生ぜしめた非晶質層が充分
に再結晶化せず、特にp+−ｎ接合を形成した際
には、接合部より深部の領域に存在するシリコン
イオン注入による残留欠陥のために接合リークが
生じ易く、良好な素子を形成することができなか
つた。
本発明は上記従来法の欠点を解消した、シリコ
ン基体中の硼素イオン注入層の低温活性化方法を
用いた半導体装置の製造方法を提供するものであ
る。
本発明は、シリコン基体のｎ型層内に硼素をイ
オン注入して得られる第１のイオン注入層と硼素
イオンよりも質量数が大きく且つシリコン基体の
導電型に影響を与えないイオンを注入して得られ
る第２のイオン注入層とを、その濃度分布の極大
値の位置を略合致させ、且つその極大値より深い
領域での第２のイオン注入層の濃度分布の広がり
が第１のイオン注入層の濃度分布の広がりを越え
ない様に重畳せしめて形成した後、熱処理を行う
ことにより第１のイオン注入層、即ち硼素イオン
注入層の電気的活性化を図ることを特徴としてい
る。第２のイオン注入層の注入量は、イオン種に
より異なるが少くとも５×1014個／cm2以上とする
ことが好ましい。本発明によれば、第１、第２の
イオン注入層の濃度分布を規定することによつ
て、その後の熱処理を例えば500℃以下の低い温
度で行つたとしても、第２のイオン注入層による
非晶質層や残留欠陥の影響が少なく、リーク等の
少ないpn接合を形成することができる。
以下、本発明の具体的実施例について説明す
る。
実施例 １
比抵抗〜20Ω・cmのｎ型Si基体に注入エネルギ
ー20keVで例えば１×1015個／cm2の注入量にて硼
素イオン（B+：質量数11）を注入する。続いて
この硼素イオン注入層に重畳せしめて、注入エネ
ルギー45keVで１×1015個／cm2の注入量にてシリ
コンイオン（Si+：質量数28）を注入する。この
時の注入イオンのSi基体中における濃度分布は略
第１図に示す如くなる。尚、上記イオン注入は云
わゆるチヤネリング現象を生ぜしめない状況下に
て行なつた。上記工程度、Si基体を窒素（N2）
雰囲気中で熱処理した。熱処理温度は480℃、熱
処理時間は30分であつた。該熱処理後の上記イオ
ン注入層の層抵抗値は0.24kΩ／□であつた。又、
この硼素イオン注入層（p+層）と基体（ｎ型）
との間の逆方向リーク電流特性（接合リーク）を
調べた結果、逆方向印加電圧8Vに対し〜３×
10-9A／cm2程度のリーク電流密度であつた。
比較のために1000℃、10分間の熱処理を施した
場合には、得られた層抵抗値は0.13kΩ／□であ
り、また、イオン注入層と基体との間のリーク電
流密度は〜10-10A／cm2（逆方向電圧8V印加時）
であつた。
1000℃の熱処理と比較すると活性化の度合が若
干少なく、またリーク電流も若干大きいが、480
℃という低温であつても実用的には充分な電気的
活性化が行われ、またリーク電流密度も実用上全
く問題にならないレベルに抑えられていることが
わかる。
実施例 ２
比抵抗〜20Ω・cmのｎ型Si基体に注入エネルギ
ー20keVで１×1015個／cm2の注入量にて硼素イオ
ン（B+、質量数11）を注入する。続いて前記硼
素イオンの注入層に重畳せしめて注入エネルギー
150keVで、５×1014個／cm2の注入量にて錫イオ
ン（Sn+、質量数118.7）を注入する。この時の上
記注入イオンのSi基体中における濃度分布は略第
２図に示す如くなる。尚、実施例１と同様上記イ
オン注入はチヤネリング現象を生ぜしめない条件
下にて行なつた。上記工程後、Si基体を窒素
（N2）雰囲気中で熱処理した。熱処理温度は480
℃、熱処理時間は30分であつた。該熱処理後の上
記イオン注入層の層抵抗値は、実施例１の場合よ
りさらに小さく、0.19kΩ／□であつた。また、
逆方向リーク電流特性を調べた結果、逆方向印加
電圧8Vに対し〜１×10-9A／cm2となり、さらに
改善が認められた。
実施例 ３
本実施例では、実施例１、２で述べたシリコン
イオン、錫イオンの代わりにゲルマニウムイオン
（Ge+、質量数73）を硼素イオン注入層に重畳せ
しめて注入した。ゲルマニウムのイオン注入条件
は、注入エネルギー110keV、注入量５×1014
個／cm2であつた。他の条件は実施例１、２と略同
様である。窒素雰囲気中、480℃30分の熱処理後
に得られた上記イオン注入層の層抵抗値は
0.21kΩ／□であつた。又、逆方向の接合リーク
特性は、逆方向印加電圧8Vに対し、1.8×
10-9A／cm2と実用的に充分なレベルのリーク電流
密度であつた。
上記実施例で明らかな様に、本発明の方法を用
いることによつて、実用的に充分なレベルの硼素
イオン注入層の低温活性化を初期の濃度分布を殆
ど変えないで図ることができる。本発明の特徴
は、従来例の様に、硼素イオン注入後のシリコン
基体に単にシリコンイオンを非晶質化充分な量注
入するだけではなく、硼素イオン注入層に対する
シリコンイオン注入層濃度分布を厳密に限定して
形成することにある。すなわち、具体的には、シ
リコン基体に硼素イオン注入層形成後、前記硼素
イオン注入層の深部において硼素濃度分布の広が
りを越えない様に、且つ深さ方向からみた濃度分
布の極大値の位置を略合致させる様にしてシリコ
ンイオン注入層を形成する。シリコンイオン注入
濃度分布の極大値位置が硼素イオンの注入濃度分
布の極大値位置より離れると、熱処理時の硼素不
純物の電気的活性化効率が悪くなる。極大値の位
置は注入エネルギーに依つて一義的に決定される
ので、シリコンイオンの注入エネルギーを変えた
場合の熱処理後の硼素イオン注入層々抵抗値を、
硼素イオン注入量１×1015個／cm2、シリコンイオ
ン注入量１×1015個／cm2の組み合わせについて、
下表に示す。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improvement in the process of forming a p-type layer by implanting boron ions into an n-type layer of a silicon substrate. BACKGROUND ART In order to increase the density and speed of semiconductor integrated circuits, mainly silicon integrated circuits, various active elements and passive elements that constitute the circuits are being miniaturized. In the manufacturing process of silicon integrated circuits, various heat treatment processes (maximum temperature 1000-1100℃) are used.
However, it is important to suppress the movement or redistribution of doping impurities in the substrate by lowering the heat treatment temperature as much as possible when achieving the above-mentioned miniaturization. In recent years, ion implantation has become widely used as a method for precisely doping impurities into semiconductor substrates such as silicon. Usually, a heat treatment process is added to the substrate that has undergone the ion implantation process.
Electrical activation of doping impurities and recovery of crystal damage caused in the base crystal during ion implantation are simultaneously achieved. The heat treatment temperature in this case is usually
A temperature of about 900 to 1000°C is required. In this temperature range, most of the doping impurities, including boron (B), diffuse into the silicon substrate.
Manufacturing even finer elements is difficult. In order to realize fine devices, it is strongly desired to have a method of electrically activating impurities in a low temperature region, which hardly causes redistribution of impurities doped into a substrate by ion implantation. In the case of low-temperature activation of boron impurities ion-implanted into a silicon substrate, a method is conventionally known in which boron ion implantation and ion implantation of silicon or the like are superimposed. According to this method, after forming a boron ion-implanted layer, an element having a mass number larger than boron atoms, such as silicon, is implanted at a high concentration into the silicon substrate to form an amorphous silicon layer containing the boron ion-implanted layer. By forming the
Approximately 100% boron ion implantation layer by heat treatment at around 600℃
It can be activated soon. However, in the manufacturing process of silicon integrated circuits and the like, it is often necessary to perform heat treatment at a temperature of, for example, 500° C. or lower after ion implantation of impurities such as boron. If the above-mentioned conventional method is used in such a case, the heat treatment temperature is limited to 500°C or less, so that the amorphous layer produced by silicon ion implantation after boron ion implantation cannot be sufficiently recrystallized. Particularly when a p + -n junction is formed, junction leakage is likely to occur due to residual defects caused by silicon ion implantation that exist in a region deeper than the junction, making it difficult to form a good device. Nakatsuta. The present invention provides a method for manufacturing a semiconductor device using a low temperature activation method of a boron ion implanted layer in a silicon substrate, which eliminates the drawbacks of the conventional method. The present invention comprises a first ion implantation layer obtained by implanting boron ions into an n-type layer of a silicon substrate, and implanting ions that have a larger mass number than boron ions and do not affect the conductivity type of the silicon substrate. The position of the maximum value of the concentration distribution of the second ion-implanted layer is made to substantially match that of the second ion-implanted layer, and the spread of the concentration distribution of the second ion-implanted layer in a region deeper than the maximum value is that of the first ion-implanted layer. The first ion-implanted layer, that is, the boron ion-implanted layer, is electrically activated by forming the first ion-implanted layer, that is, the boron ion-implanted layer, by heat treatment after forming the first ion-implanted layer so as not to exceed the spread of the concentration distribution of the implanted layer. The implantation amount of the second ion implantation layer varies depending on the ion species, but is preferably at least 5×10 14 ions/cm 2 or more. According to the present invention, by defining the concentration distribution of the first and second ion-implanted layers, even if the subsequent heat treatment is performed at a low temperature of, for example, 500°C or less, the second ion-implanted layer It is possible to form a pn junction with less influence of amorphous layers and residual defects, and less leakage. Hereinafter, specific examples of the present invention will be described. Example 1 Boron ions (B + :mass number 11) are implanted into an n-type Si substrate having a specific resistance of ~20 Ω·cm at an implantation energy of 20 keV and at a dosage of, for example, 1×10 15 ions/cm 2 . Subsequently, silicon ions (Si + :mass number 28) are implanted at an implantation energy of 45 keV and an implantation amount of 1×10 15 ions/cm 2 superimposed on this boron ion implantation layer. The concentration distribution of the implanted ions in the Si substrate at this time is approximately as shown in FIG. Incidentally, the above ion implantation was performed under conditions that did not cause the so-called channeling phenomenon. At the above process level, the Si substrate is exposed to nitrogen (N 2 ).
Heat treated in an atmosphere. The heat treatment temperature was 480°C and the heat treatment time was 30 minutes. The layer resistance value of the ion-implanted layer after the heat treatment was 0.24 kΩ/□. or,
This boron ion implantation layer (p + layer) and the substrate (n type)
As a result of investigating the reverse leakage current characteristics (junction leakage) between
The leakage current density was about 10 -9 A/cm 2 . For comparison, when heat treatment was performed at 1000°C for 10 minutes, the obtained layer resistance value was 0.13 kΩ/□, and the leakage current density between the ion implantation layer and the substrate was ~10 - 10 A/cm 2 (when applying reverse voltage 8V)
It was hot. Compared to heat treatment at 1000°C, the degree of activation is slightly lower and the leakage current is also slightly larger, but 480°C
It can be seen that even at a low temperature of .degree. C., sufficient electrical activation is achieved for practical purposes, and the leakage current density is suppressed to a level that poses no practical problem. Example 2 Boron ions (B + , mass number 11) are implanted into an n-type Si substrate with a specific resistance of ~20 Ω·cm at an implantation energy of 20 keV and an implantation amount of 1×10 15 ions/cm 2 . Next, the implantation energy is applied to the implanted layer of boron ions.
Tin ions (Sn + , mass number 118.7) are implanted at 150 keV and at an implantation dose of 5×10 14 ions/cm 2 . At this time, the concentration distribution of the implanted ions in the Si substrate is approximately as shown in FIG. Note that, as in Example 1, the ion implantation was performed under conditions that did not cause the channeling phenomenon. After the above steps, the Si substrate was heat treated in a nitrogen (N 2 ) atmosphere. Heat treatment temperature is 480
℃, and the heat treatment time was 30 minutes. The layer resistance value of the ion-implanted layer after the heat treatment was 0.19 kΩ/□, which was even smaller than that of Example 1. Also,
As a result of examining the reverse leakage current characteristics, it was found to be ~1×10 −9 A/cm 2 for a reverse applied voltage of 8 V, indicating further improvement. Example 3 In this example, instead of the silicon ions and tin ions described in Examples 1 and 2, germanium ions (Ge + , mass number 73) were implanted in a superimposed manner on the boron ion implantation layer. The germanium ion implantation conditions are: implantation energy 110keV, implantation amount 5×10 14
pieces/ cm2 . Other conditions are substantially the same as in Examples 1 and 2. The layer resistance value of the above ion-implanted layer obtained after heat treatment at 480℃ for 30 minutes in a nitrogen atmosphere is
It was 0.21kΩ/□. In addition, the junction leakage characteristic in the reverse direction is 1.8× for a reverse applied voltage of 8V.
The leakage current density was 10 -9 A/cm 2 , which was at a practically sufficient level. As is clear from the above embodiments, by using the method of the present invention, a practically sufficient level of low-temperature activation of the boron ion-implanted layer can be achieved with almost no change in the initial concentration distribution. The feature of the present invention is not only to simply implant a sufficient amount of silicon ions into a silicon substrate after boron ion implantation to make it amorphous, as in the conventional example, but also to strictly control the concentration distribution of the silicon ion implanted layer with respect to the boron ion implanted layer. The goal is to form a system that is limited to the following. Specifically, after forming a boron ion-implanted layer on a silicon substrate, the position of the maximum value of the concentration distribution as viewed from the depth direction is determined so as not to exceed the spread of the boron concentration distribution in the deep part of the boron ion-implanted layer. A silicon ion implantation layer is formed so as to substantially match the two. If the maximum value position of the silicon ion implantation concentration distribution is far from the maximum value position of the implantation concentration distribution of boron ions, the electrical activation efficiency of boron impurities during heat treatment deteriorates. Since the position of the maximum value is uniquely determined by the implantation energy, the resistance value of the boron ion implanted layer after heat treatment when the silicon ion implantation energy is changed is
Regarding the combination of boron ion implantation amount 1×10 15 pcs/cm 2 and silicon ion implantation amount 1×10 15 pcs/cm 2 ,
Shown in the table below.
【表】
注入エネルギー20keVの硼素イオン注入層の濃
度分布極大値がシリコン基体表面から深さ略660
〓の位置にあるのに対し、注入エネルギーが(a)
25keV、(b)45keV、(c)100keVのシリコンイオン
注入層の濃度極大値の位置は、シリコン基体表面
からの深さが、夫々略(a)350Å、(b)630Å、(c)1470
Åの位置にある。これらイオン注入層の濃度分布
状態を第３図に示す。エネルギーが45keVの場合
に層抵抗値が最も小さくなることが表から分か
る。尚、注入エネルギーが100keVの場合のシリ
コンイオン注入層の濃度分布の広がりは基体の深
部では硼素イオン注入層の濃度分布領域から完全
にはみ出しており、480℃程度の熱処理温度では
シリコンイオン注入による基体シリコン中の残留
欠陥が基体深部に多量に存在するため、逆方向リ
ーク電流レベルが高く（10-4A／cm2以上）、実用
に供し得ないことは云うまでもない。
第４図は、上記硼素イオン注入層（B+、
20keV １×1015個／cm2）に重畳せしめて、注入
エネルギー45keVにてシリコンイオンを注入し、
基体を窒素雰囲気中で低温処理（480℃、30分）
した場合の、シリコンイオン注入量に対する硼素
イオン注入層の層抵抗値を示したものである。第
４図にはまた、上記シリコンイオン注入の代わり
に錫イオンを注入エネルギー150keV（濃度極大値
はシリコンイオン表面からの深さ〜640Åの位置）
にて注入した場合、およびゲルマニウムを注入エ
ネルギー110keV（濃度極大値位置はシリコン表面
からの深さ〜650Å）にて注入した場合の同様の
低温処理による結果も示した。第４図から明らか
な様に、硼素イオン注入層の低温活性化効果は重
畳注入せしめるイオンの質量数が大きい程大き
く、又重畳注入イオンの質量数が大きくなれば、
比較的低い注入量（２〜３×1014個／cm2）で硼素
イオン注入層の低温活性化が実現できる。
なお、本発明において、第１、第２のイオン注
入層の濃度分布の極大値そのものはいずれが大き
くても構わない。また実施例では、硼素イオン注
入層の形成は注入エネルギー20keV、注入量１×
1015個／cm2にて行なつたが、注入エネルギー、注
入量とも前記値に限定されるものではなく任意で
良い。又低温熱処理条件は実施例の如く480℃、
30分間に限定されるものではなく、400℃以下に
おいても（480℃におけるよりも活性化率は劣る
が）本発明の効果は確認できた。一般には、熱処
理温度の上昇や熱処理時間の増加と共に硼素の活
性化率が増加することも確められた。第２のイオ
ン注入層を本発明の如く形成して硼素の活性化率
が高められる熱処理温度の領域は、種々の実験の
結果、400℃〜900℃であり、900℃以上の温度領
域の熱処理では、硼素イオン注入層単独の熱処理
でも第２のイオン注入層を重畳させた場合の熱処
理でもそれらの間に活性化率の有意差は殆どみら
れなかつた。熱処理雰囲気は窒素ガスに限定され
るものではなく、アルゴンや水素等の不活性ガ
ス、酸化性ガス或いはそれらの混合物であつても
良い。熱処理方法としては、通常の炉による場合
の他、場合によつてはレーザービーム、電子ビー
ム等の高密度エネルギー線照射法を用いても良
い。又、上記実施例では、硼素イオン注入層に重
畳せしめて行なうイオン注入のイオン種としてシ
リコン（Si+）、錫（Sn+）、ゲルマニウム（Ge+）
を用いたが、シリコン基体中に導入して導電型を
変化させず、且つシリコン基体を非晶質化するた
めに有効なイオンならば何んでも良い。一般的に
は硼素イオンよりも質量数が大きい、第族元素
および稀ガス元素の中から選ばれる。或いは、こ
れ等を組み合わせて使用しても良い。これ等のイ
オン種を用いる場合には、本発明の効果を達成す
るために、注入エネルギー、注入量（略５×1014
個／cm2以上）を適宜選択すべきことは云うまでも
ない。勿論、硼素イオン注入をはじめ上記した
種々のイオン注入を行なうに際してはチヤネリン
グ現象を抑制しなければならない。尚、上記実施
例では、シリコン基体中に硼素イオン注入層を形
成した後に選ばれた他のイオンの注入層を前記硼
素イオン注入層に重畳せしめて形成したが、これ
らの形成順序は逆でも良い。又実施例ではシリコ
ン基体に其侭イオン注入を行なつたがシリコン基
体上に酸化膜や窒化膜を設けた後に行なつても良
い。また本発明の方法は、単結晶シリコン基体は
勿論SOI（Silicon−On−Insulator）基板上に
MOS素子やバイポーラ素子等の能動素子および
種々の受動素子等を形成する半導体装置の製造に
適用でき、基体の結晶性は単結晶、非単結晶を問
わない。[Table] The maximum concentration distribution of the boron ion implanted layer with an implantation energy of 20 keV is approximately 660 mm deep from the silicon substrate surface.
〓 position, whereas the injection energy is (a)
The positions of the maximum concentration values of the silicon ion-implanted layer at 25 keV, (b) 45 keV, and (c) 100 keV are approximately (a) 350 Å, (b) 630 Å, and (c) 1470 Å in depth from the silicon substrate surface, respectively.
Located at Å. FIG. 3 shows the concentration distribution state of these ion-implanted layers. It can be seen from the table that the layer resistance value is the smallest when the energy is 45 keV. It should be noted that when the implantation energy is 100 keV, the concentration distribution of the silicon ion implantation layer completely extends beyond the concentration distribution region of the boron ion implantation layer in the deep part of the substrate. Needless to say, since a large amount of residual defects in the silicon exist deep within the substrate, the level of reverse leakage current is high (10 -4 A/cm 2 or more) and cannot be put to practical use. FIG. 4 shows the boron ion-implanted layer (B + ,
20keV 1×10 15 pieces/cm 2 ), and implanted silicon ions at an implantation energy of 45keV.
Low-temperature treatment of the substrate in a nitrogen atmosphere (480℃, 30 minutes)
The graph shows the layer resistance value of the boron ion-implanted layer with respect to the amount of silicon ion implantation. Figure 4 also shows that tin ions are implanted at an energy of 150 keV instead of the silicon ion implantation described above (the maximum concentration is at a depth of ~640 Å from the silicon ion surface).
We also show the results of similar low-temperature treatments when germanium was implanted at 110 keV and when germanium was implanted at an implantation energy of 110 keV (maximum concentration position ~650 Å from the silicon surface). As is clear from FIG. 4, the low-temperature activation effect of the boron ion-implanted layer increases as the mass number of the ions to be superimposedly implanted increases, and as the mass number of the superimposedly implanted ions increases,
Low-temperature activation of the boron ion implantation layer can be achieved with a relatively low implantation dose (2 to 3×10 14 ions/cm 2 ). In the present invention, it does not matter whether the maximum value of the concentration distribution of the first or second ion-implanted layer is large. In addition, in the example, the boron ion implantation layer was formed using an implantation energy of 20 keV and an implantation amount of 1×
Although the implantation was performed at 10 15 particles/cm 2 , the implantation energy and the implantation amount are not limited to the above values and may be arbitrary. Also, the low temperature heat treatment conditions were 480℃ as in the example.
The effect of the present invention was confirmed not limited to 30 minutes, but also at temperatures below 400°C (although the activation rate was inferior to that at 480°C). It was also confirmed that, in general, the activation rate of boron increases as the heat treatment temperature and heat treatment time increase. As a result of various experiments, the heat treatment temperature range in which the activation rate of boron is increased by forming the second ion-implanted layer as in the present invention is 400°C to 900°C. In this case, there was almost no significant difference in activation rate between the heat treatment of the boron ion implanted layer alone and the heat treatment of the second ion implanted layer superimposed thereon. The heat treatment atmosphere is not limited to nitrogen gas, but may be an inert gas such as argon or hydrogen, an oxidizing gas, or a mixture thereof. As the heat treatment method, in addition to using a normal furnace, high-density energy ray irradiation methods such as laser beams and electron beams may be used depending on the case. In the above embodiment, silicon (Si + ), tin (Sn + ), germanium (Ge + ) is used as the ion species for ion implantation superimposed on the boron ion implantation layer.
However, any ion may be used as long as it is introduced into the silicon substrate without changing the conductivity type and is effective for making the silicon substrate amorphous. Generally, it is selected from group elements and rare gas elements that have a larger mass number than boron ions. Alternatively, a combination of these may be used. When using these ion species, the implantation energy and implantation amount (approximately 5×10 14
Needless to say, the number of particles/cm 2 or more should be selected appropriately. Of course, when performing the various ion implantations described above including boron ion implantation, the channeling phenomenon must be suppressed. In the above example, after forming a boron ion-implanted layer in the silicon substrate, a selected ion-implanted layer was formed to overlap the boron ion-implanted layer, but the order of formation may be reversed. . Further, in the embodiment, the ion implantation was performed on the silicon substrate, but it may be performed after forming an oxide film or a nitride film on the silicon substrate. Furthermore, the method of the present invention can be applied not only to a single crystal silicon substrate but also to an SOI (Silicon-On-Insulator) substrate.
It can be applied to the manufacture of semiconductor devices that form active elements such as MOS elements and bipolar elements, and various passive elements, and the crystallinity of the substrate does not matter whether it is single crystal or non-single crystal.
第１図および第２図は本発明の実施例を説明す
るための注入イオン濃度分布を示す図、第３図は
本発明の効果を説明するための注入イオン濃度分
布を示す図、第４図は同じくB+注入層抵抗値と
重畳イオン注入量の関係を示す図である。
1 and 2 are diagrams showing the implanted ion concentration distribution for explaining embodiments of the present invention, FIG. 3 is a diagram showing the implanted ion concentration distribution for explaining the effects of the present invention, and FIG. 2 is a diagram similarly showing the relationship between the resistance value of the B + implanted layer and the amount of superimposed ion implantation.
Claims (1)
工程を含む半導体装置の製造方法において、前記
ｐ型層を形成する工程は、 シリコン基体のｎ型層に硼素イオンを注入して
第１のイオン注入層を形成するする工程と、 前記第１のイオン注入層に重ねて、硼素イオン
より質量数が大きくかつ基体の導電型に影響を与
えないイオンを注入して、その濃度分布の極大値
が前記第１のイオン注入層のそれと略合致し、そ
の極大値より深部での濃度分布の広がりが第１の
イオン注入層のそれを越えないように第２のイオ
ン注入層を形成する工程と、 900℃以下の温度で熱処理して前記第１のイオ
ン注入層を活性化する工程と、 を有することを特徴とする半導体装置の製造方
法。 ２ 第２のイオン注入層の注入量は５×1014個／
cm2以上である特許請求の範囲第１項記載の半導体
装置の製造方法。 ３ 第２のイオン注入層のイオン種は、シリコ
ン、錫またはゲルマニウムである特許請求の範囲
第１項記載の半導体装置の製造方法。[Scope of Claims] 1. In a method for manufacturing a semiconductor device including a step of forming a p-type layer in an n-type layer of a silicon substrate, the step of forming the p-type layer includes the steps of: a step of implanting ions to form a first ion implantation layer, and implanting ions having a mass number larger than boron ions and having no effect on the conductivity type of the substrate, superimposed on the first ion implantation layer. , the maximum value of the concentration distribution substantially coincides with that of the first ion implantation layer, and the second ion implantation layer is arranged such that the concentration distribution at a depth deeper than the maximum value does not exceed that of the first ion implantation layer. A method for manufacturing a semiconductor device, comprising: forming an implantation layer; and activating the first ion implantation layer by heat treatment at a temperature of 900° C. or lower. 2 The implantation amount of the second ion implantation layer is 5×10 14 /
2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has a surface area of at least cm 2 . 3. The method of manufacturing a semiconductor device according to claim 1, wherein the ion species of the second ion-implanted layer is silicon, tin, or germanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15514881A JPS5856417A (en) | 1981-09-30 | 1981-09-30 | Low-temperature activating method for boron ion implanted layer in silicon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15514881A JPS5856417A (en) | 1981-09-30 | 1981-09-30 | Low-temperature activating method for boron ion implanted layer in silicon |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856417A JPS5856417A (en) | 1983-04-04 |
| JPH0334649B2 true JPH0334649B2 (en) | 1991-05-23 |
Family
ID=15599580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15514881A Granted JPS5856417A (en) | 1981-09-30 | 1981-09-30 | Low-temperature activating method for boron ion implanted layer in silicon |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856417A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2055818A1 (en) | 2007-10-30 | 2009-05-06 | TMT Machinery, Inc. | Interlacing device |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60501927A (en) * | 1983-07-25 | 1985-11-07 | アメリカン テレフオン アンド テレグラフ カムパニ− | Shallow junction semiconductor devices |
| FR2602093B1 (en) * | 1985-12-27 | 1988-10-14 | Bull Sa | METHOD FOR MANUFACTURING AN ELECTRIC RESISTOR BY DOPING A SEMICONDUCTOR MATERIAL AND INTEGRATED CIRCUIT THEREFROM |
| JPS6476760A (en) * | 1987-09-18 | 1989-03-22 | Toshiba Corp | Manufacture of semiconductor device |
| JP2522217B2 (en) * | 1990-12-27 | 1996-08-07 | 株式会社島津製作所 | Method for suppressing silicon crystal defects caused by ion implantation |
| US5298434A (en) * | 1992-02-07 | 1994-03-29 | Harris Corporation | Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits |
| JP2919254B2 (en) * | 1993-11-22 | 1999-07-12 | 日本電気株式会社 | Semiconductor device manufacturing method and forming apparatus |
-
1981
- 1981-09-30 JP JP15514881A patent/JPS5856417A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2055818A1 (en) | 2007-10-30 | 2009-05-06 | TMT Machinery, Inc. | Interlacing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5856417A (en) | 1983-04-04 |
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