JPH0396223A - Forming method for soi structure - Google Patents
Forming method for soi structureInfo
- Publication number
- JPH0396223A JPH0396223A JP23329289A JP23329289A JPH0396223A JP H0396223 A JPH0396223 A JP H0396223A JP 23329289 A JP23329289 A JP 23329289A JP 23329289 A JP23329289 A JP 23329289A JP H0396223 A JPH0396223 A JP H0396223A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nuclei
- base
- insulating film
- generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 239000007790 solid phase Substances 0.000 claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 14
- 239000012535 impurity Substances 0.000 abstract description 11
- 239000007787 solid Substances 0.000 abstract description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 18
- 150000002500 ions Chemical class 0.000 description 15
- 239000013078 crystal Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000012071 phase Substances 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 235000014548 Rubus moluccanus Nutrition 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は、S O I (Silicon on In
sulator)構造の形成方法に関し、特に固相成長
法によりSi膜を形成するものに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial field of application The present invention is applicable to S O
The present invention relates to a method for forming a Si film using a solid phase growth method.
(ロ)従来の技術
絶縁層(絶縁物の基板も含む)上に単結晶Si層を形或
したものは、Sol構造と称され、狭い領域で容易に素
子分離が行え、高集積化や高速化が可能なものとして知
られている。そして、従来のSi基板上に素子が作製さ
れる半導体集積回路(IC)に比べて、特性向上が図ら
れることから盛んに研究開発が行われている。(b) Conventional technology A structure in which a single crystal Si layer is formed on an insulating layer (including an insulating substrate) is called a Sol structure, and allows for easy element isolation in a narrow area, resulting in high integration and high speed. It is known as something that can be changed. Furthermore, research and development are being actively conducted on semiconductor integrated circuits (ICs) because they offer improved characteristics compared to conventional semiconductor integrated circuits (ICs) in which elements are fabricated on Si substrates.
絶縁層上に単結晶Si膜を形成させるものの一つに、固
相エピタキシャル戊長法があり、これは、単結晶Si基
板上に、Si基板面の一部をシードとして露出させて絶
縁膜を形威し、シードと絶縁膜上に非晶質Si(以下a
−Siと称する)膜を堆積し、600℃程度の低温でア
ニールすることで、横方向に固相戊長させてa−Si膜
を単結晶化させるものである。One of the methods for forming a single crystal Si film on an insulating layer is the solid phase epitaxial elongation method, in which an insulating film is formed on a single crystal Si substrate by exposing a part of the Si substrate surface as a seed. As a result, amorphous Si (hereinafter a) is deposited on the seed and insulating film.
-Si) is deposited and annealed at a low temperature of about 600° C., thereby elongating the solid phase in the lateral direction and converting the a-Si film into a single crystal.
固相戊長における横方向の成長距離を伸ばす方法として
、絶縁膜上のa−Si膜にP1イオンを高濃度に注入し
てから、アニール処理を行うものがある(Extend
ed Abstracts of the 16th
Conference on Solid State
Devices and Materials,Ko
be, 1984. pp507−510参照)。One way to extend the lateral growth distance during solid phase elongation is to implant P1 ions at a high concentration into the a-Si film on the insulating film, and then perform an annealing process.
ed Abstracts of the 16th
Conference on Solid State
Devices and Materials, Ko
be, 1984. (See pp507-510).
しかし、横方向の戊長距離を伸ばすために、P1イオン
を3 X 10”cm−”という高濃度にドービンダす
るので、同相威長した単結晶Si膜中の不純物(P)濃
度が非常に高くなってしまい、この固相成長した単結晶
Si膜上での半導体デバイスの作製は困鷺であった。However, in order to extend the lateral distance, P1 ions are doped to a high concentration of 3 x 10"cm-", so the impurity (P) concentration in the in-phase monocrystalline Si film is extremely high. Therefore, it has been difficult to fabricate a semiconductor device on this solid phase grown single crystal Si film.
そこで、絶縁膜上に堆積したa−Si膜の絶縁膜との界
面を除く表面付近だけにP4イオンを注入して同相成長
させ、その後、P9イオンを注入した部分を除去するこ
とで、不純物濃度の低い大面積のSonI造を得ること
が考えられている(1989、第20回理研シンポジウ
ム 予稿集第5頁乃至8頁参照)。Therefore, by implanting P4 ions only near the surface of the a-Si film deposited on the insulating film, excluding the interface with the insulating film, to cause in-phase growth, and then removing the part where P9 ions were implanted, the impurity concentration It is being considered to obtain a large-area SonI structure with a low (1989, 20th RIKEN Symposium Proceedings, pages 5 to 8).
(ハ)発明が解決しようとする課題
しかしながら、a−Si膜の表面付近だけにP“イオン
を注入して固相或長させる場合、Pが導入されていない
領域で、エビタキシャル戊長のためのシード(単結晶基
板面)の結晶方位を継承しない核が発生しやすい。この
ため、その様な核の発生によりシードからのエビタキシ
ャル成長が阻害され、a−Si膜の膜厚方向の全領域に
Pを導入した場合に較べ、横方向のエビタキシャル戊長
距離が短くなってしまう。(c) Problems to be Solved by the Invention However, when P'' ions are implanted only near the surface of the a-Si film to form a solid phase, the region where P has not been introduced will undergo evitaxial elongation. Nuclei that do not inherit the crystal orientation of the seed (single-crystal substrate surface) are likely to occur.For this reason, the generation of such nuclei inhibits the epitaxial growth from the seed, and the entire thickness of the a-Si film is Compared to the case where P is introduced into the region, the lateral epitaxial long distance becomes shorter.
本発明は、斯様な点に鑑みて為されたもので、横方向の
エビタキシャル戊長距離を伸ばし、不純物濃度が低く、
大面積のSO■構造を形成するものである。The present invention has been made in view of these points, and has a long lateral epitaxial distance, a low impurity concentration, and
This forms a large-area SO■ structure.
(二)課題を解決するための手段
本発明は、単結晶Si基台上に基台表面の一部を露出さ
せて絶縁膜を形成する工程と、基台と絶縁膜表面上にa
−Si膜を形成する工程と、該a一Sillの前記絶縁
膜との界面付近に核の発生を抑え不活性な元素を導入す
る工程と、前記a−Si膜の前記不活性な元素の導入さ
れた領域よりも表面側に核の発生を抑え活性な元素を導
入する工程と、アニールによりa−Si膜を固相戊長さ
せる工程と、同相戊長したSi膜のうち前記活性な元素
を導入した領域を除去する工程とを備えるSOI構造の
Nj虞方法である。(2) Means for Solving the Problems The present invention includes a step of forming an insulating film on a single crystal Si base by exposing a part of the base surface, and a step of forming an insulating film on the base and the surface of the insulating film.
- a step of forming a Si film, a step of introducing an inactive element to suppress generation of nuclei near the interface with the insulating film of the a-Sill, and introducing the inert element into the a-Si film; a step of suppressing the generation of nuclei and introducing an active element to the surface side of the a-Si film, a step of elongating the a-Si film in a solid phase by annealing, and a step of introducing the active element in the in-phase elongated Si film. This is an Nj method for an SOI structure comprising a step of removing the introduced region.
(ホ)作用
横方向のエビタキシャル或長を阻害する核は、a−Si
膜と絶縁膜との界面付近で発生するので、その界面付近
に核の発生を抑え不活性な元素を導入し、7その領域の
上に核の発生を抑え活性な元素を導入することで、核の
発生がa−Si膜全体で抑えられ、同時に活性な元素を
導入した領域で横方向への固相エビタキシャル戊長遠度
が大きくなるので、a−Si膜全体の横方向の同相エビ
タキシャル虞長遠度が大きくなって、横方向の同相エビ
タキシャル威長距離が伸びる.そして、活性な元素を導
入した領域を除去することにより、不純物濃度の低いS
i膜からなるSOI構造が得られる。(e) The nucleus that inhibits the lateral ebitaxial elongation is a-Si
Since it occurs near the interface between the film and the insulating film, by introducing an inert element near that interface to suppress the generation of nuclei, and introducing an active element above that area to suppress the generation of nuclei, Nucleation is suppressed throughout the a-Si film, and at the same time, the lateral solid-phase epitaxial elongation increases in the region where active elements are introduced, so the lateral in-phase epitaxial elongation of the entire a-Si film increases. The long distance increases, and the lateral in-phase epitaxial distance increases. Then, by removing the region into which active elements have been introduced, S with a low impurity concentration is created.
An SOI structure consisting of an i-film is obtained.
(へ)実施例
第l図A乃至Fは本発明一実施例の概略工程図を示す.
本実施例では、単結晶基台として単結晶Sf基板を用い
ているが、絶縁基板等の基板上に形威された単結7Si
膜を用いてもよい。(F) Example 1 Figures A to F show a schematic process diagram of an example of the present invention.
In this example, a single-crystal Sf substrate is used as the single-crystal base, but a single-crystal 7Si substrate formed on a substrate such as an insulating substrate
A membrane may also be used.
(1.)は(100)面を主面とする単結晶Si基台と
しての単結晶Si基板で、その表面に絶縁膜として膜厚
500人程(F) S f O *膜(2〉をCVD法
あるいは熱酸化により形威し、更に公知の技術である7
才トリソグラ7イ技術により、[001]方向のストラ
イブ状に、シードとしてのSi基板表面が露出する開孔
部(2a)を形成する(第1図A)。(1.) is a single-crystal Si substrate as a single-crystal Si base with (100) plane as the main surface, and an insulating film with a thickness of about 500 mm (F) S f O * film (2) is coated on its surface. It is formed by CVD method or thermal oxidation, and is a well-known technique7
Openings (2a) through which the surface of the Si substrate serving as a seed is exposed are formed in a stripe shape in the [001] direction using a trithography technique (FIG. 1A).
次に基板を洗浄後、図示しないCVD装置1こ設置し、
基板表面(開孔部(2a)において露出しているSi基
板(1)表面とS i O t膜(2)上)にa−Si
膜(3)を約600nm堆積させる(第l図B)。Next, after cleaning the substrate, one CVD device (not shown) was installed.
A-Si is deposited on the substrate surface (on the Si substrate (1) surface exposed in the opening (2a) and on the SiOt film (2)).
Film (3) is deposited to a thickness of approximately 600 nm (FIG. 1B).
そして、a−Si膜(3)とS i O !膜(2)と
の界面付近に、核の発生を抑え不活性な元素である、例
えばF4イオンを加速エネルギー190keV、ドーズ
量I X101c1”でイオン注入する(第1図C)。And a-Si film (3) and SiO! Near the interface with the film (2), F4 ions, which are an inert element that suppresses the generation of nuclei, are implanted at an acceleration energy of 190 keV and a dose of IX101c1'' (FIG. 1C).
注入するイオンは、F1イオンの他に、例えばN4″イ
オンでもよい。The ions to be implanted may be, for example, N4'' ions in addition to F1 ions.
更に続いて、核の発生を抑え活性な元素であるP+イオ
ンを、F4″イオンが注入された領域(Fドーブ層(3
a))よりも表面側(上側)に、加速エネルギー200
keV, ドーズ量4 X 10”cm−”と、加速
エネルギー100keV、ドーズ量1.5X 10”c
m−”との重ね合わせのイオン注入を行う(第1図D)
。注入するイオンは、P“イオンの他に、例えばAs”
イオンでもよい。Furthermore, P+ ions, which are active elements that suppress the generation of nuclei, are implanted in a region where F4'' ions are implanted (F dove layer (3)).
Acceleration energy 200 on the surface side (upper side) than a))
keV, dose 4 x 10"cm-", acceleration energy 100keV, dose 1.5 x 10"c
Perform ion implantation overlapping with m-” (Fig. 1D)
. In addition to P" ions, the ions to be implanted include, for example, As" ions.
It may be an ion.
ここで、活性な元素とは、固相成長時にその成長距離を
伸ばす働きをする元素であり、またキャリアを発生する
元素である。一方、不活性な元素とは、半導体層中にお
いてキャリアを発生しない。通常、a−Si膜中にSi
以外の元素を導入した場合、そのa−Si膜の固相戊長
時に核の発生は抑えられる。Here, the active element is an element that works to extend the growth distance during solid phase growth, and an element that generates carriers. On the other hand, an inactive element does not generate carriers in the semiconductor layer. Usually, Si in the a-Si film is
When other elements are introduced, the generation of nuclei during solid phase elongation of the a-Si film is suppressed.
第2図の不純物濃度プロファイルに示すように、イオン
注入の結果、a−Si膜(3)とS i O !膜(2
)との界面付近にFが導入されたFドープ層(3a)と
、そのFドープ層(3a)上にPが導入されたPドープ
層(3b)が形成される。As shown in the impurity concentration profile in FIG. 2, as a result of the ion implantation, the a-Si film (3) and SiO! Membrane (2
), and a P-doped layer (3b) in which P is introduced is formed on the F-doped layer (3a).
次に、基板を電気炉にセットし、窒素(N,)雰囲気中
で、600℃、約12時間のアニール処理を行う。この
アニール処理により単結晶Si基板(1)上のa−Si
膜(3a)は、単結晶Si基板(1)をシードとして、
固相エピタキシャル成長し単結晶Si膜(3゛)が形成
される(第1図E)。Next, the substrate is set in an electric furnace and annealed at 600° C. for about 12 hours in a nitrogen (N,) atmosphere. By this annealing treatment, the a-Si on the single crystal Si substrate (1)
The film (3a) is formed using a single crystal Si substrate (1) as a seed.
Solid phase epitaxial growth is performed to form a single crystal Si film (3゛) (FIG. 1E).
このとき、a−Si膜(3)全体の横方向の固相エピタ
キシャル戊長速度は、Pドーブ層(3b)の厚さ(本実
施例ではおよそ270乃至350nm)で決定し、この
場合、約6 X 10−’cm/sテあり、同時にa−
St膜(3)中に導入した核の発生を抑える元素により
、核の発生(特にa−Si膜(3)とSiO,膜(2)
との界面付近での発生)が抑えられて、251mの横方
向へのエビタキシャル戊長距離が得られた。At this time, the lateral solid-phase epitaxial growth rate of the entire a-Si film (3) is determined by the thickness of the P dove layer (3b) (approximately 270 to 350 nm in this example), and in this case, approximately 6 X 10-'cm/s, at the same time a-
The element that suppresses the generation of nuclei introduced into the St film (3) suppresses the generation of nuclei (particularly in the a-Si film (3) and SiO film (2)).
(occurrence near the interface with
最後に、高濃度の不純物層であるPドープ層(3b)を
、このPドーブ層(3b)だけを除去するエッチャント
、例えばH F : H N O ! ’ C H s
C 00H= 1 :3 :8のエツチャントにより
ウエットエッチングして、不活性な元素が導入されデバ
イス作製時に不都合な不純物が少ない領域だけの単結晶
Si膜(3′)とし、SOI溝造が形成される(第1図
F)。Finally, the P-doped layer (3b), which is a highly doped impurity layer, is treated with an etchant that removes only this P-doped layer (3b), such as H F : H N O ! 'C Hs
Wet etching is performed using an etchant of C 00H = 1:3:8 to form a single crystal Si film (3') only in the region where inactive elements are introduced and there are few impurities that are inconvenient during device fabrication, and an SOI groove structure is formed. (Figure 1F).
(ト)発明の効果
本発明は、以上の説明から明らかなように、a−Si膜
とSin.膜との界面付近にFを導入して界面付近での
エビタキシャル戊長を阻害する核の発生を抑え、その上
面側にPを導入して横方向の固相エビタキシャル戊長速
度を早めることで、横方向のエビタキシャル戊長距離を
伸ばすことができ、さらに固相戊長後、Pを導入した不
純物濃度の高い領域を除去することで、デバイス作製に
不都合な不純物濃度の低い、大面積の単結晶Si膜を形
成することができる。(G) Effects of the Invention As is clear from the above description, the present invention provides an a-Si film and a Sin. Introducing F near the interface with the membrane to suppress the generation of nuclei that inhibit epitaxial elongation near the interface, and introducing P on the upper surface side to accelerate the solid phase epitaxial elongation speed in the lateral direction. In addition, by removing the high impurity concentration region where P is introduced after solid phase elongation, it is possible to create a large area with low impurity concentration that is inconvenient for device fabrication. A single crystal Si film can be formed.
而して、半導体デバイスの作製に適したSOI構造の基
板が提供でき、半導体集積回路における高集積化や特性
の向上に寄与できる。Thus, a substrate with an SOI structure suitable for manufacturing semiconductor devices can be provided, contributing to higher integration and improved characteristics in semiconductor integrated circuits.
第1図A乃至Fは本発明一実施例の工程説明図、第2図
は本発明一実施例に係る不純物濃度のプロファイルを示
す図である。1A to 1F are process explanatory diagrams of an embodiment of the present invention, and FIG. 2 is a diagram showing an impurity concentration profile according to an embodiment of the present invention.
Claims (1)
絶縁膜を形成する工程と、基台と絶縁膜表面上に非晶質
Si膜を形成する工程と、該非晶質Si膜の前記絶縁膜
との界面付近に核の発生を抑え不活性な元素を導入する
工程と、前記非晶質Si膜の前記不活性な元素の導入さ
れた領域よりも表面側に核の発生を抑え活性な元素を導
入する工程と、アニールにより非晶質Si膜を固相成長
させる工程と、固相成長したSi膜のうち前記活性な元
素を導入した領域を除去する工程とを備えることを特徴
とするSOI構造の形成方法。(1) A step of forming an insulating film on a single crystal Si base by exposing a part of the base surface, a step of forming an amorphous Si film on the base and the surface of the insulating film, and a step of forming an amorphous Si film on the base and the surface of the insulating film. A step of introducing an inert element to suppress the generation of nuclei near the interface between the Si film and the insulating film, and a step of introducing an inert element to suppress the generation of nuclei in the vicinity of the interface of the Si film with the insulating film; The method includes a step of suppressing generation and introducing an active element, a step of growing an amorphous Si film in a solid phase by annealing, and a step of removing a region of the solid phase grown Si film into which the active element has been introduced. A method for forming an SOI structure characterized by the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1233292A JP2994667B2 (en) | 1989-09-08 | 1989-09-08 | Method of forming SOI structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1233292A JP2994667B2 (en) | 1989-09-08 | 1989-09-08 | Method of forming SOI structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0396223A true JPH0396223A (en) | 1991-04-22 |
JP2994667B2 JP2994667B2 (en) | 1999-12-27 |
Family
ID=16952820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1233292A Expired - Lifetime JP2994667B2 (en) | 1989-09-08 | 1989-09-08 | Method of forming SOI structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2994667B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5457058A (en) * | 1989-10-09 | 1995-10-10 | Canon Kabushiki Kaisha | Crystal growth method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329200A (en) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | Method of manufacturing semiconductor device |
-
1989
- 1989-09-08 JP JP1233292A patent/JP2994667B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5457058A (en) * | 1989-10-09 | 1995-10-10 | Canon Kabushiki Kaisha | Crystal growth method |
Also Published As
Publication number | Publication date |
---|---|
JP2994667B2 (en) | 1999-12-27 |
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