JPS60164316A - Formation of semiconductor thin film - Google Patents

Abstract

PURPOSE:To enable the formation of a semiconductor layer with excellent reproducibility and uniformity and with a simple structure and sufficient properties for practical use, by implanting ions into at least a part of polycrystalline silicon formed on the substrate for rendering it amorphous. CONSTITUTION:Poly-Si is adhered by CVD or the like on an amorphous insulation substrate 1 such as a quartz plate or the like consisting of SiO2, and then pattern etched to form a polycrystalline silicon layer 2. Thereafter, ions of Si<+> for example are implanted into at least a part of polycrystalline silicon layer 2 to form an amorphous region 3. This amorphous region 3 is formed only in the central portion of the polycrystalline silicon layer 2, while both sides thereof are left as polycrystalline regions 2a and 2b. The polycrystalline silicon layer 2 thus partially rendered amorphous is heat treated so as to cause the amorphous region 3 to crystal grow in solid phase and to form a solid-phase growth region 4. When said heat treatment is effected at a temperature within the range from 600 deg.C-700 deg.C, approximately cylindrical large crystal grains H are formed throughout the width of the amorphous region, and thus the solid-phase growth region 4 having good reproducibility can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a semiconductor thin film on an amorphous substrate such as 5LO2 (silicon dioxide).

[Background is technology and its problems]

When manufacturing thin film semiconductor devices such as TFTs (thin film transistors), a semiconductor layer close to single crystal silicon or 1.INqIi crystal is formed on an amorphous insulating substrate such as 5bO2 (silicon dioxide). Eight folds are formed.

As described above, in order to form a semiconductor layer close to a crystalline layer on an amorphous substrate, conventionally, polysilicon (PolySL) is deposited on the substrate in advance by, for example, CVD (chemical vapor deposition). ), and this crystalline silicon is partially melted and solidified by heat treatment such as laser annealing, electron beam annealing, or graphite heater annealing to form rT3 crystals.

However, in such conventional methods, reproducibility is poor due to variations in the nuclei during recrystallization, and it is difficult to treat the entire surface because it is sequentially heated at high temperatures to melt and solidify. It takes a long time to process, and changes in heating conditions during this time, such as fluctuations in laser output and changes in substrate temperature, can cause uniformity to deteriorate.Also, since the process is performed at a high temperature close to the melting temperature, thermal stress during solidification may occur. IX) Achieving a temperature environment conducive to maintaining good crystallization The structure of the heat dissipation pattern on the surface of the substrate becomes complicated. Furthermore, a special heat treatment device is required.

[Purpose of the invention]

In view of the above points, the present invention has excellent reproducibility and uniformity,
The object of the present invention is to provide a method for forming a semiconductor layer that does not require heat treatment at a high temperature as in the case of a molten wet layer, has a simple structure, and can form a semiconductor layer having practically sufficient characteristics.

[Summary of the invention]

That is, the method for forming a semiconductor thin film according to the present invention includes a step of forming polycrystalline silicon on a substrate such as a quartz plate by CVD or solid phase growth after ion implantation, which will be described later. At least -? 111 minutes Ks=
A process of ion-implanting +6 ion-implanted Ge to make it amorphous, and a process of growing crystals in the amorphous part in the same phase by heat treatment at a relatively low temperature, for example, about 550°C to 1000°C. It is characterized by having the following. Therefore, it has improved appearance and uniformity (177t), is a low-temperature process compared to conventional processes, does not generate defects due to thermal stress, eliminates the need to form complex heat dissipation patterns on the substrate, and Since there is no need to sequentially melt assimilate and recrystallize parts as in the conventional method, there is an advantage that the processing time is short and there is no residue.

〔Example〕

Preferred embodiments of the present invention will be described below with reference to the drawings.

First, in FIG. 1, Po1y-S=(polycrystalline silicon) is deposited on an amorphous insulating substrate 1 such as a quartz plate made of 5bO2 (photooxidized silicon) by CVD (chemical vapor deposition) or the like.
A polycrystalline silicon layer 2 is formed by depositing and pattern etching 19. The thickness of this polycrystalline silicon layer 2 is, for example, approximately 1000X, and the grain size of the internal crystal grains (so-called grains) is approximately equal to or greater than xooL, although this varies depending on the conditions of the CVD process.

Next, as shown in FIG. 2, for example, S,+ (silicon ions) are ion-implanted into at least a portion of the polycrystalline silicon layer 2 to form an amorphous region 3. As shown in the schematic plan view of FIG. 3, both sides of polycrystalline silicon layer 2 are formed into polycrystalline regions 2ay.
2b and only in the center, for example, a width of 2μ to lOμ
The amorphous region 3 is formed. The conditions for ion implantation at this time are the peak of the distribution at a depth of 1", the so-called projection range Rp
By implanting ions with a laser beam so as to have a thickness of 1/2 of the thickness of the polycrystalline silicon layer 2, and setting the implanted dose to approximately I x 1015/r:n1 or more when the implanted ions are SL+. , so that grain boundaries within the polycrystalline silicon are not substantially completely destroyed, resulting in an amorphous structure. Note that, as the implanted ions, other than S-, ions such as Ge''4 that do not have an adverse effect on semiconductors can be used.

In this way, a partially amorphous polycrystalline silicon layer 2 is formed.
By heat-treating the amorphous region 3 at, for example, about 600° C., the amorphous region 3 is crystal-grown in a solid phase state, thereby forming a solid-phase growth region 4 as shown in FIGS. 4 and 5. At this time, the solid phase growth consists of the amorphous region 3 and the polycrystalline remaining region 2a.
, 2b in the lateral direction (horizontal direction) from interface B, , B2 with
The growth rate is higher than the random growth rate upward in the surface of the amorphous 'J 2ifi plate 1 in Figure I54, and inside the solid phase growth region 4, As shown schematically, each multi-s-i item remaining '1 tracking area 2 a, 2
Large rod-shaped crystal grains 1' will grow at 1111 in the direction 111''I in the figure using the crystal grains G, etc. existing in B2 as the nucleus. The growth j441D4 of the above-mentioned lateral crystal growth and random nucleus growth from the substrate surface varies depending on the temperature of the above-mentioned heat treatment. It is possible to grow and form crystal grains.However, when r+, ?
If the width of
When the heat treatment is carried out at a temperature within the range of 700°C to 700°C, the lateral crystal growth is sufficiently faster than the random nucleus growth, and the width of the amorphous region 3 is 10 μm.
Although it is quite wide, the substantially rod-shaped large crystal grains Hmp are formed so as to cover the entire area, and a solid phase growth region 4 with good reproducibility can be obtained. In addition, the original amorphization 1
550℃~1000℃ when the width of 111 area 3 is narrow etc.
Of course, the solid phase growth region 4 can be obtained by performing heat treatment at a temperature within the range of .

By the way, in the ion implantation process shown in FIGS. 2 and 3, both ends (left and right ends in the figure) of the polycrystalline silicon layer 2 are left as polycrystalline silicon, and ions are implanted only in the center. For example, by implanting ions into the region 2b, one side of the polycrystalline silicon layer 2 (411 +
1) The whole may be made amorphous. In this case, only one interface B0 exists between the amorphous region and the remaining polycrystalline region, and the above-mentioned lateral in-phase growth is performed only in one direction from this interface B7. Two interfaces B1. The lateral growth from B2 does not collide in the middle, and the number of grain boundaries can be further reduced. Note that when ion implantation is performed on the entire one side of such polycrystalline silicon layer 2, the distance from the interface B1 to the edge of 1 kill of ion-implanted polycrystalline silicon layer 2 is, for example, 2 μm-1o.
Of course, it is j6fi to set it so that it is μm.

-1: The heat treatment process for in-phase growth is the same as in the above example.

The in-phase growth region 4 formed in this way has significantly fewer boundaries (baranku) than general polycrystalline silicon, and eliminates dangling bonds that have occurred on the surface of these boundary areas. Because it is possible to reduce
Good characteristics close to those of a single crystal semiconductor (for example, μ (mobility) is low) can be obtained with good reproducibility, and this region 4 can be used, for example, as an active region of a MOS transistor.

Here, the above heat treatment does not require any special equipment such as a laser annealing device, an electron beam annealing device, or a graphite heater device, which is required when forming conventional semiconductor devices, and can be performed using, for example, a general diffusion furnace. In addition, since it uses solid-phase growth in a low-temperature process instead of recrystallizing by melting and solidifying as in conventional methods, it eliminates the need for heat dissipation patterns on the substrate surface, and There is no occurrence of distortion due to stress. In addition, when manufacturing high-density integrated circuits, when a large number of active regions are formed in a polycrystalline silicon layer deposited on an amorphous substrate, non-active regions corresponding to these active regions are required. After each crystallized region is formed, by performing the above heat treatment once, all the amorphous regions can be grown in a solid phase at the same time, and there is no need to sequentially perform partial heat treatment as in the conventional method. Not only does it have excellent uniformity and high processing efficiency, but also
As in a normal diffusion process, a plurality of wafers can be introduced into a heating furnace such as a diffusion furnace and the above-mentioned heat treatment can be performed on the plurality of wafers at the same time, thereby greatly improving mass productivity.

Next, in the above-mentioned embodiment, in-phase growth is performed only in one direction (for example, the left-right direction in FIG. At least a portion of the solid-phase growth region 4, which is a silicon region, is again subjected to an amorphous treatment by ion implantation in a direction substantially perpendicular to the above-mentioned direction on the substrate plane (the vertical direction in FIG. 5) (/? - Solid phase growth may be performed.

That is, in the polycrystalline silicon layer 2 of the amorphous substrate 1, as shown in FIG. 4 is formed, and a portion other than both ends of this region 4 in a direction substantially perpendicular to the solid-phase growth direction (in the direction in the figure), for example, a region 5 surrounded by imaginary lines in the figure. Then, IJ[1] is subjected to amorphous treatment by ion implantation. This ion implantation (d1) As in the embodiment described above, ions that have no adverse effect on the semiconductor polycrystalline layer such as 5L-1- or 01 are implanted into the polycrystalline layer (in this case, the in-phase growth region 4).
) The ion-implanted region is generally amorphous '1! Drive with a dose of nail a and a sufficient amount of energy to turn into a ``Thfl''.

Next, as in the above-described embodiment, heat treatment is performed at, for example, about 600° C. to perform in-phase growth. At this time, the solid phase growth proceeds in the vertical direction in the figure with the two ends of the region 4 where the rod-shaped large crystal grains were formed as nuclei, so that the planar or thin plate-like large crystal grains grow within the region. By forming the ion-implanted portion (see the shaded area in the figure), the number of grain boundaries is further reduced, and the characteristics are improved. In principle, a polycrystalline silicon layer deposited by a CVD method or the like is subjected to intensive heat treatment for ion implantation and solid phase growth by turning the edges three times. , a single crystal having desired dimensions in the three-dimensional direction of length and thickness is obtained.

Note that the present invention is not limited to the above-mentioned embodiments, and the planar shapes of the polycrystalline silicon layer 2, the region 3 made amorphous by ion implantation, etc. may be varied in addition to those shown in the drawings. Of course, a large number of polycrystalline silicon layers and amorphous regions may be formed on the same substrate.

〔Effect of the invention〕

According to the method for forming a semiconductor thin film according to the present invention, ions are implanted into a part of polycrystalline silicon to make it amorphous, and solid phase growth from the interface is performed to form an extremely large grain boundary. Since less semiconductor layers are obtained in the
1. Because the process can be performed using a regular diffusion furnace, a large number of devices and multiple wafers can be processed simultaneously, improving processing efficiency and eliminating defects caused by thermal stress.
The heat dissipation pattern etc. are also disrespectful and β.

[Brief explanation of drawings]

Figures 1 to 5 are for explaining one embodiment of the present invention. Figure 1 is a schematic sectional view showing the state before processing, and Figure 2 is a schematic sectional view showing the state after ion implantation. , FIG. 3 is a schematic plan view showing only the polycrystalline silicon layer in FIG. 2 with salt removed, FIG. 4 is a schematic cross-sectional view showing the state after in-phase growth, and FIG. 5 is a schematic plan view showing the polycrystalline silicon layer in FIG. FIG. 6 is a schematic plan view showing only the layers taken out, and FIG. 6 is a schematic plan view showing main parts of another embodiment of the present invention. 1... Amorphous insulating substrate 2... Polycrystalline silicon layer 3
...Amorphous region 4...Solid phase growth region 1 town 1)
He Rong - Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] The method includes a step of forming polycrystalline silicon on a substrate, a step of implanting ions into at least a portion of this polycrystalline silicon to make it amorphous, and a step of growing crystals in this amorphous portion in an in-phase state. Formation force method for semiconductor thin films.