JPH0547660A - Solid growth method for semiconductor thin film - Google Patents

Abstract

PURPOSE:To shorten a forming time of an amorphous semiconductor layer having a low nucleus density and to obtain an SOI having excellent characteristics at a low temperature by heat treating an amorphous semiconductor film laminated on an insulating board to generate crystalline growing nuclei, then again heat treating it in a state that the density of the nuclei is reduced, and solid growing it. CONSTITUTION:An amoqhous silicon thin film 2 is deposited on an insulating board 1 under a condition having a low impurity concentration in a film, and further an amorphous silicon thin film 3 is deposited under a condition having a high impurity concentration. And, when it is heat treated at 600 deg.C in an N2 atmosphere, crystalline nuclei 4 are generated near a boundary between the surface and the amorphous silicon thin films 2 and 3. When Si ions are implanted in a region having high impurity concentration near the surface of the film in this state to be made amorphous, the density of the nuclei 4 is reduced, and an amorphous silicon layer 3' containing small amount of the impurity of the state that the nuclei partly remain is obtained. It is further heat treated at 600 deg.C in an N2 atmosphere in this state for about 24 hours to obtain a semiconductor layer having about 2.5mum of average crystalline grain size.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for forming a semiconductor thin film having large-sized crystal nuclei on an insulating substrate such as quartz and a thin film semiconductor device having an inverted stagger structure formed by using this method.

[0002]

2. Description of the Related Art A method of forming a silicon thin film having good crystallinity on an insulating substrate or an insulating film on a Si wafer is known as SOI technology. Among the SOI technologies, the so-called recrystallization method is a method in which a polycrystalline or amorphous material is once melted and then recrystallized, and a method of recrystallizing a crystal without raising it to a melting temperature. There is a solid phase growth method in which crystals are grown while promoting arraying. In the solid phase growth method, recrystallization can be performed at a low temperature of 600 ° C. or lower, which is excellent in terms of low temperature. In the solid-phase growth method, first, nuclei serving as a base point of crystal growth are generated, and then crystals grow around the nuclei. It is generally known that the activation energy for nucleation is smaller than the activation energy for solid phase growth. Therefore, the heat treatment at a lower temperature has a remarkable effect of lowering the nucleus generation density. By reducing the density of nucleation, a semiconductor film having a larger crystal grain size can be obtained. The average crystal grain size is inversely proportional to the 1/2 power of the nucleation density. After all, in order to obtain crystals with a large grain size, it is necessary to keep the nucleation density low. 550 ° C-600
Heat treatment at a low temperature of ℃ is preferable in that the density of nuclei formation is reduced as described above, but it is not practical because the time until the nuclei are formed (latency time) becomes extremely long. It is a drawback. On the other hand, JP-A-2-238
The technique of Japanese Patent No. 617 proposes a solid phase growth method by adopting a high temperature short time heat treatment process at 700 to 800 ° C., followed by a first annealing process and a second annealing process at a temperature lower than the first annealing process. ing. On the other hand, the present inventor previously disclosed, in Japanese Patent Application No. 3-14780, that amorphous semiconductor layers having different impurity concentrations are stacked on an insulating substrate, and nuclei for crystal growth are generated by thermal annealing, and then the nuclei density of the film surface is increased. We provide a method to remove the high temperature region by etching and perform solid phase growth again by thermal annealing.
Due to the necessity of an etching process and the contamination of the etching surface (remaining of C and F) by the etching gas (SF ₆ , CF ₄ , O ₂ etc.), the surface of the surface before the thermal annealing of the solid phase growth is performed. There was a need for labor such as performing a cleaning process. Further, it is necessary to add the film thickness of the semiconductor layer to be removed by etching to the film thickness required after the solid phase growth and deposit it on the substrate in advance.

[0003]

[Objective] The object of the present invention is to propose a new solid phase growth method, specifically, in the step of solid phase growing an amorphous silicon thin film deposited on an insulating substrate, A method for solving the drawback of requiring a long time (hundreds of hours) heat treatment described in 1., and further performing heat treatment in a state in which the density of nucleation is suppressed to a low level to perform solid phase growth of a silicon thin film having crystals with large grain size. Is to provide. Another object of the present invention is to provide a method which does not use an etching process as in Japanese Patent Application No. 3-14780.

[0004]

According to a first aspect of the present invention, (a) a step of sequentially depositing an amorphous semiconductor film having a low impurity concentration and an amorphous semiconductor film having a high impurity concentration on an insulating substrate; The amorphous semiconductor film is heat-treated to generate nuclei for crystal growth, and (c) ion-implantation is performed to a region of the film where the nuclei are formed, which has a high impurity concentration near the film surface. Solid phase of a semiconductor thin film, which comprises: a step of reducing the density of nuclei by solidification, and (d) a thermal annealing step of performing heat treatment again on the film having the reduced density of nuclei to perform solid phase growth. Regarding the growth method. Second of the present invention
Relates to a thin film semiconductor device having an inverted staggered structure, wherein a semiconductor thin film formed by the solid phase growth method according to claim 1 is used as a gate electrode, and a gate oxide film is formed by thermal oxidation of the semiconductor layer. .. The third aspect of the present invention is
A thin film semiconductor device having an inverted stagger structure according to claim 2, wherein the channel region is also a semiconductor thin film formed by the solid phase growth method according to claim 1.

When the impurity concentration is low, the standard is that the impurity concentration is usually 1 × 10 ¹⁶ to 1 × 10 ¹⁷ (atom / cc), and particularly preferably 1 × 10 ^{16 to} 5.
× 10 ¹⁶ (atom / cc) is included. When the impurity concentration is high, the standard is that the impurity concentration is usually 1 × 1.
It is a case where it is contained in an amount of 0 ²⁰ to 1 × 10 ²¹ (atom / cc), and particularly preferably 2 × 10 ^{20 to} 5 × 10 ²⁰ (atom / cc).
cc) If included.

Next, the present invention will be specifically described. First, as shown in FIG. 1A, an amorphous silicon thin film 2 is deposited on an insulating substrate 1 under the condition that the impurity concentration in the film is low. Here, the conditions for the LPCVD method and the plasma CVD method will be described. [] Shows a preferable range. (1) Example of LPCVD method Raw material gas Si ₂ H ₆ (purity 99.999%) Pressure 0.2 Torr [0.1 to 0.5 Torr] Substrate temperature 500 ° C [470 to 530 ° C] Film thickness 1500Å [1000 to 3000Å] ( 2) In case of plasma CVD method Raw material gas 10% SiH ₄ (Purity 99.999%) + H ₂ (Purity 99.9999
9%) Pressure 0.6 Torr [0.1 to 0.8 Torr] Substrate temperature 100 ℃ [70 to 150 ℃] RF power 30 W [20 to 100 W] Film thickness 1500 Å [1000 to 3000 Å] Amorphous under high impurity concentration conditions Quality thin silicon film 3
Deposit. In the case of the LPCVD method (1), PH ₃ is added to Si ₂ H ₆ at a flow rate ratio of about 1/10 ³ [1/10 ⁴ to 1/10 ³ ].
Deposition is performed by mixing (corresponding to the case of high concentration). Performing deposition by mixing the same degree of PH ₃ to SiH ₄ in plasma CVD method (2). In addition, in order to introduce C, N, O as impurities, CH ₄ , N ₂ O, CO ₂ , NH _3, etc. are mixed. The film thickness of 3 was 500 Å [300 to 700 Å].
FIG. 1 (b) shows the state of FIG. 1 (a) after being heat-treated in an N ₂ atmosphere at a temperature of 600 ° C. for 12 hours, and 4 is near the surface and the interface between the layers 2 and 3. It represents the crystal nuclei formed in. Impurities P, N, C, O, etc. in amorphous silicon have the effect of shortening the latent time until nucleation and increasing the nucleation rate, but since the layer 2 has a low concentration of these impurities, this After the heat treatment for about a time, almost no nucleation is observed in the film of No.2. Next, FIG. 1C shows a state in which Si ions are implanted in the vicinity of the film surface from the state of FIG. 1B to make it amorphous. Reference numeral 3'denotes an amorphous silicon layer having a small amount of impurities in a state where the crystal nuclei previously produced are partially left. Si ion implantation condition is 4
It is 0 KeV and 2 × 10 ¹⁵ cm ^-2 . Under this condition, it is amorphized to a depth of 500 to 700 Å from the surface. Approximately 2 at 600 ° C. in N ₂ atmosphere from the state shown in FIG.
After annealing for 4 hours, a semiconductor layer having a crystal grain size of about 2.5 μm was obtained. FIG. 2 is a graph showing the PH ₃ / SiH ₄ concentration dependence of the nucleation rate and the incubation time in the above specific example. Further, FIG. 3 shows a concrete example of the second and third aspects of the present invention. That is, after forming the large grain size Si layer 23 formed by the solid phase growth method of the present invention as a gate electrode, a thermal oxide film 27 is formed at a temperature of 900 ° C., and the solid phase growth of the present invention is further formed thereon. The channel region 24, the source region 26, and the drain region 25 are formed by repeatedly using the method.

[0007]

[Effect] The time required to generate low-density nuclei was greatly shortened. Polycrystalline silicon with large grain size was obtained under low nucleation density. It is possible to provide an SOI with excellent characteristics at low temperatures. Since the gate insulating film is formed from a silicon thin film having a large grain size, the insulating film is flattened and the characteristics of the silicon thin film formed thereon are further improved.

[Brief description of drawings]

1A to 1C show an example of a manufacturing process according to the first aspect of the present invention with reference to (a), (b), and (c).

FIG. 2 is a graph showing the PH ₃ / SiH ₄ concentration dependence of nucleation rate and latency in specific examples of the present invention, where Δ-Δ is the time from the start of annealing to the generation of nuclei, that is, the latency. .. indicates the rate at which nuclei are generated and corresponds to the nucleation rate.

FIG. 3 is an explanatory diagram showing an example of an inverted stagger type thin film semiconductor element of the present invention.

[Explanation of symbols]

1 Insulating substrate 2 Amorphous silicon thin film deposited under conditions of low impurity concentration 3 Amorphous silicon thin film deposited under conditions of high impurity concentration 3 ' Amorphous silicon thin film 4 Crystal nucleus 23 Gate electrode 24 Channel region 25 Drain region 26 Source region 27 Thermal oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/40 A 7738-4M 29/784 // H01L 21/265

Claims (3)

[Claims] 1. A step of sequentially depositing an amorphous semiconductor film having a low impurity concentration and an amorphous semiconductor film having a high impurity concentration on an insulating substrate, and (b) the stacked amorphous semiconductors. A thermal annealing process in which a film is heat-treated to generate nuclei for crystal growth, and (c) nuclei are formed by ion-implanting a region of the film in which the nuclei are generated near the film surface with a high impurity concentration to make it amorphous. And (d) a thermal annealing step of performing heat treatment again on the film having the reduced density of nuclei to perform solid phase growth, the solid phase growth method for a semiconductor thin film. 2. A thin film having an inverted staggered structure, wherein the semiconductor thin film formed by the solid phase growth method according to claim 1 is used as a gate electrode, and the gate oxide film is formed by thermal oxidation of the semiconductor layer. Semiconductor device. 3. A thin film semiconductor device having an inverted staggered structure according to claim 2, wherein the channel region is also a semiconductor thin film formed by the solid phase growth method according to claim 1.