KR100420409B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device to suppress the degradation of the hot carrier effect, GIDL and junction leakage characteristics due to thermally induced stress or mechanically induced stress during the manufacturing process of the semiconductor device. The present invention includes forming a capacitor on a semiconductor substrate on which a transistor is formed, rapidly thermally processing the semiconductor substrate including the capacitor, and thermally treating the rapid thermally treated semiconductor substrate at 600 ° C. to 800 ° C. do.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to relieve thermally or mechanically induced stress.

In general, various annealing techniques are used in a process of manufacturing integrated circuits using silicon. For example, the silicon substrate may be oxidized to SiO ₂ to form an insulating layer, or to form an etching mask and a gate oxide film for a transistor.

In addition, the heat treatment technology injects trivalent or pentavalent ions into the silicon substrate, and the implanted ions are rearranged from the invasive to substituted into the silicon crystal, thereby contributing to extra holes or electrons that may contribute to electrical conduction. It is also used as a means to generate).

In addition, heat treatment techniques are used for heat treatment of thin films formed by various methods and reflow of BPSG films, and heat treatment processes are used for manufacturing semiconductor devices for various other purposes. An apparatus commonly used in this heat treatment process is an electric furnace.

In recent years, however, as semiconductor devices have been increasingly integrated, there has been a tendency for heat treatment using Rapid Thermal Annealing (RTA) devices in order to reduce the overall thermal budget of the manufacturing process due to the reduction in device size.

Rapid heat treatment (RTA) is divided into two types according to the heating method, a lamp heating heat treatment apparatus using a halogen lamp or an arc lamp as a heat source, and a hot well heat treatment apparatus using a resistance heating heater.

Recently, as the thermal safety of the metal is recognized as an important problem due to the expansion of the application range of the metal wiring for the high efficiency of the transistor by the integration of the device, a reduced thermal budget is required. On the other hand, high temperature thermal processes are required to increase the use of high concentration layers and to improve contact resistance. Therefore, in many cases, the application range of rapid thermal treatment (RTA), which enables a short time process at high temperature, is gradually expanding.

1A to 1C are cross-sectional views of a manufacturing process of a semiconductor device according to the prior art.

As shown in FIG. 1A, a field oxide film 12 defining an active region and a field region of an element is formed in a predetermined portion of the semiconductor substrate 11. At this time, the field oxide film 12 is formed by etching the semiconductor substrate 11 to a predetermined depth to form a trench, and filling the trench with an insulating film. On the other hand, although the field oxide film 12 has been shown to be formed by a shallow trench isolation (STI) method, it may also be formed by a local oxide of silicon (LOCOS) method.

Subsequently, a gate insulating film 13 is formed on the active region of the semiconductor substrate 11 and polysilicon is deposited on the gate insulating film 13, and then a photosensitive film is coated on the polysilicon and patterned by exposure and development.

Subsequently, the polysilicon and gate insulating film 13 are selectively patterned using the patterned photosensitive film as a mask to form a laminated structure of the gate insulating film 13 and the gate electrode 14, and then the gate electrode 14 is used as a mask. Ion implantation of the low concentration impurity 15 into the surface of the semiconductor substrate 11 is performed.

As shown in FIG. 1B, an insulating film is deposited on the entire surface including the gate electrode 14 and etched to form sidewalls 16 contacting both sides of the gate electrode 14, and then the gate electrode 14 and the sidewalls ( Using the 16 as a mask, high concentration impurities 17 are implanted into the surface of the semiconductor substrate 11 below the sidewall 16.

As shown in FIG. 1C, a rapid heat treatment process for activating the low concentration impurity 15 and the high concentration impurity 17 is performed to form the source / drain region 17a of the LDD 15a structure.

In such a conventional technique, ion implantation is to apply energy to predetermined ions so that ions penetrate the surface of the semiconductor substrate and be positioned inside the semiconductor substrate, and in order to form a channel region at the voltage of the gate electrode, the atomic lattice of the semiconductor substrate Impurities located in between must be at the position of the atom. This change in the position of impurities is called activation, and activation of such impurities is caused by external energy and is usually performed by annealing process.

However, when the rapid thermal treatment (RTA) process is used to activate such impurities, stress (see FIG. 2), LDD ion implantation, and source / drain ion implantation due to the separation of the interface due to thermal expansion of the field oxide film and the semiconductor substrate There is a problem that causes crystal defects.

Referring to FIG. 2, stress is concentrated in the corner portion (A) of the gate electrode, the upper edge portion (B) of the field oxide film, and the lower edge portion (C) of the field oxide film after the rapid thermal treatment (RTA) process. The region B is included in the junction region doped with impurities, and thus has a great influence on the characteristics of the device.

In addition, when the lattice defects are distributed at the interface between the gate insulating film and the semiconductor substrate of the transistor and at the periphery of the junction, there is a problem that adversely affects device characteristics such as hot carrier degradation, GIDL, junction leakage, and the like.

Rapid thermal treatment (RTA), on the other hand, is known to cause lattice defects such as dislocations due to rapid temperature changes and temperature gradients in the wafer.

In addition, since the LDD structure, which is a low concentration impurity region on the drain region side, overlaps with the gate electrode after the rapid thermal treatment (RTA), the short channel effect (SCE) in which the effective channel length is reduced is increased, Due to the short distance of the drain region, GIDL (Gate Induced Drain Leakage) may occur, resulting in deterioration of device characteristics.

Due to the short channel effect described above, the electric field in the depletion layer in the drain region of the channel is increased, so that electrons are accelerated at high speed and collide with atoms, causing an avalanche phenomenon in which electrons accumulate, and the generated high energy is absorbed. Some of the high-speed electrons have a hot carrier effect that enters and is trapped in the gate insulating film and changes the threshold voltage of the transistor, which shortens the lifetime of the device.

There is a need for a method for manufacturing a more reliable semiconductor device by suppressing degradation of each device in a circuit due to the hot carrier effect as described above, and also maintaining data of DRAM generated by the above-mentioned device degradation. There is a need for a method that can improve the reduction of the date retention time, ie the refresh time tREF.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and is a method of manufacturing a semiconductor device suitable for suppressing a decrease in hot carrier effect, GIDL and junction leakage characteristics due to thermally induced stress or mechanically induced stress. The purpose is to provide.

Further, another object of the present invention is to provide a method of manufacturing a semiconductor device having a memory device to prevent a reduction in data retention time.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a view showing a stress concentration in accordance with the rapid thermal treatment process of the prior art,

3 is a flowchart of a heat treatment process of a semiconductor device according to the present invention;

4A to 4C are cross-sectional views illustrating a method for releasing stress in a semiconductor device according to a first embodiment of the present invention;

5a is a view showing that the amount of stress increases when the heat treatment temperature rises with the change of stress according to the temperature of the rapid heat treatment process,

Figure 5b is a view showing the degree of relaxation of stress after heat treatment;

6 is a diagram illustrating leakage current characteristics according to a voltage Vg applied to a gate electrode;

FIG. 7 is a diagram illustrating a variation in threshold voltage Vt before and after hot carrier stress; FIG.

8 is a view comparing GIDL characteristics,

9A to 9B are cross-sectional views illustrating a method for releasing stress in a semiconductor device according to a second embodiment of the present invention;

10 is a view for explaining a stress relaxation method of a semiconductor device according to a third embodiment of the present invention;

11 is a diagram showing capacitance and contact resistance according to rapid heat treatment temperature;

12 is a view comparing data retention time.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 field oxide film

23: gate insulating film 24: gate electrode

25a: LDD 26: side wall

27a: source / drain area

A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a capacitor on a semiconductor substrate on which a transistor is formed, rapidly heat treating the semiconductor substrate including the capacitor, and the rapid thermally processed semiconductor substrate It characterized in that it comprises a heat treatment step.

In addition, the method of manufacturing a semiconductor device of the present invention includes the steps of forming a capacitor having a ferroelectric film on a semiconductor substrate on which a transistor is formed, and subjecting the semiconductor substrate including the capacitor to thermal processing.

In addition, in the method of manufacturing a semiconductor device of the present invention, forming a gate insulating film and a gate electrode on a semiconductor substrate, implanting impurities into the semiconductor substrate using the gate electrode as a mask, and performing the impurity using rapid thermal treatment. Forming a source / drain by activating the semiconductor substrate; and heat-treating the semiconductor substrate on which the source / drain is formed.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a heat treatment flowchart of a semiconductor device according to the present invention, in which a semiconductor device subjected to a plurality of rapid heat treatment (RTA-1 to RTA-N) processes is subjected to a thermal treatment.

The rapid heat treatment step is applied to a source / drain step, a field oxide film step, a silicide step, a contact step, a reflow step of an interlayer insulating film, a crystallization step of a capacitor dielectric film, and the like.

As described above, during the rapid heat treatment process, the semiconductor device is degraded due to thermal stress, and the mechanical device is subjected to mechanical mechanical polishing (CMP) during the manufacturing process of the semiconductor device in addition to the rapid heat treatment process. Stress may be induced to lower the reliability of the semiconductor device.

Accordingly, embodiments of the present invention introduce a thermal treatment process to mitigate the thermal and mechanical stresses described above.

4A through 4C are cross-sectional views illustrating a method for releasing stress in a semiconductor device according to a first embodiment of the present invention, and illustrating a method for mitigating thermal stress induced during transistor manufacturing.

As shown in FIG. 4A, a field oxide film 22 defining an active region and a field region of an element is formed in a predetermined portion of the semiconductor substrate 21. At this time, the field oxide film 22 is formed by etching the semiconductor substrate 21 to a predetermined depth to form a trench, and filling the trench with an insulating film. On the other hand, although the field oxide film 22 has been shown to be formed by the STI method, it can also be formed by the LOCOS method.

Subsequently, a gate insulating film 23 is formed on the active region of the semiconductor substrate 21 and polysilicon is deposited on the gate insulating film 23. Then, a photosensitive film is coated on the polysilicon and patterned by exposure and development.

Subsequently, the polysilicon and gate insulating film 23 are selectively patterned using the patterned photosensitive film as a mask to form a laminated structure of the gate insulating film 23 and the gate electrode 24, and then the gate electrode 24 is used as a mask. Ion implantation of the low concentration impurity 25 into the surface of the semiconductor substrate 21 is performed.

Next, an insulating film is deposited on the entire structure including the gate electrode 24 and etched to form a spacer 26 in contact with both sides of the gate electrode 24, and then the gate electrode 24 and the spacer 26 are masked. The high concentration impurity 27 is ion-implanted into the surface of the semiconductor substrate 21 under the spacer 26 by using the ion. Typically, the high concentration impurity 27 is ion implanted deeper than the low concentration impurity 25.

As shown in FIG. 4B, a high temperature (800 ° C. or higher) rapid thermal treatment (RTA)) process is performed to activate the low concentration impurity 25 and the high concentration impurity 27. At this time, a source / drain region 27a having an LDD 25a structure is formed, and the LDD 25a overlaps a corner portion of the gate electrode with a predetermined width.

As shown in FIG. 4C, a source / drain region electrically connected to the LDD 25a and the LDD 25a formed by overlapping a predetermined width at a corner portion of the gate electrode 24 by the rapid thermal treatment (RTA) process described above. The semiconductor substrate 21 on which the 27a is formed is subjected to heat treatment at 600 占 폚 to 800 占 폚.

Although not shown in the drawings, a metal wiring for connecting the source / drain regions 27a with external devices is formed in a subsequent process.

The thermal treatment is thermally induced in the corner portion A ″ of the gate electrode 24, the upper edge portion B ″ of the field oxide film, and the lower edge portion C ″ of the field oxide film by a rapid thermal treatment (RTA) process. Reduce stress (see FIG. 5B).

FIG. 5A is a diagram illustrating an increase in the amount of stress when the heat treatment temperature is increased due to the change of stress according to the temperature of the rapid thermal treatment (RTA) process. As shown in FIG. 3, the corner portion A ′ of the gate electrode 24 is increased. It can be seen that the amount of stress is increased in the upper edge portion B 'of the field oxide film and the lower edge portion C' of the field oxide film.

FIG. 5B is a diagram illustrating a degree of stress relaxation according to an exemplary embodiment of the present invention. As a result of the thermal treatment after the rapid thermal treatment (RTA) process, the gate electrode has a corner portion A ″ of about 40% as compared to FIG. 5B. A reduction effect can be obtained, and the upper edge portion (B ") of the field oxide film can obtain a reduction effect of about 60%, and the amount of thermal stress induced in A" and B "included in the junction region as a whole is 40. It can be seen that the% to 60% decrease.

FIG. 6 is a graph illustrating leakage current characteristics according to a voltage Vg applied to a gate electrode. FIG. 6 is a rapid heat treatment (RTA) process, a mixed heat treatment of rapid heat treatment (RTA) and a furnace treatment, and a leakage current after heat treatment only of the furnace treatment. It is shown.

Referring to FIG. 6, it can be seen that the leakage current is reduced in the case where only the heat treatment is performed than in the case of the rapid heat treatment (RTA) and the rapid heat treatment (RTA) and the heat treatment.

7 is a graph illustrating changes in threshold voltage Vt before and after hot carrier stress.

Referring to FIG. 7, it can be seen that the cumulative probability of the hot carrier decreases when the subsequent heat treatment is performed rather than immediately after the completion of the high temperature rapid heat treatment (RTA) process.

8 is a graph comparing the GIDL characteristics, and it can be seen that the GIDL characteristics are improved when the subsequent heat treatment is performed, rather than immediately after the completion of all the high temperature rapid heat treatment (RTA) processes. That is, the leakage current of the drain region induced in the gate electrode is reduced.

In the first embodiment described above, the hot carrier effect and the GIDL characteristics can be improved by thermal treatment after rapid thermal treatment (RTA) to alleviate thermal stress induced by the rapid thermal treatment (RTA) process during transistor manufacturing.

9A to 9B are cross-sectional views illustrating a method for releasing stress in a semiconductor device according to a second embodiment of the present invention, and illustrating a semiconductor device having a capacitor.

As shown in FIG. 9A, a field oxide film 32 for isolation between devices is formed on the semiconductor substrate 31 using an STI or LOCOS process, and the gate insulating film 33 and the word line are formed on the semiconductor substrate 31. After forming 34, low concentration impurities are implanted into the semiconductor substrate 31 on both sides of the word line 34. As shown in FIG.

Next, after the insulating film is deposited on the entire surface including the word line 34, the entire surface is etched to form sidewalls 35, which are in contact with both sides of the wordline 34, and the sidewalls 35 and the wordline 34 are masked. Thus, a high concentration of impurities are implanted into the semiconductor substrate 31.

Next, a low concentration impurity and a high concentration impurity are activated by a rapid thermal treatment (RTA) process to form a source / drain region 37 electrically connected to the LDD region 36 and the LDD region 36. At this time, the LDD region 36 overlaps a corner of the word line 34 by a predetermined width.

Next, after depositing and planarizing the first interlayer insulating film 38 on the entire surface of the semiconductor substrate 31 including the transistor formed by the above-described process, the first interlayer insulating film 38 is etched to form a source / drain region 37. ) To form a contact hole exposing one side.

Subsequently, a conductive film for forming a bit line is deposited on the entire surface including the contact hole and then patterned to form a bit line 39 connected to one side of the source / drain region 37.

After the deposition and planarization of the second interlayer insulating film 40 on the first interlayer insulating film 38 including the bit line 39, the lower electrode 41 is formed on a predetermined surface of the second interlayer insulating film 40. A stacked capacitor consisting of a dielectric film 42 and an upper electrode 43 is formed.

Here, the lower electrode 41 and the upper electrode 43 are polysilicon doped with impurities, such as doped polysilicon doped with a high concentration of P-type impurities such as phosphorous (P) or Pt, Ir, IrO _{x , Ru, RuO x, Rh,} RhO x, CaRuO 3, SrRuO 3, BaRuO 3, BaSrRuO 3, CaIrO 3, SrIrO 3, BaIrO 3, (La, Sr) CoO 3, Cu, Al, Ta, Mo, W, Au, Ag, WSi ₂ , TiSi ₂ , MoSi _x (x = 0.3-2), CoSi _x (x = 1-2), NbSi _x (x = 0.3-2), TaSi _x (x = 1-2), A metal electrode made of at least one or a combination of two or more selected from the group consisting of TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN, IrTiN, TaSiN and TaAlN is used. In addition, as a dielectric film, both a low dielectric film of SiO ₂ , NO (Nitride Oxide) and a high dielectric film such as Ta ₂ O ₅ , TaON, and Al ₂ O ₃ may be used.

Meanwhile, when the capacitor is formed, the upper electrode 43 is etched first, and then the dielectric layer 42 and the lower electrode 41 are sequentially etched, or the upper electrode 43, the dielectric layer 42, and the lower electrode 41 are sequentially After etching, the upper electrode 43 may be etched again.

Next, a rapid thermal treatment (RTA) of the semiconductor substrate on which the capacitor formation is completed is performed at a high temperature of 800 ° C to 1000 ° C. This rapid thermal treatment not only reduces the contact resistance of the bit line 39 and the source / drain region 37a. Rather, the rapid thermal treatment increases the capacitance of the capacitor by compensating the etch loss after etching the electrode and the dielectric film to form the capacitor (see FIG. 11). In particular, when using polysilicon doped with a high concentration of impurities as an electrode, it is possible to increase the capacitance by reducing the depletion layer due to activation of the impurities.

Meanwhile, referring to FIG. 11, it can be seen that as the heat treatment temperature of the rapid thermal treatment (RTA) process increases, the capacitance increases and the contact resistances of the bit lines and the source / drain regions decrease. As will be described later, the range of the heat treatment temperature of the rapid thermal treatment (RTA) process is applied only when the above-described dielectric film is used as the dielectric film of the capacitor, and when the ferroelectric film is used, the structure of the ferroelectric film is destroyed due to the high temperature heat treatment, thereby deteriorating the ferroelectric properties. Therefore, the range is limited.

As shown in FIG. 9B, the thermal treatment is performed at 600 ° C. to 800 ° C. to relieve thermal stress induced by the above-described rapid heat treatment (RTA) process.

As described above, the thermal treatment after rapid thermal treatment can reduce the stress induced during a large number of rapid thermal treatments, thereby improving the characteristics of transistors such as junction leakage and improving the data retention time of semiconductor devices, particularly DRAM. (See FIG. 12).

Referring to FIG. 12, it can be seen that the data retention time is improved by about 120% when the thermal treatment is performed after the high temperature rapid heat treatment rather than after the high temperature rapid heat treatment (RTA).

FIG. 10 is a diagram illustrating a stress relaxation method of a semiconductor device according to a third embodiment of the present invention, and illustrates a case in which a ferroelectric film is used as a dielectric film of a capacitor.

Referring to FIG. 10, a field oxide film 32 for isolation between devices is formed on a semiconductor substrate 31 using an STI or LOCOS process, and a gate insulating film 33 and a word line 34 are formed on the semiconductor substrate 31. ), Low concentration impurities are implanted into the semiconductor substrate 31 on both sides of the word line 34.

Next, after the insulating film is deposited on the entire surface including the word line 34, the entire surface is etched to form sidewalls 35, which are in contact with both sides of the wordline 34, and the sidewalls 35 and the wordline 34 are masked. Thus, a high concentration of impurities are implanted into the semiconductor substrate 31.

Next, a low concentration impurity and a high concentration impurity are activated by a rapid thermal treatment (RTA) process to form a source / drain region 37 electrically connected to the LDD region 36 and the LDD region 36. At this time, the LDD region 36 overlaps a corner of the word line 34 by a predetermined width.

Next, after depositing and planarizing the first interlayer insulating film 38 on the entire surface of the semiconductor substrate 31 including the transistor formed by the above-described process, the first interlayer insulating film 38 is etched to etch the source / drain regions 37a. ) To form a contact hole exposing one side.

Subsequently, a conductive film for forming a bit line is deposited on the entire surface including the contact hole and then patterned to form a bit line 39 connected to one side of the source / drain region 37a.

After the deposition and planarization of the second interlayer insulating film 40 on the first interlayer insulating film 38 including the bit line 39, the lower electrode 41 is formed on a predetermined surface of the second interlayer insulating film 40. A stacked capacitor consisting of a dielectric film 42 and an upper electrode 43 is formed.

Here, the dough has a lower electrode 41 and upper electrode 43 peudeu polysilicon, Pt, Ir, IrO _x, Ru, RuO _x, Rh, RhO _x, CaRuO _3, SrRuO _3, BaRuO _3, BaSrRuO _3, CaIrO ₃ , SrIrO ₃ , BaIrO ₃ , (La, Sr) CoO ₃ , Cu, Al, Ta, Mo, W, Au, Ag, WSi ₂ , TiSi ₂ , MoSi _x (x = 0.3 to 2), CoSi _x (x = 1-2), NbSi _x (x = 0.3-2), TaSi _x (x = 1-2), TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN, IrTiN, A metal electrode made of at least one or a combination of two or more selected from the group consisting of TaSiN and TaAlN is used.

The dielectric film 42 includes STO (SrTiO ₃ ), BTO (BaTiO ₃ ), SBTN ((Sr, Bi) (Ta, Nb) ₂ O ₉ ), SBT ((Sr, Bi) Ta ₂ O ₉ ), BLT _{((Bi, La) Ti 3} O 12), BT (BaTiO 3), use the ferroelectric film containing the _{ST (SrTiO 3), PT (} PbTiO 3).

Meanwhile, when the capacitor is formed, the upper electrode 43 is etched first, and then the dielectric layer 42 and the lower electrode 41 are sequentially etched, or the upper electrode 43, the dielectric layer 42, and the lower electrode 41 are sequentially After etching, the upper electrode 43 may be etched again.

At least one rapid heat treatment process will be performed before proceeding with the above-described process, and the semiconductor substrate 31 on which the capacitor is formed is subjected to heat treatment at 600 ° C. to 800 ° C., wherein the electrode for forming the capacitor is subjected to the heat treatment. In addition to compensating the etch loss after etching the dielectric layer, in particular, in the case of using polysilicon doped with a high concentration of impurities as an electrode, the depletion layer due to activation of impurities is reduced, thereby increasing the capacitance of the capacitor.

In addition, it is possible to improve the characteristics of the transistor by reducing the thermal stress induced in the junction layer (source / drain region) similarly to the first embodiment.

In the case of a semiconductor device using a ferroelectric film, only the heat treatment is performed without rapid heat treatment. The rapid heat treatment has a problem that the temperature changes rapidly and the structure of the ferroelectric film is destroyed. This is because the ferroelectric properties of the ferroelectric film can be secured.

Meanwhile, in the second and third embodiments, stacked capacitors are exemplified, but are applicable to various types of capacitors including concave and cylindrical, and CUB (Capacitor Over Bitline) structure. It is also applicable to semiconductor devices having a capacitor under bitline structure. That is, the heat treatment process is performed before the metal wiring process for connecting the upper electrode (or plate line) of the capacitor to the external element.

In addition, the present invention can be applied to a CMOS process in which a capacitor is formed only in a cell region and a bit line is formed in a peripheral region. In this case, the bit line is formed in the peripheral region. After the heat treatment (800 ° C. to 1000 ° C.), the contact resistance between the bit line and the source / drain regions may be reduced to achieve high speed DRAM operation.

The heat treatment process may be performed immediately after the capacitor is manufactured, but may be performed after the capacitor manufacturing process, before any metal wiring process, that is, after the last rapid heat treatment process of the semiconductor device manufacturing process.

The stress relaxation method of the semiconductor device as described above is not limited only to rapid thermal treatment, and even if mechanical stress is induced by chemical mechanical polishing (CMP), the thermal stress treatment may be performed by a subsequent process to reduce mechanical stress. .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has the effect of increasing the utilization of the rapid heat treatment process by relieving thermal stress which is a disadvantage of the rapid heat treatment (RTA) by heat treatment after the rapid heat treatment process.

In addition, by reducing the thermally induced stress and mechanical stress to reduce the grid defect and the probability of trap generation, it is possible to improve the reliability of the device by improving the hot carrier effect, GIDL, leakage current characteristics.

In addition, the yield of the semiconductor device can be increased by drastically improving the data retention time of the DRAM.

Claims (13)

delete delete delete delete Forming a capacitor on the semiconductor substrate on which the transistor is formed; Rapid thermal treatment of the semiconductor substrate including the capacitor; And Thermally treating the rapidly thermally processed semiconductor substrate; Method of manufacturing a semiconductor device comprising a. The method of claim 5, wherein The rapid heat treatment is a manufacturing method of a semiconductor device, characterized in that at a temperature of 800 ℃ to 1000 ℃. The method of claim 5, wherein The heat treatment step is a method of manufacturing a semiconductor device, characterized in that at a temperature of 600 ℃ to 800 ℃. The method of claim 5, wherein Forming the capacitor, Sequentially forming a first conductive film, a dielectric film, and a second conductive film on the semiconductor substrate; Selectively patterning the second conductive layer, the dielectric layer, and the first conductive layer Method for manufacturing a semiconductor device comprising a. The method of claim 8, The dielectric film includes at least one selected from SiO ₂ , NO, Ta ₂ O ₅ , TaON, and Al ₂ O ₃ , or a combination thereof. The method of claim 8, Wherein the first and second conductive films comprise at least one selected from the group consisting of polysilicon, a metal film and a metal oxide film or a combination thereof. Forming a capacitor having a ferroelectric film on the semiconductor substrate on which the transistor is formed; And Thermally treating the semiconductor substrate including the capacitor Method of manufacturing a semiconductor device comprising a. The method of claim 11, The heat treatment step is a method of manufacturing a semiconductor device, characterized in that at a temperature of 600 ℃ to 800 ℃. The method of claim 11, The ferroelectric film may include STO (SrTiO ₃ ), BTO (BaTiO ₃ ), SBTN ((Sr, Bi) (Ta, Nb) ₂ O ₉ ), SBT ((Sr, Bi) Ta ₂ O ₉ ), BLT ((Bi, _{La) Ti 3 O 12),} BT (BaTiO 3), ST (SrTiO 3) and a method of manufacturing a semiconductor device according to at least one, or characterized in that it comprises a film combination thereof is selected from the group consisting of PT (PbTiO _3).