KR100688059B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device suitable for improving the characteristics of the device by reducing the contact resistance between the gate electrode and the bit line, the semiconductor device manufacturing method of the present invention is divided into a cell region and a peripheral circuit region Forming a plurality of gate patterns having metal silicide gate electrodes on the semiconductor substrate; Forming a first interlayer insulating film on the entire surface including the gate pattern; Forming a landing plug in the cell region so as to contact the semiconductor substrate through the first interlayer insulating film; Forming a second interlayer insulating film on an entire surface including the first interlayer insulating film and the landing plug; Selectively etching the second interlayer dielectric layer in the cell region to form a first open portion exposing the landing plug; Selectively etching the second interlayer dielectric layer and the first interlayer dielectric layer in the peripheral circuit region to form a second open portion exposing the semiconductor substrate; Forming a first barrier metal on the second interlayer insulating layer on which the first and second open portions are formed; Forming metal silicide in a region in contact with the landing plug in the first open portion and in a region in contact with the semiconductor substrate in the second open portion; Removing the first barrier metal; Selectively etching the second interlayer dielectric layer so as to expose the gate pattern of the peripheral circuit region; Removing a hard mask on the exposed gate pattern; Forming a second barrier metal on the gate pattern from which the second interlayer insulating layer, the metal silicide layer, and the hard mask are removed; And forming a conductive film on the second barrier metal.

Bitline, Contact Resistor, BLC1, BLC2, Barrier Metal

Description

 Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a graph illustrating resistance characteristics between bit line contacts / gates according to gate line widths.

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2 is a graph illustrating resistance characteristics between bit line contacts / gates according to a material formed on a gate;

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

41 semiconductor substrate 42 device isolation film

43 polysilicon film 44 metal silicide

45 gate hard mask 46 gate spacer

47: first interlayer insulating film 48: landing plug

49: second interlayer insulating film 50: titanium film

51: titanium silicide 52: titanium nitride film

53: bit line conductive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming bit line contacts in a semiconductor device.

Among the semiconductor memory devices, a DRAM (Dynmic Random Access Memory) and the like are largely divided into, for example, a cell region including a plurality of unit cells composed of 1T1C (one transistor and one capacitor) and a peripheral region including other unit elements.

For example, a bit line is a line connected to the source side of a cell transistor to actually transmit data. On the cell region side, a bit line contact and a cell line plug contacting a junction region for electrical connection of the bit line are performed. In terms of the peripheral area, which includes a bitline sense amplifier for sensing and amplifying the cell data transmitted through the bitline, the gate electrode and the bitline of the peripheral circuit transistor are connected for the electrical connection between the bitline sense amplifier and the bitline. You need a liver contact.

Meanwhile, the contact between the contact plug and the bit line contacted to the source / drain junction region on the side of the word line in the cell region is called BLC1, and the contact between the gate electrode and the bit line of the bit line sense amplifier in the peripheral region is referred to as BLC2.

As such, when the bit line is contacted to the silicon substrate, the polysilicon plug, and the gate electrode in the junction region, a barrier metal titanium silicide TiSi ₂ ) is formed to lower the contact resistance. In order to form such a titanium silicide, Ti / TiN is formed of a bit line barrier metal, and titanium silicide is formed by rapid heat treatment (RTP). In the case of the thus formed titanium silicide, there is a possibility of affecting the bit line contact resistance by thermal in the subsequent process.

Recently, the annealing temperature was increased after the formation of the lower electrode in order to improve the leakage characteristic of the metal-inslator-metal (MIM) capacitor. Increasing the annealing temperature has the effect of reducing the leakage characteristics of the capacitor, but resulted in an increase in the capacitor line bit line and gate resistance. In the existing paper, it can be seen that in the high temperature thermal process, titanium silicide is formed in the lower poly region through the grain boundary of tungsten silicide as the gate electrode, which seems to increase the contact resistance. (Reference: Reaction of Ti with WSi ₂ -J. Appl. Phys. 82 (12), 15 December 1997)

On the other hand, in the case of the contact resistance between the bit line and the gate electrode, it has been confirmed that the gate contact resistance rapidly increases when the device becomes extremely small and falls below a specific contact size.
1 is a graph illustrating resistance characteristics between bit line contacts and gates according to gate line widths. As the contact size decreases, the contact resistance between the bit line contact and the gate gradually increases and rapidly increases when the contact size becomes smaller than a certain size. It can be seen that.

FIG. 2 is a graph illustrating contact resistance characteristics between a bit line and a gate electrode. When the conductive titanium nitride layer is directly bonded to the gate electrode and the bit line, not the titanium silicide, the contact resistance between the bit line and the gate electrode is uniform. It can be seen that it has a low value.

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The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for improving the characteristics of the device by reducing the contact resistance between the gate electrode and the bit line.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns having a metal silicide gate electrode on a semiconductor substrate divided into a cell region and a peripheral circuit region; Forming a first interlayer insulating film on the entire surface including the gate pattern; Forming a landing plug in the cell region so as to contact the semiconductor substrate through the first interlayer insulating film; Forming a second interlayer insulating film on an entire surface including the first interlayer insulating film and the landing plug; Selectively etching the second interlayer dielectric layer in the cell region to form a first open portion exposing the landing plug; Selectively etching the second interlayer dielectric layer and the first interlayer dielectric layer in the peripheral circuit region to form a second open portion exposing the semiconductor substrate; Forming a first barrier metal on the second interlayer insulating layer on which the first and second open portions are formed; Forming metal silicide in a region in contact with the landing plug in the first open portion and in a region in contact with the semiconductor substrate in the second open portion; Removing the first barrier metal; Selectively etching the second interlayer dielectric layer so as to expose the gate pattern of the peripheral circuit region; Removing a hard mask on the exposed gate pattern; Forming a second barrier metal on the gate pattern from which the second interlayer insulating layer, the metal silicide layer, and the hard mask are removed; And forming a conductive film on the second barrier metal.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, an isolation layer 42 and a well (not shown) are formed on a semiconductor substrate 41 having a cell region and a peripheral circuit region separated by a shallow trench isolation (STI) method. On the other hand, the semiconductor substrate 41 is a normal silicon substrate.

Subsequently, a gate oxide film (not shown) is formed on the semiconductor substrate 41, the conductive films 43 and 44 for gate electrodes are laminated on the gate oxide film, and the conductive films 43 and 44 for gate electrodes are formed. After depositing the gate hard mask 45 on, a mask pattern for forming a gate pattern is formed through a photolithography process.

Subsequently, the gate patterns of the gate hard mask 45 and the gate electrodes 43 and 44 are etched by etching the conductive films 43 and 44 for the gate electrode and the gate hard mask 45 using the mask pattern as an etch mask. To form.

On the other hand, as the conductive film for the gate electrode, a metal silicide / polysilicon structure, for example, tungsten silicide (WSi) is used, and the gate hard mask 45 includes an insulating film of a nitride film series or an oxide film series.

Subsequently, an insulating film is deposited in the form of a nitride or oxide film alone or in combination along the profile in which the gate pattern is formed, and then dry etching is performed to form sidewall spacers 46 on the sidewalls of the gate pattern. The sidewall spacers 46 are intended to prevent the gate pattern from being attacked in a subsequent etching process.

Subsequently, an ion implantation process is performed in the peripheral circuit region to dope an N-type impurity into the semiconductor substrate 41 to be aligned with the side of the gate pattern, and then the doped impurities are diffused through heat treatment to form a source / drain region of the NMOS transistor ( Not shown).

In the same manner, an ion implantation process is performed to dope P-type impurities into the semiconductor substrate 41 to be aligned with the side of the gate pattern, and then the doped impurities are diffused through heat treatment to thereby source / drain regions of the PMOS transistor (not shown). ).

Meanwhile, in the case of the peripheral circuit region, the ion / drain is implanted twice before forming the spacer so that the source / drain has a lightly doped drain (LDD) structure, and thus the detailed process is omitted.

Subsequently, a first interlayer insulating film 47 is formed on the entire surface of the resultant product.

In this case, the first interlayer insulating film 47 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho). -Silicate film, HDP (High Density Plasma) oxide film, SOG (Spin On Glass) film or APL (Advanced Planarization Layer) film, etc. are used. In addition to oxide film, low dielectric constant film of inorganic or organic type can be used.

Subsequently, in order to secure a margin in a subsequent photolithography process, the upper portion of the first interlayer insulating film 47 is planarized by performing chemical mechanical polishing (CMP) or etch back process.

Next, a mask pattern (not shown) for forming a cell contact is formed on the planarized first interlayer insulating layer 47, and the first interlayer insulating layer 47 is etched using the mask pattern as an etch mask to form a gate pattern in the cell region. After exposing the substrate therebetween, the mask pattern is removed, a conductive film for forming a plug, for example, a polysilicon film is deposited on the entire surface, and a planarization process is performed on the target to which the gate hard mask 45 is exposed. To form.

Subsequently, a second interlayer insulating film 49 is deposited on the landing plug 48 and the first interlayer insulating film 47, and the second interlayer insulating film 49 is planarized.

Next, the substrate of the first opening portion and the N-type impurity diffusion region exposing the landing plug 48, that is, the region where the bit line contact BLC1 is to be formed in the cell region, that is, the second and first interlayer insulating layers are selectively etched, is removed. A second open portion for exposing is formed.

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As shown in FIG. 3B, the titanium film 50 for the barrier metal is deposited along the profile of the result of the bit line contact etching process. In addition to the titanium film 50, the barrier metal material layer may include a structure including a single or a laminated film of a titanium film, a titanium nitride film, and a titanium silicide film.

As illustrated in FIG. 3C, a rapid heat treatment is performed on the front surface of the resultant at a temperature of 700 ° C. to 900 ° C. to form titanium silicide 51 in an upper portion of the landing plug 48 of the cell region and an open bit line contact region of the peripheral circuit region. ).

As shown in FIG. 3D, dry cleaning is performed to remove the titanium film 50 except for the unsilicided titanium silicide 51.

As shown in FIG. 3E, a third open portion in which the metal silicide is exposed is formed by a mask and an etching process. That is, a third open portion is formed by etching the second interlayer insulating layer 49 and the gate hard mask 45 in the peripheral circuit region.

As shown in FIG. 3F, a titanium nitride film 52 is deposited along the profile of the result. Here, not only the titanium nitride film 52 but also a titanium film may be used, or may be used as a laminated film thereof.
Then, a tungsten film is deposited on the entire surface of the resultant with the bit line conductive film 53.

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As described above, the present invention forms a titanium silicide on the polysilicon landing plug and a silicon substrate (bonding region) when forming the barrier metal for the bit line contact, and forms a titanium nitride film thereon, while forming a titanium silicide on the metal silicide gate electrode. The titanium nitride film can be directly formed without a structure, thereby improving contact resistance between the metal silicide gate electrode and the bit line, even with high integration and subsequent high temperature annealing.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the above-described present invention, there is no increase in contact resistance between the bit line and the gate electrode during the rapid heat treatment process, so that the thermal process temperature of the MIM capacitor annealing process can be increased, thereby reducing the leakage of the capacitor. .

In addition, since the titanium nitride film is directly bonded on the gate electrode, the bit line contact resistance is uniformly reduced.

In addition, since there is no barrier metal titanium film on the side of the bit line contact on the gate electrode, there is a contact increase effect, thereby reducing the contact resistance between the bit line and the gate electrode.

Claims (6)

Forming a plurality of gate patterns having metal silicide gate electrodes on a semiconductor substrate divided into a cell region and a peripheral circuit region; Forming a first interlayer insulating film on the entire surface including the gate pattern; Forming a landing plug in the cell region so as to contact the semiconductor substrate through the first interlayer insulating film; Forming a second interlayer insulating film on an entire surface including the first interlayer insulating film and the landing plug; Selectively etching the second interlayer dielectric layer in the cell region to form a first open portion exposing the landing plug; Selectively etching the second interlayer dielectric layer and the first interlayer dielectric layer in the peripheral circuit region to form a second open portion exposing the semiconductor substrate; Forming a first barrier metal on the second interlayer insulating layer on which the first and second open portions are formed; Forming metal silicide in a region in contact with the landing plug in the first open portion and in a region in contact with the semiconductor substrate in the second open portion; Removing the first barrier metal; Selectively etching the second interlayer dielectric layer so as to expose the gate pattern of the peripheral circuit region; Removing a hard mask on the exposed gate pattern; Forming a second barrier metal on the gate pattern from which the second interlayer insulating layer, the metal silicide layer, and the hard mask are removed; And Forming a conductive film on the second barrier metal Semiconductor device manufacturing method comprising a. The method of claim 1, The first barrier metal is a semiconductor device manufacturing method consisting of a single or a laminated film of titanium film, titanium nitride film and titanium silicide film. The method of claim 1, Forming the metal silicide, A method of manufacturing a semiconductor device, which is formed by performing a rapid heat treatment after forming the first barrier metal. The method of claim 1, Removing the first barrier metal, A semiconductor device manufacturing method performed by dry cleaning. The method of claim 1, The first barrier metal uses a titanium film, and the second barrier metal uses a titanium nitride film. The method of claim 1, The second barrier metal is a semiconductor device manufacturing method of forming a single film or a laminated film of a titanium film or titanium nitride film.

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