KR20070001419A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to reduce bit line contact resistance by contacting barrier metals to a gate electrode. Plural gate patterns are formed on a semiconductor substrate(41) divided as a cell region and a peripheral region. An impurity diffusion region aligned to a side of each gate pattern is formed on the peripheral region. A first interlayer dielectric(47) is formed on the whole surface including the gate pattern. A plug is contacted to the semiconductor substrate by passing through the first interlayer dielectric on the cell region. The first interlayer dielectric and an upper portion of the plug are planarized. A second interlayer dielectric is formed on the whole surface including the first interlayer dielectric and the plug. The second interlayer dielectric of the cell region is selectively etched to form a first open unit exposing the upper portion of the plug. The second interlayer dielectric and the first interlayer dielectric of the peripheral region are selectively etched to form a second open unit exposing the impurity diffusion region. A first barrier metal is formed along a profile of the resultant structure where the open unit is formed. Silicide(51) is formed on the first and second open units. A first barrier metal except for the silicide is removed. The second interlayer dielectric is selectively etched on the peripheral region to remove a hard mask(45) of the gate pattern. A second barrier metal(52) is formed along a profile of the resultant structure. Conductive layers(43,44) are formed on the second barrier metal and the whole surface.

Description

 Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a graph showing contact resistance characteristics between a bit line and a gate;

2 is a graph showing resistance characteristics between bit line contacts / gates according to gate line widths;

3 is a graph illustrating resistance characteristics between bit line contacts / gates according to a material formed on a gate;

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

41 semiconductor substrate 42 device isolation film

43 polysilicon film 44 silicide

45 hard mask nitride film 46 gate spacer

47: first interlayer insulating film 48: landing plug

49: second interlayer insulating film 50: first barrier metal (Ti)

51: titanium silicide 52: second barrier metal (TiN)

53: bitline tungsten

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming bit line contacts in a semiconductor device.

Among the semiconductor memory devices, a DRAM (Dynmic Random Access Memory) and the like are largely divided into, for example, a cell region including a plurality of unit cells composed of 1T1C (one transistor and one capacitor) and a peripheral region including other unit elements.

For example, a bit line is a line connected to the source side of a cell transistor to actually transmit data. On the cell region side, a source / drain junction on the side of a gate electrode (eg, a word line) for electrical connection of the bit line is provided. It is connected between the bit line sense amplifier and the bit line in terms of the peripheral area, which is connected to the cell contact plugs contacted to the area through bit line contacts, and includes a bit line sense amplifier for sensing and amplifying the cell data transferred through these bit lines. A contact is required for the electrical connection.

On the other hand, the contact plug and bit line contacted to the source / drain junction region on the side of the word line in the cell region are referred to as BLC1, and the bit line contact connecting the gate electrode and the source / drain of the bit line sense amplifier in the peripheral region is Called BLC2.

In general, in the bit line process, in the case of the bit line contact formed on the silicon substrate and the poly plug, a barrier metal titanium silicide (TiSi ₂ ) is formed to lower contact resistance. In order to form such a titanium silicide, Ti / TiN is formed of a bit line barrier metal, and titanium silicide is formed by rapid heat treatment (RTP). In the case of the thus formed titanium silicide, there is a possibility of affecting the bit line contact resistance by thermal in the subsequent process.

Recently, the annealing temperature was increased after the formation of the lower electrode in order to improve the leakage characteristic of the metal-inslator-metal (MIM) capacitor. This increase in annealing temperature has the effect of reducing the capacitor's leakage characteristics, but also results in increased bit line and gate resistance. Existing papers show that when the thermal is high, titanium silicide is formed in the lower poly region through the grain boundary of the tungsten silicide, the word line, which appears to increase contact resistance. (Reference: Reaction of Ti with WSi ₂ -J. Appl. Phys. 82 (12), 15 December 1997)

On the other hand, in the case of the contact resistance between the bit line and the gate, it has been confirmed that the gate contact resistance rapidly increases when the device becomes extremely small and falls below a specific contact size.

FIG. 1 is a graph showing contact resistance characteristics between a bit line and a gate. When titanium, not titanium silicide, is directly bonded to a gate and a bit line contact, the contact resistance between the bit line and the gate has a uniform and low value. Can be.

2 is a graph illustrating resistance characteristics between bit line contacts and gates according to gate line widths. As the contact size decreases, the contact resistance between the bit line contact and the gate gradually increases, and rapidly increases when the contact size becomes smaller than a certain size. It can be seen that.

FIG. 3 is a graph illustrating resistance characteristics between bit line contacts / gates according to materials formed on gates. When the non-titanium silicide titanium is directly formed on the gates, the contact resistances between the bit line contacts and the gates are uniform and low. Able to know.

The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device manufacturing method suitable for improving the characteristics of the device by reducing the contact resistance between the gate electrode and the bit line in the cell region and the peripheral circuit region. There is a purpose.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a plurality of gate patterns on a semiconductor substrate divided into a cell region and a peripheral circuit region; Forming a doped impurity diffusion region, forming a first interlayer insulating film on the entire surface including the gate pattern, penetrating the first interlayer insulating film in the cell region, and contacting the semiconductor substrate; Forming an interlayer insulating film and a plug having a planarization thereon; forming a second interlayer insulating film on the entire surface including the first interlayer insulating film and the plug; and selectively etching the second interlayer insulating film in the cell region. Forming a first open portion exposing the upper portion of the plug, the second interlayer insulating layer in the peripheral circuit region Selectively etching the first insulating layer to form a second open portion exposing the impurity diffusion region, forming a first barrier metal according to a profile of the resultant portion in which the open portion is formed, the first open portion and the first Forming a silicide in an open portion, removing the first barrier metal except for the silicide, selectively etching the second interlayer insulating layer in the peripheral circuit region, and removing the hard mask of the gate pattern; Forming a second barrier metal along a profile of the resultant, and forming a conductive film on the entire surface of the second barrier metal and the resultant.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

4A through 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 4A, an isolation layer 42 and a well (not shown) are formed on a semiconductor substrate 41 having a cell region and a peripheral circuit region separated by a shallow trench isolation (STI) method. On the other hand, the semiconductor substrate 41 is a normal silicon substrate.

Subsequently, a gate oxide film (not shown) is formed on the semiconductor substrate 41, the conductive films 43 and 44 for gate electrodes are laminated on the gate oxide film, and the conductive films 43 and 44 for gate electrodes are formed. After depositing the gate hard mask 45 on, a mask pattern for forming a gate pattern is formed through a photolithography process.

Subsequently, the gate pattern conductive layers 43 and 44 and the gate hard mask 45 are etched using the mask pattern as an etch mask to form a gate pattern having a stacked structure of the hard mask 45 and the gate electrodes 43 and 44. Form.

On the other hand, as the conductive film for the gate electrode, for example, a polysilicon film 43 and a silicide 44 film are used, and in addition, a tungsten film, a tungsten silicide, a titanium film, a titanium nitride film, or the like or a combination thereof is included. In addition, the gate hard mask 45 may include an insulating film based on a nitride film or an oxide film.

Subsequently, an insulating film is deposited in the form of a nitride film or an oxide film alone or in combination along the profile in which the gate pattern is formed, and then dry etching is performed to form the gate spacer 46 on the side of the gate pattern. The gate spacer 46 is to prevent the gate pattern from being attacked in a subsequent etching process.

Subsequently, an ion implantation process is performed in the peripheral circuit region to dope an N-type impurity into the semiconductor substrate 41 to be aligned with the side of the gate pattern, and then the doped impurities are diffused through heat treatment to form a source / drain region of the NMOS transistor ( Not shown).

In the same manner, an ion implantation process is performed to dope P-type impurities into the semiconductor substrate 41 to be aligned with the side of the gate pattern, and then the doped impurities are diffused through heat treatment to thereby source / drain regions of the PMOS transistor (not shown). ).

Meanwhile, in the case of the peripheral circuit region, the ion / drain is implanted twice before forming the spacer so that the source / drain has a lightly doped drain (LDD) structure, and thus the detailed process is omitted.

Subsequently, a first interlayer insulating film 47 is formed on the entire surface of the resultant product.

In this case, the first interlayer insulating film 47 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho). -Silicate film, HDP (High Density Plasma) oxide film, SOG (Spin On Glass) film or APL (Advanced Planarization Layer) film, etc. are used. In addition to oxide film, low dielectric constant film of inorganic or organic type can be used.

Subsequently, in order to secure a margin in a subsequent photolithography process, the upper portion of the first interlayer insulating film 47 is planarized by performing chemical mechanical polishing (CMP) or etch back process.

Next, a mask pattern (not shown) for forming a cell contact is formed on the planarized first interlayer insulating layer 47, and the first interlayer insulating layer 47 is etched using the mask pattern as an etch mask to form a gate pattern in the cell region. After exposing the substrate therebetween, the mask pattern is removed, a conductive film for forming a plug, for example, a polysilicon film is deposited on the entire surface, and a planarization process is performed on the target to which the gate hard mask 45 is exposed. To form.

Subsequently, a second interlayer insulating film 49 is deposited on the landing plug 48 and the first interlayer insulating film 47, and the second interlayer insulating film 49 is planarized.

Next, a contact etching process for exposing a region where the bit line contact BLC1 is to be made in the cell region is performed, and then a contact etching process for exposing an N-type impurity diffusion region in which the bit line contact BLC2 is to be made in the peripheral circuit region. A mask pattern (not shown) for this purpose is formed on the second interlayer insulating film 49, and then the second interlayer insulating film 49 and the first interlayer insulating film 47 are formed using the mask pattern as an etch mask. Etching forms an open portion exposing the N-type impurity diffusion region. The bit line contact process is performed in the same manner in the PMOS region.

Next, a photoresist strip process is performed to remove the mask pattern, which is a photoresist pattern.

As shown in FIG. 4B, the bit line first barrier metal 50 is deposited along the profile of the result of the bit line contact etching process. In this case, the first barrier metal 50 uses a single or combined structure such as a titanium film (Ti), a titanium nitride film (TiN), or a titanium silicide film (TiSi ₂ ), for example, an embodiment of the present invention. Uses a single film of titanium film.

As shown in FIG. 4C, the titanium silicide 51 is formed on the open bit line contact region of the upper part of the landing plug 48 of the cell region and the peripheral circuit region by rapid heat treatment at a temperature of 700 ° C. to 900 ° C. on the front surface of the resultant. ). More specifically, it is a metal silicide through the reaction of the first barrier metal 50 and silicon, and serves to reduce the contact resistance by making an ohmic contact between the bit line conductive film and the contact portion.

As shown in FIG. 4D, dry cleaning is performed to remove the titanium film 50 except for the titanium silicide 51.

As shown in FIG. 4E, after the titanium film is removed by dry cleaning, a gate mask (not shown) is formed on the second interlayer insulating film 49a of the peripheral circuit region, and the gate mask is used as an etch mask to form the second interlayer insulating film ( 49a) and an etching process for removing the gate hard mask 45 of the gate pattern is performed.

As shown in FIG. 4F, a second barrier metal 52 is deposited along the profile of the result. In this case, the second barrier metal 52 uses a single or combined structure such as a titanium film (Ti), a titanium nitride film (TiN), or a titanium silicide film (TiSi ₂ ), for example, an embodiment of the present invention. In this case, a single film of titanium nitride film is used.

Next, a tungsten film is deposited on the bit line conductive film 53 on the entire surface of the resultant product including the second barrier metal 52.

As described above, only the NMOS and PMOS regions of the peripheral circuit region in the bit line contacts BLC 1 and BLC2 regions requiring ohmic contacts are first etched to form titanium silicide, and then the bit line contacts are added to the gate. After etching, the titanium nitride film, which is a barrier metal, is deposited, and then a tungsten film, which is a bit line conductive film, is deposited to not form a titanium film or titanium silicide on the gate pattern. There is no increase in the contact resistance between the gate and the gate, thereby reducing leakage.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the above-described present invention, there is no increase in contact resistance between the bit line and the gate electrode during the rapid heat treatment process, so that the thermal temperature of the MIM capacitor annealing process can be increased, thereby reducing the leakage of the capacitor.

In addition, since the titanium nitride film is directly bonded on the gate electrode, the bit line contact resistance is uniformly reduced.

In addition, since there is no barrier metal titanium film on the side of the bit line contact on the gate, there is a contact increase effect, thereby reducing the contact resistance between the bit line and the gate electrode.

Claims (5)

Forming a plurality of gate patterns on a semiconductor substrate divided into a cell region and a peripheral circuit region; Forming an impurity diffusion region in the peripheral circuit region that is aligned with side surfaces of each gate pattern; Forming a first interlayer insulating film on the entire surface including the gate pattern; Forming a plug in the cell region penetrating through the first interlayer insulating film and contacting the semiconductor substrate, wherein the plug is planarized on the first interlayer insulating film; Forming a second interlayer insulating film on an entire surface including the first interlayer insulating film and the plug; Selectively etching the second interlayer dielectric layer in the cell region to form a first open portion exposing the upper portion of the plug; Selectively etching the second interlayer dielectric layer and the first interlayer dielectric layer in the peripheral circuit region to form a second open portion exposing the impurity diffusion region; Forming a first barrier metal along a profile of the resultant portion in which the open portion is formed; Forming a silicide in the first open portion and the second open portion; Removing the first barrier metal except for the silicide; Selectively etching the second interlayer insulating layer in the peripheral circuit region to remove the hard mask of the gate pattern; Forming a second barrier metal along the profile of the result; And Forming a conductive film on the entire surface of the second barrier metal and the resultant Semiconductor device manufacturing method comprising a. The method of claim 1, The first barrier metal uses a single or combined structure of a titanium film, a titanium nitride film and a titanium silicide film, and the second barrier metal uses a single or combined structure of a titanium film, a titanium nitride film and a titanium silicide film. A semiconductor device manufacturing method. Following claim 1 Forming silicide on the first and second open portions, A method of manufacturing a semiconductor device for performing a rapid heat treatment to silicide the first barrier metal. The method of claim 1, Removing the first barrier metal except the silicide, The method of claim 1, wherein the first barrier metal excluding the silicide is removed by chemical dry etching. The method of claim 1, The first barrier metal uses a titanium film, and the second barrier metal uses a titanium nitride film.

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