KR100600045B1 - Semiconductor device able to decrease bitline contact resistance and method for fabricatrion of the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce the bit line contact resistance in both the P-type water-diffusion diffusion region and the N-type impurity diffusion region, the present invention to achieve the above object, To this end, the present invention, the N-type impurity diffusion region formed in a predetermined region of the substrate; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; And a bit line formed on the first barrier layer and the second barrier layer.

In addition, the present invention, the gate electrode formed on the substrate; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; A third barrier film formed on the gate electrode with the second thickness; And a bit line formed on the first barrier film, the second barrier film, and the third barrier film.

Bit line, contact resistance, P-type impurity diffusion region, N-type impurity diffusion region, barrier film, ion implantation, BLC1, BLC2.

Description

A semiconductor device capable of reducing bit line contact resistance and a method of manufacturing the same {SEMICONDUCTOR DEVICE ABLE TO DECREASE BITLINE CONTACT RESISTANCE AND METHOD FOR FABRICATRION OF THE SAME}             

1 is a cross-sectional view showing a semiconductor device having a bit line according to the prior art.

2 is a flowchart illustrating a bit line forming process according to the prior art.

3 is a cross-sectional view illustrating a semiconductor device in which a bit line is formed in accordance with an embodiment of the present invention.

4 is a flowchart illustrating a bit line forming process according to the present invention.

5A through 5E are cross-sectional views illustrating a bit line forming process of a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

500: substrate 501: field oxide film

502: gate conductive film 503: gate hard mask

504: spacer 505a: N-type impurity diffusion region

505b: P-type impurity diffusion region 506: first insulating film

507: plug 508: second insulating film

510, 515, 516, 518: open part 512, 519: barrier film

513, 520: conductive film 521 bit line hard mask

G1, G2, G3: gate electrode pattern B / L1, B / L2: bit line

A: cell area B: peripheral area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line forming technology of a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same, which can reduce the contact resistance of a bit line contacting a source / drain of a PMOS or NMOS transistor in a peripheral region.

Among the semiconductor memory devices, a DRAM (Dynamic Random Access Memory) and the like are largely divided into, for example, a cell region including a plurality of unit cells composed of 1T1C (one transistor and one capacitor) and a peripheral region including other unit elements. .

For example, a bitline is a line connected to the source side of a cell transistor to actually transmit data. On the cell region side, a source / drain junction region on the side of a gate electrode (eg, a wordline) for electrical connection of such a bitline. Bit line sense amplifiers are connected via cell line plugs and bit line contacts that are connected to the device and include a bit line sense amplifier for sensing and amplifying cell data transmitted through these bit lines. A contact is needed for the electrical connection between the bit line (the gate and source / drain junctions of the transistors that make up the bit line sense amplifier).

Meanwhile, hereinafter referred to as BLC1 through the process of contacting the cell contact plug and the bit line contacted to the source / drain junction region on the side of the word line in the cell region, and the gate electrode and the source / drain of the bit line sense amplifier in the peripheral region. The bit line contact to connect is called BLC2.

1 is a cross-sectional view illustrating a semiconductor device having a bit line according to the related art. Here, 'A' represents a cell region, and 'B' represents a peripheral region (specifically, a bit line sense amplifier forming region).

Referring to FIG. 1, a field oxide film 101 is formed locally on the substrate 100 to distinguish between the field region and the active region, and the gate conductive layer 102 is formed on the substrate 100 of the cell region A. Gate hard masks 103 are stacked and gate electrode patterns G1 and G2 having spacers 104 are formed on the sidewalls, and impurities such as a source / drain are formed on the substrate 100 between the gate electrode patterns G1 and G2. A diffusion region is formed.

In the peripheral area B, the gate conductive layer 102 and the gate hard mask 103 are stacked, and a gate electrode pattern G3 having a spacer 104 is formed on the sidewall thereof, and both sides include source / drain. The high concentration N-type (N +) impurity diffusion region 105a and the high concentration P-type (P +) impurity diffusion region 105b are formed.

In the cell region A, a cell contact plug 107 is formed through the first interlayer insulating film 106 and electrically connected to the impurity diffusion region, and having the gate hard mask 103 and the top thereof flattened.

A second interlayer insulating film 108 is formed on the cell contact plug 107 and the first interlayer insulating film 106. In the cell region A, the second interlayer insulating film 108 is selectively etched to form a cell contact plug 107. The first open portion 109d, that is, the open portion for BLC1, is formed. In the peripheral region B, the second interlayer insulating film 108 and the first interlayer insulating film 106 are selectively etched to form the substrate 100. Second and third open portions 109a and 109c exposing the impurity diffusion regions 105a and 105b of N + and P +, respectively, and the second interlayer insulating film 108 and the gate hard mask 103 are selectively etched. A fourth open portion 109c exposing the gate conductive film 102 of the gate electrode pattern G3 is formed.

Here, the second and third open portions 109a and 109c and the fourth open portion 109c are intended for bit line contact in the peripheral area B and are open portions for the BLC2.

The barrier film 110 and the bit line conductive film 111 are formed along the profiles of the first to fourth open portions 109a to 109d, and the bit line hard mask 112 is stacked and patterned thereon to form the bit. Lines B / L1 and B / L2 are formed.

The barrier film 110 is made of Ti, TiN, TiSi ₂ , and the like, and the bit line conductive film 111 includes tungsten or the like. In addition, the sidewalls of the bit lines B / L1 and B / L2 include spacers, which are not shown here.

On the other hand, the bit line contact resistance in the cell region A is important, but the contact resistance at the time of bit line contact in the peripheral region B is also important. One of the factors that is largely involved in such contact resistance is a barrier film 110 used between the bit line and the lower plug or the source / drain of the substrate. The barrier film 110 includes a stacked structure of TiN / Ti. Is used a lot.

On the other hand, the source / drain of the PMOS transistor, that is, the P + impurity diffusion region 105b, and the source / drain of the NMOS transistor, that is, the N + impurity diffusion region 105a, have opposite characteristics in terms of contact resistance.

That is, the contact resistance decreases as the thickness of the barrier layer 110 is thinner in the P + impurity diffusion region 105b, and the contact resistance increases as the barrier layer 110 is thicker in the N + impurity diffusion region 105a. This is a declining feature.

On the other hand, when forming the bit line in contact with the P + impurity diffusion region 105b and the N + impurity diffusion region 105a, the barrier film and the bit line conductive film were deposited in the same steps in the related art.

2 is a flowchart illustrating a bit line forming process according to the prior art, and looks at the conventional bit line forming process with reference to this.

After the cell contact plug forming process is completed in the cell region, a bit pattern contact, that is, a BLC2 mask pattern for forming a connection between the common drain and the gate of the bit line sense amplifier is formed in the peripheral region (S201), and then the mask pattern is formed. The interlayer insulating layer or the interlayer insulating layer and the gate hard mask are etched using the etching mask to expose the source / drain and the gate conductive layer to which the bit line is to be contacted (S202).

 Subsequently, after forming a mask pattern for forming a bit line contact in the cell region (S203), the interlayer insulating layer is etched using the mask pattern as an etch mask to expose the cell contact plug to which the bit line contact is to be made (S204).

Forming a mask for P + additional implantation to compensate for the low doping concentration of boron impurities due to the active thermal behavior of boron doped in the source / drain of PMOS, ie, P-type impurity diffusion region, and then ion implantation mask After performing the ion implantation process of adding the P + impurity diffusion region using (S205), the P + ion implantation mask is removed (S206).

Subsequently, a heat treatment process for diffusing the additional ion-implanted boron is performed (S207), and a barrier film is deposited to have a uniform thickness along the profile of each open part where the bitline contact is to be made (S208). Subsequently, a heat treatment process is performed to form metal silicide at an interface between the barrier film and the lower portion (impurity diffusion region, cell contact plug) through the reaction between the metal used as the barrier layer and the lower silicon (S209).

Subsequently, a bit line forming conductive film such as a tungsten film is deposited on the barrier film (210), and then a selective etching process using a bit line forming mask pattern is performed to form a bit line forming process in which the barrier film and the bit line conductive film are stacked. This is completed (S211).

As described in the above-described process of FIG. 2, in the conventional case, a satisfactory contact resistance in both of the trade-off relations is formed by simultaneously forming a barrier film in a portion contacting the P + impurity diffusion region and the N + impurity diffusion region. The barrier film was deposited at a thickness that could not be obtained and thus compromised between the two.

Therefore, a lower bit line contact resistance is required for higher speed operation, and a process technology for simultaneously lowering bit line contact resistance in the P + impurity diffusion region and the N + impurity diffusion region is required.

The present invention has been proposed to solve the above problems of the prior art, and to provide a semiconductor device and a method of manufacturing the same that can reduce the bit line contact resistance in both the P-type pure water diffusion region and the N-type impurity diffusion region. For that purpose.

In order to achieve the above object, the present invention, the N-type impurity diffusion region formed in a predetermined region of the substrate; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; And a bit line formed on the first barrier layer and the second barrier layer.

In addition, the present invention to achieve the above object, the gate electrode formed on a substrate; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; A third barrier film formed on the gate electrode with the second thickness; And a bit line formed on the first barrier film, the second barrier film, and the third barrier film.

In addition, to achieve the above object, the present invention is a semiconductor device divided into a cell region and a peripheral region, in the peripheral region, a gate electrode formed on a substrate; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; A third barrier film formed on the gate electrode with the second thickness; And a first bit line formed on the first barrier film, the second barrier film, and the third barrier film, wherein the plug contacts the substrate in the cell region; A fourth barrier film formed on the plug with the second thickness; And a second bit line formed on the fourth barrier film.

In addition, in order to achieve the above object, the present invention is a semiconductor device divided into a cell region and a peripheral region, in the peripheral region, the first gate electrode formed on the substrate and having a laminated structure of a hard mask / gate conductive film ; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the first gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first insulating layer substantially planar with the first gate electrode; A second insulating film formed on the first insulating film; A first barrier layer having a first thickness such that the first insulating layer and the second insulating layer are etched to contact the P-type impurity diffusion region along a profile of a first open part exposing the P-type impurity diffusion region; A first conductive film buried in the first open portion on the first barrier film and substantially flattened with the second insulating film; A second open portion for etching the first insulating layer and the second insulating layer to expose the N-type impurity diffusion region and a third open portion for etching the second insulating layer and the hard mask to expose the gate conductive layer are formed. A second barrier film formed to a second thickness thicker than the first thickness to contact the N-type impurity diffusion region and the P-type impurity diffusion region; And a second conductive film formed on the second barrier film, wherein the first conductive film and the second conductive film form a first bit line, and in the cell region, are formed on the substrate and formed of a hard mask / gate conductive film. Second and third gate electrodes having a stacked structure; A plug penetrating the first insulating layer and contacting the substrate between the second and third gate electrodes and substantially planarizing with the first insulating layer; A third barrier layer formed to the second thickness such that the second insulating layer is etched to contact the plug along a profile of a fourth open portion exposing the plug; And a second bit line formed on the fourth barrier film.

In addition, in order to achieve the above object, the present invention, in the method for manufacturing a semiconductor device divided into a cell region and a peripheral region, forming a plurality of gate electrodes having a laminated structure of a hard mask / gate conductive film on the substrate step; Forming a P-type impurity diffusion region and an N-type impurity diffusion region that are aligned with side surfaces of each gate electrode in the peripheral region; Forming a first insulating film on the entire surface including the gate electrode; Forming a plug penetrating the first insulating layer in the cell region and contacting the substrate, wherein the plug is substantially planarized with the first insulating layer; Forming a second insulating film on an entire surface including the first insulating film and the plug; Selectively etching the second insulating layer and the first insulating layer in the peripheral area to form a first open part exposing the P-type impurity diffusion region; Depositing a first barrier film of a first thickness along a profile in which the first opening is formed; Depositing a first conductive film on the first barrier film; Removing the first conductive layer and the first barrier layer to planarize the target substrate to which the second insulating layer is exposed; Selectively etching the second and first insulating layers in the peripheral region to form a second open portion exposing the N-type impurity diffusion region, and etching the second insulating layer and the hard mask to expose the gate conductive layer. Forming an open portion; Selectively etching the second insulating layer in the cell region to form a fourth open portion exposing the plug; Forming a second barrier film having a second thickness thicker than the first thickness along the profile in which the second to fourth open portions are formed; Forming a second conductive film on the second barrier film; And selectively etching the second conductive layer and the second barrier layer to contact the fourth open portion in the cell region and the first contact portion contacting the first to third open portions in the peripheral region. It provides a method for manufacturing a semiconductor device comprising forming a bit line.

The present invention varies the thickness of the barrier film used between the bit line and the N-type impurity diffusion region formed by the BLC2 process and between the bit line and the P-type impurity diffusion region.

 That is, the thickness of the barrier film in the P-type impurity diffused region is lowered, and the thickness of the barrier film is increased in the N-type impurity diffused region, thereby reducing bit line contact resistance in both. At this time, in the bit line contact portion of the cell region, as in the N-type impurity diffusion region, the thickness of the barrier layer is increased to lower the bit line contact resistance.

Meanwhile, in order to have the above-described configuration, the conventional BLC2 process is divided into a BLC2-N (contact between N-type impurity diffusion region and bit line) process and BLC2-P (contact between P-type impurity diffusion region and bit line) process. Conduct. At this time, the P + additional ion implantation process can be performed using the BLC2-P mask, and the process is not complicated compared with the prior art.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a cross-sectional view illustrating a semiconductor device in which a bit line is formed according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device of the present invention is isolated from the N-type impurity diffusion region 505a and the N-type impurity diffusion region 505a formed in a predetermined region of the substrate 500. P-type impurity diffusion region 505b formed, a first barrier film 512 formed with a first thickness on P-type impurity diffusion region 505b, and a first thickness on N-type impurity diffusion region 505a. And a second barrier film 519 formed to a thick second thickness, and bit lines B / L2 formed on the first barrier film 512 and the second barrier film 519.

In addition, referring to FIG. 1, the semiconductor device of the present invention is an N-type impurity diffusion region formed on a predetermined region of the substrate 500 by being separated from the gate electrode G3 and the gate electrode G3 formed on the substrate 500. 505a, a P-type impurity diffusion region 505b formed in a predetermined region of the substrate 500 in isolation from the N-type impurity diffusion region 505a, and formed on the P-type impurity diffusion region 505b with a first thickness. The first barrier film 512, the second barrier film 519a formed on the N-type impurity diffusion region 505a to a second thickness thicker than the first thickness, and the second thickness on the gate electrode G3. And a bit line B / L2 formed on the first barrier film 519b, the first barrier film 512, the second barrier film 519a, and the third barrier film 519b.

In addition, referring to FIG. 1, the semiconductor device of the present invention, which is divided into a cell region A and a peripheral region B, includes a gate electrode G3 formed on the substrate 500 in the peripheral region B, and a gate. N-type impurity diffusion region 505a formed in a predetermined region of the substrate 500 to be isolated from the electrode G3, and P-type impurity diffusion formed in a predetermined region of the substrate 500 to be isolated from the N-type impurity diffusion region 505a. A first barrier film 512 formed with a first thickness on the region 505b, the P-type impurity diffusion region 505b, and a second thickness larger than the first thickness on the N-type impurity diffusion region 505a. The second barrier film 519a, the third barrier film 519b formed on the gate electrode G3 with the second thickness, the first barrier film 512, the second barrier film 519a, and the third barrier. A plug 507 having a first bit line B / L1 formed on the film 519b and contacting the substrate 500 in the cell region A and having a second thickness on the plug 507. The fourth barrier film 519c formed, Claim Further included is a second bit line (B / L1) formed on the fourth barrier layer (519c).

In addition, referring to FIG. 1, the semiconductor device of the present invention, which is divided into a cell region A and a peripheral region B, is formed on the substrate 500 in the peripheral region and has a hard mask 503 / gate conductive film ( A first gate electrode G3 having a stacked structure of 502, an N-type impurity diffusion region 505a formed in a predetermined region of the substrate 500, isolated from the first gate electrode G3, and an N-type impurity diffusion region A P-type impurity diffusion region 505b formed in a predetermined region of the substrate 500, isolated from 505a, a first insulating film 506 substantially flattened with the first gate electrode G3, and a first insulating film 506. The second insulating film 508 and the first insulating film 506 and the second insulating film 508 are etched along the profile of the first open part 510 exposing the P-type impurity diffusion region 505b. A first barrier film 512 formed to a first thickness so as to contact the P-type impurity diffusion region 505b, and a first open portion 510 are buried on the first barrier film 512, and the second insulating film 5 is embedded. 08 and the second conductive portion 515 that is substantially planarized with the first conductive film 513 and the first insulating film 506 and the second insulating film 508 are exposed to expose the N-type impurity diffusion region 505a. And an N-type impurity diffusion region 505a and a P-type impurity diffusion region along the profile of the third opening portion 516 exposing the second insulating layer 508 and the hard mask 503 to expose the gate conductive layer 503. The first conductive film includes a second barrier film 519 formed to a second thickness thicker than the first thickness so as to contact 505b, and a second conductive film 520 formed on the second barrier film 519. 513 and the second conductive film are made of a tungsten film or the like, and form a first bit line B / L2, and are formed on the substrate 500 in the cell region A, and the hard mask 503 / gate conductive film ( 502 contacts the substrate 500 between the second and third gate electrodes G1 and G2 and the second and third gate electrodes G1 and G2 through the first insulating layer 506. And the first insulating film 506 A second thickness formed such that the substantially flattened plug 507 and the second insulating film 508 are etched to contact the plug 507 along the profile of the fourth open portion 518 that exposes the plug 507. The third barrier film 519c and the second bit line B / L1 formed on the fourth barrier film 519c are provided.

Meanwhile, the drawings corresponding to the plurality of configurations of FIG. 1 described above are illustrated in one drawing of FIG. 3 without separately drawing the drawings.

The second barrier film 519 and the second conductive film 520 extend over the planarized first conductive film 513 and are electrically connected to the first conductive film 513 so that the first bit line B / L2 may be electrically connected. To achieve.

The second thickness is 50 kPa to 100 kPa when the first thickness is 30 kPa to 80 kPa, and the second thickness is 50 kPa to 120 kPa when the first thickness is 30 kPa to 100 kPa.

In the above configuration, reference numeral 501 denotes a field oxide film, and reference numeral 521 denotes a bit line hard mask.

In addition, each barrier film has a structure in which Ti film, TiN film, TiSi _2, etc. are singly or combined.

As can be seen from the configuration of Fig. 3, in the P-type impurity diffusion region 505b, that is, the bit line contact portion corresponding to the source / drain of the PMOS transistor, the thickness of the barrier film is set to 'd1', and the N-type impurity diffusion region 505a. In other words, the thickness of the barrier film is set to 'd2' in the bit line contact portion corresponding to the source / drain of the NMOS transistor, the gate electrode of the NMOS transistor, and the substrate of the cell region A using the NMOS transistor.

Therefore, in the P-type region, the thickness of the barrier film may be lowered to lower the bit line contact resistance, and in the N-type region, the thickness of the barrier film may be increased, which in turn may lower the bit line contact resistance.

4 is a flowchart illustrating a bit line forming process according to the present invention, and looks at the bit line forming process of the present invention with reference to the flowchart.

After the cell contact plug forming process is completed in the cell region, a P-type impurity diffusion region and a bit line contact, that is, a first mask pattern for BLC2 P + are formed in the peripheral region (S401), and then the first mask pattern is used as an etch mask. The interlayer insulating layer is etched to expose the P-type impurity diffusion region to which the bit line is to be contacted, that is, the source / drain of the PMOS transistor (S402). Subsequently, additional ion implantation using boron is performed to the exposed P-type impurity diffusion region using the first mask pattern (S403). Subsequently, the first mask pattern is removed, and a heat treatment process for diffusing the ion-implanted boron is performed (S404). Subsequently, after the barrier film is deposited to contact the P-type impurity diffusion region (S405), the conductive film is deposited on the barrier film (S406), and then planarized through an etch back process (S407). Subsequently, in the peripheral region, an N-type impurity diffusion region and a bit line contact, that is, a second mask pattern for BLC2 N + are formed (S408), and the interlayer insulating layer is etched using the second mask pattern as an etch mask to etch the bit line to N contact. The type impurity diffusion region, that is, the source / drain of the NMOS transistor is exposed (S409).

At this time, the barrier film contacting the P-type impurity diffusion region is deposited to have a first thickness.

Subsequently, after forming a third mask pattern for forming a bit line contact in the cell region (S410), the interlayer insulating layer is etched using the second mask pattern as an etch mask to expose the cell contact plug for the bit line contact (S411). .

Subsequently, a barrier having a thickness greater than the first thickness is formed along the profile of the N-type impurity diffusion region in the exposed peripheral region and the open portion exposing the plug in the gate electrode and the cell region through the process of exposing the BLC2 N + and the cell contact plug. A film is deposited (S412). Subsequently, the metal silicide is formed at an interface between the barrier layer and the lower portion (impurity diffusion region, cell contact plug) by reacting the metal used as the barrier layer with the lower silicon (S414).

Subsequently, a bit line forming conductive film, such as a tungsten film, is deposited on the barrier film, and then a selective etching process using a bit line forming mask pattern is performed to stack the barrier film and the bit line conductive film in the cell region and the peripheral region. The line forming process is completed (S415).

5A through 5E are cross-sectional views illustrating a bit line forming process of a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, a process of manufacturing a semiconductor device having the configuration of FIG. 3 will be described with reference to the flowchart of FIG. 4 through the embodiments of FIGS. 5A to 5E.

Here, 'A' represents a cell region and 'B' represents a peripheral region.

A field oxide film 501 and a well (not shown) are formed on a substrate 500 on which various elements for forming a semiconductor device are formed.

Subsequently, a gate insulating film (not shown) is formed on the substrate 500. An oxide film-based insulating film is used as the gate insulating film. Here, the substrate 500 is a normal silicon substrate.

After depositing a conductive film and a hard mask insulating film on the gate insulating film in order, a mask pattern for forming a gate electrode pattern is formed through a photolithography process, and then the conductive film and the hard mask insulating film are etched using the mask pattern as an etching mask. Thus, the gate electrode patterns G1, G2, and G3 having a laminated structure of the hard mask 503 / gate conductive film 502 are formed.

The gate conductive layer 502 includes a single or combined structure of polysilicon, tungsten, tungsten silicide, Ti, TiN, and the like, and the gate hard mask 503 includes an insulating layer based on a nitride layer or an oxide layer.

Subsequently, an insulating film is deposited in the form of a nitride film or an oxide film alone or in combination along the profile in which the gate electrode structure is formed, and then an etch back process is performed to form spacers 504 on the sidewalls of the gate electrode. The spacer 504 is to prevent the gate electrode from being attacked in a subsequent etching process.

Subsequently, an ion implantation process is performed in the peripheral region B to dope the N-type impurity to the substrate 500 to be aligned with the side of the gate electrode, and then the doped impurities are diffused through heat treatment to source / drain the NMOS transistor. An N-type impurity diffusion region 505a is formed. In this case, as the N-type impurity, an acenic or the like is used.

In the same manner, the ion implantation process is performed to dope the P-type impurity into the substrate 500 to be aligned with the side of the gate electrode, and then diffuse the doped impurity through heat treatment to diffuse the P-type impurity, which is the source / drain of the PMOS transistor. Area 505b is formed. In this case, boron or the like is used as the P-type impurity.

Meanwhile, in the case of the peripheral region B, two ion implantations are performed before and after forming the spacer 504 so that the source / drain has a lightly doped drain (LDD) structure.

Subsequently, an etch stop film (not shown) is formed on the spacer 504.

The etch stop layer 504 serves as an etch stop in an etching process such as a self alignment contact (hereinafter referred to as SAC) and mainly uses a nitride layer series. Accordingly, the spacer 504 may be regarded as consisting of an etch stop film and a double structure.

Next, a first insulating film 506 is formed over the entire surface. The first insulating film 506 includes an oxide film-based insulating film or an organic or inorganic-based low dielectric constant film.

Examples of the oxide-based insulating film include BSG (Boro Silicate Glass), BPSG (Boro Phospho Silicate Glass), PSG (Phospho Silicate Glass), TEOS (Tetra Ethyl Ortho Silicate), HDP (High Density Plasma), It includes a single or combined structure, such as a spin on glass (SOG) film, an advanced planarization layer (APL) film.

Subsequently, the upper portion of the first insulating layer 506 is planarized by using a CMP or etch back process to secure a margin in a subsequent photolithography process.

Subsequently, a mask pattern (not shown) for forming a cell contact is formed on the planarized first insulating layer 506, and the first insulating layer 506 is etched using the mask pattern as an etch mask to form a gate electrode in the cell region A. FIG. After exposing the substrate between the patterns G1 and G2, the mask pattern is removed, a conductive film for forming a plug, for example, a polysilicon film is deposited on the front surface, and a planarization process is performed on the target to which the gate hard mask 503 is exposed. Isolate 507.

Subsequently, a second insulating film 508 is deposited on the plug 507 and the first insulating film 506, and then the top of the second insulating film 508 is planarized. The second insulating film 508 includes an oxide film-based insulating film.

Subsequently, a contact etching process is performed to expose the P-type impurity diffusion region 505b where the bit line contact is to be made in the peripheral region B. A mask pattern 509 is formed on the second insulating layer 508. Next, the second insulating layer 509 and the first insulating layer 506 are etched using the mask pattern 509 to form an open portion 510 exposing the P-type impurity diffusion region 505b.

Subsequently, an additional ion implantation step 511 is performed in the P + impurity diffusion region using the mask pattern 509 as an ion implantation mask.

P-type impurities such as boron are more active by heat than N-type impurities, and due to heat generated in a subsequent process performed after formation of the P-type impurity diffusion region 505b, impurities are diffused and disappeared under the substrate 500. The concentration of impurities in the P-type impurity diffusion region 505b is lowered. This low impurity concentration results in an increase in contact resistance. Therefore, the P-type impurity diffusion region 505b requires an additional impurity ion implantation process 511.

Next, a photoresist strip process is performed to remove the mask pattern 509 that is a photoresist pattern.

Subsequently, as shown in FIG. 5B, a heat treatment process for diffusion of the doped impurities in the P-type impurity diffusion region 505b in which additional impurity ion implantation ions are completed is performed using boron or the like. In this case, in order to solve the problems caused by excessive diffusion of impurities in the P-type impurity diffusion region 505b and exposure to high temperature processes for a long time, rapid thermal treatment (hereinafter referred to as RTA) Is carried out.

Subsequently, the barrier layer 512 is deposited along the profile in which the open portion 511 is formed, and then the open portion 510 is buried by depositing a conductive film 513 for forming a bit line on the entire surface.

Subsequently, an etch back process is performed to remove the conductive film 513 and the barrier film 512 from the target to which the second insulating film 508 is exposed.

At this time, the barrier film 512 has a single or combined structure such as a Ti film, a TiN film, or a TiSi ₂ , and the conductive film 513 includes a tungsten film as a bit line conductive film.

At this time, the thickness of the barrier film 512 is made thin to minimize the contact resistance between the P-type impurity diffusion region 505b, the barrier film 512, and the conductive film 513.

At this time, unlike the conventional method, only the process of forming the barrier film 512 in contact with the P-type impurity diffusion region 505b can be performed alone, and the thickness thereof can be arbitrarily lowered.

Subsequently, as shown in FIG. 5C, a contact etching process is performed to expose the N-type impurity diffusion region 505a and the gate conductive layer 502 where the bit line contact is to be made in the peripheral region B. After the mask pattern 514 is formed on the second insulating layer 508, the second insulating layer 509 and the first insulating layer 506 are etched using the mask pattern 514 as an etch mask to form the N-type impurity diffusion region 505a. ) To form an open portion 515.

At the same time, the second insulating layer 508 and the gate hard mask 503 are etched to form an open portion 516 exposing the gate conductive layer 502.

Next, a photoresist strip process is performed to remove the mask pattern 514.

Subsequently, as shown in FIG. 5D, a mask pattern 517 for forming a bit line contact is formed in the cell region A, and then the second insulating layer 508 is etched using the mask pattern 517 as an etch mask. An open portion 518 is formed to expose the upper portion of the plug 507 where the bit line contact is to be made.

Next, the mask pattern 517 is removed.

Accordingly, the regions (source / drain and gate electrodes of the NMOS transistor) in which the bit line contact is made except for the P-type impurity diffusion region 505b are exposed through the open portions 515, 516, and 518.

Subsequently, a barrier layer 519 is deposited along the profile in which the open portions 515, 516, and 518 are formed, and then a conductive layer 520 for forming a bit line is deposited on the barrier layer 519.

The barrier film 519 is a structure alone or in combination, such as a Ti film, a TiN film, or TiSi ₂ , and the conductive film 520 includes a tungsten film.

At this time, the thickness of the barrier film 519 is made thicker than that of the barrier film 512 so that the thickness of the barrier film 519 between the N-type impurity diffusion region 505a or the gate conductive film 502 and the barrier film 519 and the conductive film 520 can be increased. Minimize contact resistance.

At this time, unlike the conventional method, only the barrier film 512 forming step of contacting the P-type impurity diffusion region 505b can be performed alone, and the barrier film 519 forming step in other areas can be separated. The barrier film thicknesses mutually required can be arbitrarily adjusted.

Subsequently, the conductive film 520 is heat-treated to provide a barrier film 519, an N-type impurity diffusion region 505a, a barrier film 519 and a plug 507, a barrier film 519, a gate conductive film 502, and a barrier. A metal silicide such as TiSi ₂ is formed between the film 512 and the P-type impurity diffusion region 505b through the reaction of the metal of the barrier film with silicon to form an ohmic contact between the bit line conductive film and the contact portion. .

Subsequently, by depositing the bit line hard mask 521 on the conductive film 520, and then performing a patterning process, as shown in Figure 3, the eye area in the cell region (A) and the peripheral region (B), respectively Forms the bitlined B / L1 and B / L2.

According to the present invention made as described above, the thickness of the barrier film used between the bit line and the N-type impurity diffusion region formed by the BLC2 process and between the bit line and the P-type impurity diffusion region is different. The thickness of the barrier film is lowered, and the thickness of the barrier film is increased in the N-type impurity diffusion region, thereby reducing the bit line contact resistance on both sides. At this time, in the bit line contact portion of the cell region, as in the N-type impurity diffusion region, the thickness of the barrier layer can be increased to reduce the bit line contact resistance.

In addition, the conventional BLC2 process is divided into a BLC2-N (contact between N-type impurity diffusion region and bit line) process and a BLC2-P (contact between P-type impurity diffusion region and bit line) process to have the above-described configuration. Conduct. In this case, the PLC additional ion implantation process can be performed using the BLC2-P mask, and it was found through the examples that the process is not complicated compared to the prior art.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can reduce the bit line contact resistance, thereby improving the performance of the semiconductor device.

Claims (14)

An N-type impurity diffusion region formed in a predetermined region of the substrate; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; And Bit lines formed on the first barrier layer and the second barrier layer Semiconductor device comprising a. A gate electrode formed on the substrate; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; A third barrier film formed on the gate electrode with the second thickness; And Bit lines formed on the first barrier layer, the second barrier layer, and the third barrier layer Semiconductor device comprising a. In a semiconductor device divided into a cell region and a peripheral region, In the peripheral area, A gate electrode formed on the substrate; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first barrier film having a first thickness on the P-type impurity diffusion region; A second barrier film formed on the N-type impurity diffusion region with a second thickness thicker than the first thickness; A third barrier film formed on the gate electrode with the second thickness; And A first bit line formed on the first barrier film, the second barrier film, and the third barrier film; In the cell area, A plug contacted to the substrate; A fourth barrier film formed on the plug with the second thickness; And And a second bit line formed on the fourth barrier film. In a semiconductor device divided into a cell region and a peripheral region, In the peripheral area, A first gate electrode formed on the substrate and having a stacked structure of a hard mask / gate conductive film; An N-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the first gate electrode; A P-type impurity diffusion region formed in a predetermined region of the substrate to be isolated from the N-type impurity diffusion region; A first insulating layer substantially planar with the first gate electrode; A second insulating film formed on the first insulating film; A first barrier layer having a first thickness such that the first insulating layer and the second insulating layer are etched to contact the P-type impurity diffusion region along a profile of a first open part exposing the P-type impurity diffusion region; A first conductive film buried in the first open portion on the first barrier film and substantially flattened with the second insulating film; A second open portion for etching the first insulating layer and the second insulating layer to expose the N-type impurity diffusion region and a third open portion for etching the second insulating layer and the hard mask to expose the gate conductive layer are formed. A second barrier film formed to a second thickness thicker than the first thickness to contact the N-type impurity diffusion region and the P-type impurity diffusion region; And A second conductive film formed on the second barrier film, wherein the first conductive film and the second conductive film form a first bit line; In the cell area, Second and third gate electrodes formed on the substrate and having a stacked structure of a hard mask / gate conductive layer; A plug penetrating the first insulating layer and contacting the substrate between the second and third gate electrodes and substantially planarizing with the first insulating layer; A third barrier layer formed to the second thickness such that the second insulating layer is etched to contact the plug along a profile of a fourth open portion exposing the plug; And And a second bit line formed on the fourth barrier film. The method of claim 4, wherein And the second barrier film and the second conductive film extend over the planarized first conductive film and are electrically connected to the first conductive film. The method according to any one of claims 1 to 5, And the first thickness is 30 mW to 80 mW, and the second thickness is 50 mW to 100 mW. The method according to any one of claims 1 to 5, And the first thickness is 30 mW to 100 mW, and the second thickness is 50 mW to 120 mW. In the method of manufacturing a semiconductor device divided into a cell region and a peripheral region, Forming a plurality of gate electrodes having a stacked structure of a hard mask / gate conductive layer on the substrate; Forming a P-type impurity diffusion region and an N-type impurity diffusion region that are aligned with side surfaces of each gate electrode in the peripheral region; Forming a first insulating film on the entire surface including the gate electrode; Forming a plug penetrating the first insulating layer in the cell region and contacting the substrate, wherein the plug is substantially planarized with the first insulating layer; Forming a second insulating film on an entire surface including the first insulating film and the plug; Selectively etching the second insulating layer and the first insulating layer in the peripheral area to form a first open part exposing the P-type impurity diffusion region; Depositing a first barrier film of a first thickness along a profile in which the first opening is formed; Depositing a first conductive film on the first barrier film; Removing the first conductive layer and the first barrier layer to planarize the target substrate to which the second insulating layer is exposed; Selectively etching the second and first insulating layers in the peripheral region to form a second open portion exposing the N-type impurity diffusion region, and etching the second insulating layer and the hard mask to expose the gate conductive layer. Forming an open portion; Selectively etching the second insulating layer in the cell region to form a fourth open portion exposing the plug; Forming a second barrier film having a second thickness thicker than the first thickness along the profile in which the second to fourth open portions are formed; Forming a second conductive film on the second barrier film; And Selectively etching the second conductive layer and the second barrier layer to contact the fourth open portion in the cell region, and first bits contacting the first to third open portions in the peripheral region. Forming lines Semiconductor device manufacturing method comprising a. The method of claim 8, And after implanting the first open portion, ion implanting additional impurities into the exposed P-type pure water diffusion acid region. The method of claim 9, And forming the first open portion and implanting the additional impurities in the same mask pattern. The method of claim 8, The first thickness is 30 Å to 80 Å, and the second thickness is 50 Å to 100 Å. The method of claim 8, And said first thickness is in the range of 30 mW to 100 mW and said second thickness is in the range of 50 mW to 120 mW. The method of claim 9, And further heat-treating the additional ion implantation. The method of claim 8, And the first and second barrier films comprise a Ti film or a TiN film.

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