KR20010058453A - Method for forming MOS transistor of semconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a MOS transistor of a semiconductor device is provided to form widely a contact electrode for bit line and storage node by forming a source/drain junction on a substrate under an edge of the gate electrode. CONSTITUTION: A field oxide layer(12) is formed on a semiconductor substrate(10). A gate oxide layer(14) is formed on the semiconductor substrate(10). A conductive material is deposited on the gate oxide layer(14). A gate electrode is formed by patterning the gate oxide layer(14). A capping layer(20) is formed on the gate electrode(14). An LDD region(22) is formed on the substrate(10) under an edge of the gate electrode. A spacer(24) is formed at a side of the gate electrode. A high density doped polysilicon layer(26) is formed on the structure. A source/drain junction(28) is formed by diffusing the high density doped polysilicon layer(26). An interlayer dielectric(30) is formed on the substrate(10). A contact electrode(32) is formed by forming a contact hole on the interlayer dielectric(30) and burying the conductive material therein.

Description

Method for manufacturing MOS transistor of semiconductor device {Method for forming MOS transistor of semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor of a semiconductor device having a self-aligned contact structure in a highly integrated semiconductor device.

In recent years, as semiconductor devices become more integrated, memory, for example, dynamic random access memory (DRAM) cell sizes are gradually decreasing, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller and smaller, so that capacitor contacts must be made smaller. do.

In addition, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, when a design rule such as a semiconductor memory cell has no margin and the same pattern is repeated, a method of reducing the area of the memory cell by forming contact holes in a self-aligned manner has been researched and developed. . The self-aligned contact method forms a contact hole by using a step of the surrounding structure, and obtains contact holes of various sizes without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. As a result, it can be used as the most suitable method for realizing a semiconductor device which is reduced in size by high integration.

However, in the conventional self-aligned contact plug manufacturing method, when the nitride film is mainly used for the spacer and capping of the upper portion of the gate electrode, the space margin between the gate electrodes is insufficient when the interlayer insulating film is etched, and the nitride film used as the etching barrier is sufficiently barriered. The capping layer and the spacer are often overetched because they do not play a role, and the loss due to such overetching not only causes a short circuit between the bit line or the plug contact and the word line (gate electrode), but also the storage electrode contact and the bit. There was a problem that caused a short circuit in the line.

An object of the present invention is to form a source / drain junction in the substrate near the edge of the gate electrode by forming a thin doped polysilicon layer on the entire surface of the substrate and performing a heat treatment process before the source / drain ion implantation is omitted and the interlayer insulating film is formed. Thereafter, a contact electrode for a bit line and a storage node can be formed over a wide area, thereby providing a method of manufacturing a transistor of a semiconductor device, which can reduce damage due to fine contact hole etching in a highly integrated semiconductor device.

1 to 4 are process flowcharts illustrating a method of manufacturing a MOS transistor of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

10 semiconductor substrate 12 field oxide film

14 gate oxide film 16 doped polysilicon film for gate electrode

18: Tungsten Silicide for Gate Electrode

20: capping film 22: LDD region

24: spacer 26: high concentration doped polysilicon film

28 source / drain junction 30 interlayer insulating film

32: contact electrode

In order to achieve the above object, the present invention provides a method for manufacturing a MOS transistor, the method comprising: forming a field oxide film on a semiconductor substrate, forming a gate oxide film on the substrate, depositing and patterning a conductor on the gate oxide film; Forming a gate electrode and forming a capping layer of an insulating material on the gate electrode, forming an LDD region in which a conductive impurity is injected into the substrate exposed under the edge of the gate electrode, and forming an LDD region on the side of the gate electrode. Forming a spacer, forming a high concentration doped polysilicon film on the entire surface of the substrate on which the spacer is formed, and performing a heat treatment at high temperature and high pressure to diffuse the dopant of the high concentration doped polysilicon film into the substrate surface to obtain a source / drain junction. Forming an interlayer insulating film on the entire surface of the substrate; And, forming a contact hole in the interlayer insulating film and embedding a conductive material and forming a contact electrode.

According to the present invention, the dopant of the doped polysilicon film is transferred to the LDD region by omitting the source / drain ion implantation during the MOS transistor manufacturing process and forming a high concentration doped polysilicon film on the entire surface of the substrate and performing a heat treatment process before forming the interlayer insulating film. Out-diffusion may form a source / drain region, and at the same time, the contact area between the contact electrode and the junction region may be increased by the polysilicon film to increase the contact resistance of the contact surface.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are process flowcharts for explaining a method of manufacturing a MOS transistor of a semiconductor device according to the present invention.

As shown in FIG. 1, a field oxide film 12 for defining active and inactive regions of a device is formed on a silicon substrate 10 as a semiconductor substrate. The gate oxide film 14 is formed on the substrate 10 on which the field oxide film 12 is formed. A doped polysilicon film 16 and a tungsten silicide 18 are formed on the gate oxide film 14 as a gate conductor, and a nitride film is stacked on the gate oxide film 14 as a capping film 20 thereon.

Next, the capping layer 20, the tungsten silicide 18, and the doped polysilicon are patterned to form a gate electrode by performing a photo-etching process using a gate mask. The gate oxide film 14 is also etched in accordance with the gate electrode.

P (phosphorus) is implanted at low concentration as a conductive impurity to form the LDD region 22 near the surface of the substrate 10, that is, between the edge of the gate electrode or between the gate electrode G and the field oxide film.

Next, as shown in FIG. 2, a nitride film is deposited as an insulator to form a spacer on the sidewall of the gate electrode. The entire surface etching process is performed to etch the nitride film to form the spacers 24 on the sidewalls of the gate electrodes. Next, a high concentration doped polysilicon film 26 is formed on the entire surface of the substrate on which the spacers 24 are formed. In this case, the thickness of the high concentration doped polysilicon film 26 is preferably about 1000 kPa.

Subsequently, a heat treatment process is performed at high temperature and high pressure to diffuse the dopant of the high concentration doped polysilicon film 26 into the substrate surface to form the source / drain junction 28.

3, a thick interlayer insulating film 30 is formed on the entire surface of the substrate. In addition, a contact hole is formed in the interlayer insulating layer 30 by performing a photo mask and an etching process using a contact mask, and the etching process is performed using the high concentration doped polysilicon layer 26 as an etch stop target during the etching process. The contact hole etching process uses a self-aligned contact etching method, which is formed over the field oxide layer 12 and the source / drain junction 28 to increase the area of the contact hole, The contact electrodes to be formed can be spaced apart / insulated far away. Subsequently, a doped polysilicon film is embedded in the interlayer insulating film 30 in which the contact hole is formed as a conductor and patterned to form a contact electrode 32.

Therefore, in the method of manufacturing a MOS transistor according to the present invention, after a spacer is formed, a thin doped polysilicon film 26 is deposited on the entire surface of the substrate, and then a heat treatment is performed to diffuse the dopant in the LDD region 22 to obtain a source / The drain junction 28 is formed. As a result, the present invention omits high energy ion implantation for the source / drain ion implantation process, thereby reducing the damage of the junction region and increasing the contact area of the contact electrode and the source / drain junction during the contact hole etching process. It is possible to prevent short-circuits or excessive spacer etching between contact electrodes due to misalignment.

As described above, according to the MOS transistor manufacturing method of the semiconductor device according to the present invention, since the high energy ion implantation for the source / drain ion implantation process is omitted, damage to the junction region can be reduced.

In addition, the present invention can form a contact electrode between the source / drain junction region and the field oxide film, which can greatly reduce the source / drain junction size than before, and the polysilicon produced over the source / drain junction and the field oxide film. The film can increase the contact area of the contact electrode for the bit line and storage node electrodes and the source / drain junction, which can greatly reduce the contact resistance.

In addition, the present invention can prevent the short-circuit between the contact electrodes due to the mis-alignment or the excessive etching of the spacer due to the mis-alignment during the fine contact hole etching process, thereby improving the manufacturing yield while improving the operating characteristics of the device.

Claims (5)

In the MOS transistor manufacturing method, Forming a field oxide film on the semiconductor substrate; Forming a gate oxide film on the substrate; Depositing and patterning a conductor on the gate oxide layer to form a gate electrode and forming a capping layer of an insulating material on the gate electrode; Forming an LDD region in which a conductive impurity is injected at a low concentration in the substrate exposed under the edge of the gate electrode; Forming a spacer of an insulating material on the side of the gate electrode; Forming a high concentration doped polysilicon film on the entire surface of the substrate on which the spacer is formed; Performing a heat treatment process at a high temperature and a high pressure to diffuse the dopant of the high concentration doped polysilicon film into the substrate surface to form a source / drain junction; Forming an interlayer insulating film on the entire surface of the substrate; And And forming a contact hole in the interlayer insulating film and filling a conductor to form a contact electrode. The method of claim 1, wherein the thick doped polysilicon film has a thickness of about 1000 GPa. The method of claim 1, wherein the manufacturing of the contact hole in the interlayer insulating layer is performed using the high concentration doped polysilicon layer as an etch stop target. The method of claim 1, wherein the contact hole etching process in the interlayer insulating film uses a self-aligned contact etching method. 2. The method of claim 1, wherein the contact hole etching process in the interlayer insulating film is formed over a field oxide film and a source / drain junction.