KR100282712B1 - Contact hole of highly integrated semiconductor device and method of forming the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same for forming a contact hole having good characteristics in a highly integrated DRAM device having a fine line width length.

In the semiconductor device of the present invention, after forming a contact hole for direct contact in the cell region and the core region, the first conductor is deposited and the first conductor remains on both sidewalls of the contact hole in the form of a spacer through a front surface etching process. And a cleaning process to deposit a second conductor to be used as a bit line conductor.

As such, the present invention forms conductive polysilicon spacers on both sidewalls of the contact hole, thereby preventing the contact hole from being excessively expanded during the cleaning process due to the difference in etching speed between the first and second interlayer insulating films in a subsequent process step. By increasing the size of the effective contact hole by the conductive thin film spacer, it is possible to prevent the contact resistance from increasing.

Description

Contact hole of highly integrated semiconductor device and method of forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact hole of a semiconductor device and a method of forming the same, and more particularly to a contact hole having a good characteristic and a manufacturing method thereof in a highly integrated DRAM device having a fine line width length.

BACKGROUND A semiconductor integrated circuit device electrically connects elements formed on a semiconductor substrate using an interlayer insulating film and a plurality of conductive layers. That is, there is a need for a method capable of selectively electrically connecting an active element formed on a semiconductor substrate or another conductive layer formed thereon with an optional conductive layer interposed therebetween. That is, in the semiconductor integrated circuit process, in order to selectively connect the element formed on the semiconductor substrate and a conductive layer, the method of selectively forming a contact hole in the interlayer insulation film of the site | part which needs electrical connection is used.

However, the spacing between gate electrodes formed on a semiconductor substrate as the minimum feature size applied to a semiconductor integrated circuit process is reduced to a deep sub-half-micron size. Will be narrowed down to the same level. Accordingly, the interlayer insulating film applied to insulate the gate electrode from the subsequent conductive layer has difficulty in filling a narrow gap between the gate electrodes. Therefore, a fluidized oxide film (eg, a BPSG film) is used in the semiconductor manufacturing industry to form an interlayer insulating film formed between the gate electrodes and the conductive layer formed on the semiconductor substrate at narrow intervals.

However, according to the related art shown in FIG. 1, the fluidized first interlayer insulating layer 110 formed between the gate electrodes and the conductive layer formed on the semiconductor substrate at narrow intervals is formed on the second interlayer insulating layer 111 that is subsequently deposited. Since it has a faster wet etch rate, a region 130 in which the micro-sized contact hole for high integration is enlarged by a subsequent cleaning process occurs.

As a means to solve this problem, Erik S. Jeng et al. In US Pat. No. 5,710,073 form a silicon nitride film (SiN) after forming the contact holes 140 and 150 as shown in FIG. The silicon nitride film was left only on the sidewalls 141, 142, 151 and 152 of the contact hole by depositing and etching the entire surface, thereby solving the problem of the contact hole being enlarged by a subsequent cleaning process.

However, in order that the silicon nitride film spacers 141, 142, 151, and 152 formed according to the technique disclosed in US Pat. No. 5,710,073 are not removed by a subsequent cleaning process, the silicon nitride film to be deposited requires a certain thickness or more. . Therefore, the silicon nitride film spacers formed on the sidewalls of the micro-sized contact holes cause an effect of relatively reducing the effective size of the contact holes, thereby causing a problem in that the contact resistance increases.

In addition, when forming a contact hole in the gate electrode of the core region according to the prior art disclosed in the above-mentioned US Patent No. 5,710,073, due to over etching to ensure a sufficient margin when forming the contact hole Silicon nitride film spacers 141, 142, 151, and 152 may be formed up to an intermediate portion of the gate conductive layer 145. Accordingly, in the subsequent cleaning, the gate upper conductor is removed and the conductive polysilicon is deposited, so that the silicon nitride spacers 141, 142, 151, and 152 remain in the gate conductive layer 145, thereby increasing the gate contact resistance. It is the cause of letting.

Accordingly, a first object of the present invention is to provide a good contact hole and a method for forming the same in a highly integrated semiconductor device.

A second object of the present invention is to provide a contact hole of a highly integrated semiconductor device and a method of forming the same, in addition to the first object, in which the size of the contact hole does not increase by subsequent cleaning.

It is a third object of the present invention to provide a contact hole of a highly integrated semiconductor device and a method of forming the same in order to improve the contact resistance value by increasing the size of the effective contact hole in addition to the first object.

A fourth object of the present invention is to provide, in addition to the first object, a contact hole having a good contact resistance value in a highly integrated gate structure and a method of forming the same.

1 is a process cross-sectional view showing a contact enlarged by a cleaning process according to the prior art.

2 is a cross-sectional view showing a contact hole formed in a gate structure of a core region according to the prior art.

3 to 7 are process flowcharts showing a method of forming a semiconductor device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

200: semiconductor substrate

201, 301: silicon nitride film

202, 302: tungsten silicide

204: device isolation region

205, 206, 305, 306: Gate spacer

210: first interlayer insulating film

211 silicon nitride film

220: second interlayer insulating film

221, 321, 322: direct contact contacts

230, 231, 330, 331, 332, 333: contact space

240: conductive polysilicon

241: Tungsten Silicide

In order to achieve the above object, the present invention comprises the steps of forming a first conductive layer on a semiconductor substrate; Forming a plurality of insulating layers on the first conductive layer; Forming a contact hole pattern on the plurality of insulating layers; Forming a contact hole by etching the plurality of insulating layers according to the formed contact hole pattern; Applying a conductive thin film to the contact hole; Forming a spacer on both sidewalls of the contact hole by etching the conductive thin film on the entire surface; And forming a second conductive thin film on the resultant of the contact hole.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device manufacturing method according to the present invention will now be described in detail with reference to the accompanying drawings.

3 through 7 are process flowcharts illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

First, referring to FIG. 1, gate insulating layers 207 and 307 are formed on a semiconductor substrate 200, and polysilicon gate electrodes 203 and 303 and tungsten silicide are formed on the gate insulating layers 207 and 307. 202 and 302 and silicon nitride films 201 and 301 are formed. In addition, conductive channels 208 and 308 are formed in the lower semiconductor substrate 200 of the gate insulating layers 207 and 307, and center the gate structures 201, 202, 203, 301, 302 and 303. Therefore, spacers 205, 206, 305, and 306 are formed on both sidewalls. The gate structures 201, 202, 203 are for the cell region of the DRAM device, and the gate structures 301, 302, 303 are for the core region.

In addition, self-aligned active regions 209 and 309 are formed in the lower semiconductor substrate 200 of the spacers 205, 206, 305 and 306, and an isolation region 204 is formed. Meanwhile, as a preferred embodiment for the device isolation, shallow trench isolation (STI) or local oxidation of silicon (LOCOS) may be used.

4 is a cross-sectional view illustrating a process of forming a pad for forming a buried contact and direct contact in a cell region. First, a silicon nitride film 211 is coated and a first interlayer insulating film 210 is formed. According to a preferred embodiment of the present invention, the first interlayer insulating film may deposit a tetraethyl orthosilicate (TEOS) thin film by chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD).

In another preferred embodiment of the present invention, a siren-based borophosilicate glass (BPSG) film is deposited at 400 to 450 ° C. as the first interlayer insulating film, and then concentrated at about 800 ° C. for about an hour. It can form by doing. In addition, the silicon nitride film 211 formed under the first interlayer insulating film 210 serves to prevent diffusion of dopants from the BPSG film 210 into the active device formed on the polysilicon or the semiconductor substrate 200. .

Subsequently, a contact window for forming buried contacts and direct contacts in the cell region is formed on the first interlayer insulating layer, and the second contact layer pattern is formed according to the contact pad pattern for the contact pad. The first interlayer insulating layer 210 and the silicon nitride layer 211 are etched away to open the active region 209.

The contact hole 213 for the contact pad formed as described above is filled with a conductive polysilicon plug doped at a high concentration to form a storage node. In a preferred embodiment according to the present invention, the conductive polysilicon coated on the front surface of the semiconductor substrate is etched back to the front surface of the first interlayer insulating film while leaving the conductive polysilicon plug filled in the contact pad 213 for the contact pad. )can do. In the core region of the DRAM device, the above-described pad contact hole forming process is not applied, and is simply applied to the first interlayer insulating layer 210 on the gate structures 301, 302, and 305.

FIG. 5 is a diagram illustrating a process of directly forming a contact in a cell and a core region of a DRAM device. First, a second interlayer insulating layer 210 and a polysilicon pad 213 formed on the second interlayer film are formed on the second silicon layer. The interlayer insulating film is completely coated and planarized.

In a preferred embodiment of the present invention, the second interlayer insulating film is a planarized second interlayer insulating film by applying an insulating film having a low glass transition temperature and annealing at a temperature higher than the glass transition temperature. Can be formed. In addition, as a preferred embodiment of the present invention, the second interlayer insulating film may be planarized by a chemical mechanical polish (CMP) process.

Subsequently, the cell region of the DRAM device opens a contact hole 221 in the second interlayer insulating film to form a contact directly on the polysilicon pad 213. The core region of the DRAM device forms a contact hole 321 by etching the active region 322 formed in the semiconductor substrate and the silicon nitride layer 301 of the gate structure according to the direct contact pattern formed on the second interlayer insulating layer.

In a preferred embodiment of the present invention, the core region of the DRAM device is a contact hole by etching to the active region 322 formed in the semiconductor substrate and the tungsten silicide layer 302 of the gate structure according to the direct contact pattern formed on the second interlayer insulating film. 321 may be formed.

Referring to FIG. 6, spacers may be formed on both sidewalls of the contact holes 221, 321, and 322 for the direct contact by using an anisotropic etching process. 230, 231, 330, 331, 332, 333.

As a preferred embodiment of the present invention, the first conductive thin film may use a heavily doped polysilicon, and may perform an anisotropic etching process using reactive ion etching. Subsequently, the gate top metal wiring layer (ie, tungsten silicide) 302 of the core region is removed by cleaning, and then a second conductor to be used as a bit line is deposited to fill the direct contacts 221, 321, and 322.

Therefore, in the case of forming contact holes in the interlayer insulating film according to a preferred embodiment of the present invention, spacers 330 and 331 made of conductive polysilicon on both sidewalls of the contact holes 321 are first interlayer insulating films in a subsequent cleaning process. Since the sidewalls of the 210 and the second interlayer insulating layer 220 are prevented from being wet-etched, it is possible to prevent the size of the contact hole having a fine size from being enlarged by the cleaning process. In addition, since the spacers 332 and 333 that protect the sidewalls of the first interlayer insulating film 310 and the second interlayer insulating film 220 are formed of a conductive thin film during the cleaning process, the effective size of the contact hole experienced by the prior art is reduced. The problem of an increase in contact resistance can be avoided.

Also, in the case of the contact hole 321 formed in the gate structure of the core region of the DRAM device, the effective contact hole is increased by using conductive polysilicon as the spacers 330 and 331 instead of the silicon nitride film spacer used in the prior art. With this effect, stable contact resistance can be obtained and the resistance value does not increase because it is the same material as the spacer on the gate electrode.

In a preferred embodiment according to the present invention, the second conductive material may use a heavily doped polysilicon 240, and the bit line process may be performed by depositing and patterning tungsten silicide 241 with a metal wiring layer thereon. You are done. On the other hand, the subsequent process is to complete the DRAM device manufacturing process according to the manufacturing method of the COB (capacitor over bit line) structure generally used in the manufacturing of the DRAM device.

The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously changed, substituted, and changed without departing from the spirit or scope of the invention described in the claims.

As described above, the semiconductor device according to the present invention has a structure in which a conventional integrated DRAM device having a narrow gap between gate electrodes is solved. The present invention provides a subsequent cleaning process by forming conductive polysilicon spacers on both sidewalls of the contact hole. In the step, the contact hole size can be prevented from being enlarged due to the difference in etching speed between the first interlayer insulating film and the second interlayer insulating film, and the contact resistance can be prevented from increasing by preserving the size of the effective contact hole.

Claims (24)

In a contact hole of a highly integrated semiconductor device formed on a semiconductor substrate, A first conductive layer formed on the substrate; A plurality of insulating layers formed on the first conductive layer; A second conductive layer formed on the plurality of insulating layers; Contact holes formed in the plurality of insulating layers to electrically connect the first conductive layer and the second conductive layer; Conductive thin film spacers formed on both sidewalls of the contact hole A highly integrated semiconductor device comprising: a. The semiconductor device of claim 1, wherein the conductive spacers formed on both sidewalls of the contact hole include polysilicon doped at a high concentration. The semiconductor device of claim 1, wherein the plurality of insulating layers formed on the first conductive layer comprises an interlayer insulating layer between the polysilicon and the metal conductive layer. The high density semiconductor device of claim 1, wherein the plurality of insulating layers formed on the first conductive layer comprises a plurality of interlayer insulating layers having different etching rates from each other during wet etching. The semiconductor device of claim 1, wherein the plurality of insulating layers formed on the first conductive layer includes an interlayer insulating layer between an active region and a metal conductive layer. In the manufacturing method of the contact hole formed on the semiconductor substrate, Forming a first conductive layer on the semiconductor substrate; Forming a plurality of insulating layers on the first conductive layer; Forming a contact hole pattern on the plurality of insulating layers; Forming a contact hole by etching the plurality of insulating layers according to the formed contact hole pattern; Applying a conductive thin film to the contact hole; Forming a spacer on both sidewalls of the contact hole by etching the conductive thin film on the entire surface; Embedding a second conductive thin film on the resultant of the contact hole Method for manufacturing a semiconductor device comprising a. The method of claim 6, wherein the forming the contact hole by etching the plurality of insulating layers according to the formed contact hole pattern further comprises cleaning the contact hole. The method of claim 6, wherein the applying of the conductive thin film to the contact hole comprises applying a heavily doped polysilicon. Forming a gate structure on the semiconductor substrate; Forming an active region in the semiconductor substrate in a self-aligned manner with the gate structure interposed therebetween; Applying a silicon nitride film over the entire surface of the resultant formed on the semiconductor substrate; Forming a first interlayer insulating film on the silicon nitride film; Forming a contact hole pattern for a contact pad on the first interlayer insulating layer; Etching the first interlayer insulating layer and the silicon nitride layer by etching the contact hole pattern for the contact pad to open the active region; Applying the opened contact pad contact hole to the entire surface of the semiconductor substrate with conductive polysilicon to fill the filling; Etching back the conductive polysilicon; Applying an entire surface of a second interlayer insulating layer on the resultant formed on the semiconductor substrate; Forming a contact hole pattern for direct contact on the second interlayer insulating film; Forming a contact hole for electrically connecting the conductive layer by etching away the insulating layer formed on the conductive layer to be electrically connected according to the contact hole pattern for the direct contact; Applying a first conductive thin film on the entire surface of the resultant formed on the semiconductor substrate; Etching the first conductive thin film to form a spacer on both sidewalls of the contact hole for the direct contact; Front coating the second conductive thin film on the resultant formed on the semiconductor substrate such that the contact hole for the direct contact is filled Method for manufacturing a semiconductor device comprising a. The method of claim 9, wherein the gate structure formed on the semiconductor substrate has a stacked structure of a silicon oxide film below and a tungsten silicide and a silicon nitride film above the silicon oxide film. The method of claim 9, wherein the gate structure formed on the semiconductor substrate includes spacers on both sidewalls of the gate. The method of claim 9, wherein the forming of the first interlayer insulating film comprises: Applying a first interlayer insulating film on the silicon nitride film; Planarizing the first interlayer insulating film Method for manufacturing a semiconductor device comprising a. The method of claim 9, wherein the forming of the contact pad contact hole pattern on the first interlayer insulating layer comprises forming a pad contact hole pattern for directly forming a contact with a buried contact in a cell region of the DRAM device. The manufacturing method of the semiconductor device. The method of claim 9, wherein forming a contact pad pattern for a contact pad on the first interlayer insulating layer excludes a core region of a DRAM device. The semiconductor device of claim 9, wherein the etching of the conductive polysilicon is performed by etching the conductive polysilicon to the entire surface of the first interlayer insulating layer while leaving the conductive polysilicon plug filled in the contact pad contact hole. Method of preparation. 10. The method of claim 9, wherein the first conductive thin film comprises conductive polysilicon. The method of claim 9, wherein forming the contact hole for the direct contact comprises etching the second interlayer insulating film according to the contact hole pattern to expose the polysilicon pad for the cell region of the DRAM device. The manufacturing method of a semiconductor device. The method of claim 9, wherein the forming of the contact hole for the direct contact comprises contacting the first interlayer insulating layer, the second interlayer insulating layer, and the silicon nitride layer on the gate structure for the core region of the DRAM w arch. Etching according to a sphere pattern to expose the tungsten silicide of the gate structure. The method of claim 9, wherein the forming of the contact hole for the direct contact comprises etching the first interlayer insulating layer and the second interlayer insulating layer according to the contact hole pattern to form a core region of the DRAM device. Exposing an active region within the semiconductor device. 10. The method of claim 9, wherein the second conductive thin film comprises conductive polysilicon. 10. The method of claim 9, wherein the step of applying the entire surface of the second conductive thin film Filling the contact hole for the direct contact with the second conductive thin film; Etching and planarizing the second conductive thin film; Forming tungsten silicide on the second conductive thin film Method for manufacturing a semiconductor device comprising a. 10. The method of claim 9, wherein forming the first interlayer insulating film includes applying a BPSG film and reflowing or chemical mechanical polishing (CMP) planarization by heat treatment. 10. The method of claim 9, wherein forming the second interlayer insulating film includes applying a film having a thickness of 500-1500 Å. The method of manufacturing a semiconductor device according to claim 9, wherein a width of the spacer formed on the sidewall of the contact hole for the direct contact is 100 to 300 Å.