JPS5839014A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5839014A
JPS5839014A JP13810681A JP13810681A JPS5839014A JP S5839014 A JPS5839014 A JP S5839014A JP 13810681 A JP13810681 A JP 13810681A JP 13810681 A JP13810681 A JP 13810681A JP S5839014 A JPS5839014 A JP S5839014A
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
silicon substrate
silicon
aperture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13810681A
Other languages
Japanese (ja)
Inventor
Masahiko Nakatsuka
中塚 正彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13810681A priority Critical patent/JPS5839014A/en
Publication of JPS5839014A publication Critical patent/JPS5839014A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To remove the lattice defect of the titled device by a method wherein the distortion generated due to the difference in the coefficient of thermal expansion between the silicon substrate and the oxide film at the circumferential part of the silicon oxide film is reduced. CONSTITUTION:After ions are implanted, the silicon oxide film 2 located on the whole surface of the silicon substrate 1 is removed, a new silicon oxide film 5 is grown in vapor-phase on the whole surface of the silicon substrate 1, and then the above is annealed by performing heat treatment at 1,000 deg.C in a nitrogenous or oxygenous atmosphere for thirty minutes. In this case, as the annealing is performed in the state wherein no aperture is provided on the silicon oxide film, the thermal distortion which will be generated in the vicinity of the aperture can be prevented, thereby enabling to sharply reduce a leakage current.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

最近、半導体装置の製造工程において、イオン注入技術
が広く適用されるようになってきたが。
Recently, ion implantation technology has come to be widely applied in the manufacturing process of semiconductor devices.

注入量3XIQ  cm−2以上の中高濃度イオン注入
において、接合漏洩電流が熱拡散法に比べ、1〜2桁大
きくなることも少なくない。
In medium to high concentration ion implantation with an implantation amount of 3XIQ cm-2 or more, the junction leakage current is often one to two orders of magnitude larger than that in the thermal diffusion method.

すなわち、従来の製造方法は、第1図に示すように、N
型シリ;ン基板10表面にシリコン酸化膜2を熱酸化法
または気相成長法で形成してから、フォトエツチング法
により開口部3を設けたのち、PWi不純物であるホウ
素を、例えば加速電圧50kVで注入量1×1015c
m′イオン注入する。
That is, in the conventional manufacturing method, as shown in FIG.
A silicon oxide film 2 is formed on the surface of the silicon substrate 10 by thermal oxidation or vapor phase growth, and then an opening 3 is formed by photoetching, and then boron, which is a PWi impurity, is deposited at an accelerating voltage of 50 kV, for example. Injection amount 1×1015c
m′ ion implantation.

このとき格子欠陥は模式的に黒点で示すように注入領域
の表面側に分布している。このあと、1000℃酸素雰
囲気で10分間軽く酸化(ホウ素原子が表面から飛び出
すのを防ぐため)してから、窒素雰囲気で50分間アニ
ール(焼鈍)を行なう。
At this time, lattice defects are distributed on the surface side of the implanted region, as schematically shown by black dots. Thereafter, it is lightly oxidized for 10 minutes in an oxygen atmosphere at 1000° C. (to prevent boron atoms from jumping out from the surface), and then annealed for 50 minutes in a nitrogen atmosphere.

辷のとき第2図のように、格子欠陥の#1とんどけ消失
するが、シリコン酸化1!2の開口の周辺部4では、シ
リコン基板1との熱膨張係数の違いによる歪応力が集中
するため、イオン注入によって発生した格子欠陥がシリ
コン−酸化膜境界面を中心に転位網に成長してP−N接
合漏洩電流を生ずるものと考えられる。とこでは、シリ
コン酸化膜2をイオン注入マスクとして用いているが、
シリコン窒化膜を用いても漏洩電流の問題を解消すると
とはできなかった、この程度の注入量になると、耐熱性
のないフォトレジストをイオン注入マスクとして使用す
ることはできない。
When stretched, as shown in Figure 2, lattice defect #1 almost disappears, but strain stress due to the difference in thermal expansion coefficient with silicon substrate 1 is concentrated in the peripheral area 4 of the opening of silicon oxide 1!2. Therefore, it is considered that lattice defects generated by ion implantation grow into a dislocation network around the silicon-oxide film interface, causing a P-N junction leakage current. Here, the silicon oxide film 2 is used as an ion implantation mask.
Even with the use of a silicon nitride film, it has not been possible to solve the problem of leakage current, and with such an implantation amount, a photoresist with no heat resistance cannot be used as an ion implantation mask.

本発明は前記のような接合漏洩電流の原因となる結晶欠
陥を解消することのできる製造方法を提供するものであ
る。
The present invention provides a manufacturing method that can eliminate crystal defects that cause junction leakage current as described above.

本発明は、前記シリコン酸化膜20周辺部4が熱処理に
よって受けるシリコン基板1とシリコン酸化膜2との熱
膨張係数の違いによる歪を軽減することにより、格子欠
陥を解消するものである9本発明の実施例を次に述べる
The present invention eliminates lattice defects by reducing the strain caused by the difference in thermal expansion coefficient between the silicon substrate 1 and the silicon oxide film 2, which the peripheral portion 4 of the silicon oxide film 20 receives due to heat treatment. An example will be described below.

実施例1、 tX1図のようにイオン注入が終ったら、シリコン酸化
膜2を全面除去し、第3図に示すように、シリコン基板
lの全面に新しいシリコン酸化膜5を気相成長してから
、例えば1000°Cの窒素または酸素雰囲気中での3
0分間の熱処理によってアニールを行なう。この場合に
は、シリコン酸化膜に開口部がない状態でアニールされ
るため、前述の開口部近傍に発生する熱歪はなくなり、
漏洩実施例2 第1図のようにイオン注入が終ったら、酸化膜2を除去
したtまで第4図の状態で実施例1の場゛合と同11(
7)条件でアニールを行々い、同様の効果を得ることが
できる。ただし、この場合はシリコン基板表面がむき出
しになっているため、注入されたホウ素が飛び出して注
入されていないシリコン表層部6に再拡散す、るため、
表層部6を後続の工程で熱酸化してしまうとか、注入領
域3の表面濃度と周囲の表層部6との表面濃度に大差が
ないとか、アニール雰囲気が酸素などの酸化性雰囲気で
あるとかのいずれかの条件が必要となる。なお。
Example 1: After the ion implantation is completed as shown in the tX1 diagram, the silicon oxide film 2 is completely removed, and a new silicon oxide film 5 is grown in a vapor phase on the entire surface of the silicon substrate 1 as shown in FIG. , e.g. 3 in a nitrogen or oxygen atmosphere at 1000°C.
Annealing is performed by heat treatment for 0 minutes. In this case, since the silicon oxide film is annealed without any openings, the thermal strain that occurs near the openings described above is eliminated.
Leakage Example 2 After the ion implantation is completed as shown in FIG. 1, the process is carried out in the same manner as in Example 1 in the state shown in FIG. 4 until t when the oxide film 2 is removed.
7) Similar effects can be obtained by performing annealing under different conditions. However, in this case, since the silicon substrate surface is exposed, the implanted boron jumps out and re-diffuses into the unimplanted silicon surface layer 6.
The surface layer 6 may be thermally oxidized in a subsequent process, the surface concentration of the implanted region 3 and the surrounding surface layer 6 may not be significantly different, or the annealing atmosphere may be an oxidizing atmosphere such as oxygen. Either condition is required. In addition.

上記の場合のアニール法として高出力のレーザ、フラッ
ジ凰光、電子ビームなどを照射する方法を用いても良く
、これらの場合には照射時間が短くてすむため、前記ホ
ウ素の飛び出しがなく、上記の諸条件は不要となる。
As an annealing method in the above case, a method of irradiating with a high-power laser, flood light, electron beam, etc. may be used. In these cases, the irradiation time is short, so the boron does not jump out, and the above-mentioned The following conditions are no longer necessary.

これらの実施例のいずれかを実施することによ)、イオ
ン注入領域の接合漏洩電流を軽減するととが可能となっ
た。
By implementing any of these embodiments), it has become possible to reduce junction leakage current in the ion implantation region.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来の製造方法を示す断面図、第3
図及び第4図は本発明の実施例を示す断面図である。 1・・・・・・シリコン基板、2・・・・・・シリコン
酸化膜、3、・・・・・・開口部、4・・・・・・開口
の周辺部、5・・・・・・新しいシリコン−化膜、6・
・・・・・周囲の注入されて卒4ノ
Figures 1 and 2 are cross-sectional views showing the conventional manufacturing method;
FIG. 4 is a sectional view showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Silicon oxide film, 3...Opening, 4...Periphery of opening, 5...・New silicon film, 6.
...The surroundings are injected and the 4th

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一生面上の薄膜の一部に設けられた開孔を
通して不純物を前記基板内にイオン注入する工程と、前
記薄膜を全面除去する工程と、アニーリングを行って前
記基板表面の結晶の損傷を回復させる工程を含むことを
特徴とする半導体装置の製造方法。
A step of ion-implanting impurities into the substrate through an opening provided in a part of a thin film on the entire surface of the semiconductor substrate, a step of completely removing the thin film, and annealing to damage the crystals on the surface of the substrate. 1. A method of manufacturing a semiconductor device, comprising a step of recovering .
JP13810681A 1981-09-02 1981-09-02 Manufacture of semiconductor device Pending JPS5839014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13810681A JPS5839014A (en) 1981-09-02 1981-09-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13810681A JPS5839014A (en) 1981-09-02 1981-09-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5839014A true JPS5839014A (en) 1983-03-07

Family

ID=15214084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13810681A Pending JPS5839014A (en) 1981-09-02 1981-09-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5839014A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63144517A (en) * 1986-12-09 1988-06-16 Nec Corp Manufacture of semiconductor device
US4818711A (en) * 1987-08-28 1989-04-04 Intel Corporation High quality oxide on an ion implanted polysilicon surface
US4931405A (en) * 1988-02-08 1990-06-05 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device and suppressing the generation of bulk microdefects near the substrate surface layer
EP0731500A2 (en) * 1995-03-08 1996-09-11 Hitachi, Ltd. Method of forming a semiconductor device comprising an oxidation step followed by a heat-treatment step
US6297113B1 (en) 1998-04-03 2001-10-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50548A (en) * 1973-04-20 1975-01-07
JPS55127018A (en) * 1979-03-26 1980-10-01 Hitachi Ltd Impurity diffusion into semiconductor substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50548A (en) * 1973-04-20 1975-01-07
JPS55127018A (en) * 1979-03-26 1980-10-01 Hitachi Ltd Impurity diffusion into semiconductor substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63144517A (en) * 1986-12-09 1988-06-16 Nec Corp Manufacture of semiconductor device
US4818711A (en) * 1987-08-28 1989-04-04 Intel Corporation High quality oxide on an ion implanted polysilicon surface
US4931405A (en) * 1988-02-08 1990-06-05 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device and suppressing the generation of bulk microdefects near the substrate surface layer
EP0731500A2 (en) * 1995-03-08 1996-09-11 Hitachi, Ltd. Method of forming a semiconductor device comprising an oxidation step followed by a heat-treatment step
EP0731500A3 (en) * 1995-03-08 1998-05-20 Hitachi, Ltd. Method of forming a semiconductor device comprising an oxidation step followed by a heat-treatment step
US6326284B1 (en) 1995-03-08 2001-12-04 Hitachi, Ltd. Semiconductor device and production thereof
US6297113B1 (en) 1998-04-03 2001-10-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby

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