JPS6312376B2 - - Google Patents
Info
- Publication number
- JPS6312376B2 JPS6312376B2 JP16445482A JP16445482A JPS6312376B2 JP S6312376 B2 JPS6312376 B2 JP S6312376B2 JP 16445482 A JP16445482 A JP 16445482A JP 16445482 A JP16445482 A JP 16445482A JP S6312376 B2 JPS6312376 B2 JP S6312376B2
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- silicon
- oxygen
- defects
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 37
- 229910052710 silicon Inorganic materials 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000013078 crystal Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 description 34
- 238000000034 method Methods 0.000 description 15
- 238000010438 heat treatment Methods 0.000 description 11
- 229910052787 antimony Inorganic materials 0.000 description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 5
- 238000005247 gettering Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000005049 silicon tetrachloride Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にゲツタリ
ング方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a gettering method.
本発明の製造方法によれば特にN型シリコン基
板を必要とする半導体素子のリーク電流を極めて
低く抑える事ができ、半導体素子特性の劣化を防
ぎ高歩留り、高品質の半導体装置を得ることがで
きる。 According to the manufacturing method of the present invention, it is possible to suppress leakage current of a semiconductor element particularly requiring an N-type silicon substrate to an extremely low level, prevent deterioration of semiconductor element characteristics, and obtain a high-yield, high-quality semiconductor device. .
従来の方法では、デバイスプロセスの熱履歴に
よりシリコン基板に内在する酸素が析出し内部欠
陥、表面欠陥として現われてしまう。内部欠陥は
ゲツタリング効果で有効であるが表面欠陥は半導
体素子の特性、歩留りの低下の原因となつてしま
う。 In conventional methods, oxygen inherent in the silicon substrate precipitates due to the thermal history of the device process and appears as internal defects and surface defects. Although internal defects are effective due to gettering effects, surface defects cause a decrease in the characteristics and yield of semiconductor devices.
表面欠陥を除去するためデバイスプロセス中あ
るいは前に表面無欠陥層の形成および内部欠陥形
成のための熱処理を施す方法、所謂イントリンシ
ツクゲツタリング(IG)技術がある。しかし、
IG処理には種々の制約がある。例えば、シリコ
ン基板中の酸素濃度の最適化、無欠陥層および内
部欠陥形成のための熱処理とデバイスプロセスと
の適性化等がそれである。 In order to remove surface defects, there is a so-called intrinsic gettering (IG) technique, which is a method in which heat treatment is performed to form a surface defect-free layer and to form internal defects during or before device processing. but,
IG processing has various restrictions. Examples include optimizing the oxygen concentration in a silicon substrate, and optimizing heat treatment and device processes for forming defect-free layers and internal defects.
酸素濃度、熱処理の選択を極く僅かでも誤ると
内部欠陥が表面にまで到達してしまつたり、内部
欠陥が形成されなかつたりして半導体素子の特性
が劣化し、製造上の歩留りと品質が低下する問題
があつた。 If the selection of oxygen concentration or heat treatment is even slightly incorrect, internal defects may reach the surface or may not be formed, resulting in deterioration of the characteristics of the semiconductor device and lowering manufacturing yield and quality. There was a problem with the decline.
また、表面欠陥を除去する方法としてエピタキ
シヤルウエハーを使う方法もあるが、既知のエピ
タキシヤル成長は一般に1000℃以上の高温で行う
ためシリコン基板中の酸素の析出核(内部欠陥
核)が溶解してしまい、内部欠陥密度を上げるこ
とには限界があつた。 There is also a method of using epitaxial wafers to remove surface defects, but since known epitaxial growth is generally performed at high temperatures of 1000°C or higher, oxygen precipitated nuclei (internal defect nuclei) in the silicon substrate are dissolved. Therefore, there was a limit to increasing the internal defect density.
第1図は、従来の製造方法を用いた場合のシリ
コンウエハーの断面図である。先ず、シリコン結
晶中の酸素濃度が18×1017cm-3、アンチモンの濃
度が1×1015cm-3のN型基板1を用意する(第1
図a)。その後、半導体素子を形成するための
種々の熱処理を経ることによりシリコン基板1に
は酸素起因の内部欠陥2、および表面欠陥3が形
成されてしまう(第1図b)。 FIG. 1 is a cross-sectional view of a silicon wafer using a conventional manufacturing method. First, an N-type substrate 1 in which the oxygen concentration in the silicon crystal is 18×10 17 cm -3 and the antimony concentration is 1×10 15 cm -3 is prepared (first
Diagram a). Thereafter, internal defects 2 and surface defects 3 caused by oxygen are formed in the silicon substrate 1 through various heat treatments for forming a semiconductor element (FIG. 1b).
第2図は、表面欠陥を除去するためIG処理を
施した場合のシリコンウエハの断面図である。例
えば、シリコン結晶中の酸素の濃度が19×1017cm
-3、アンチモンの濃度が1×1015cm-3のN型基板
4を用意する(第2図a)。先ず、1200℃の温度
で3時間の熱処理を施しシリコン基板4表面の酸
素を外方拡散させ表面付近の酸素の濃度を下げさ
らに750℃の温度で10時間の熱処理を施し内部欠
陥核5を成長させる(第2図b)。しかるのち半
導体素子を形成するための種々の熱処理を経るこ
とにより、シリコン基板4中に内部欠陥6が形成
される(第2図c)。本例の場合シリコン結晶中
の酸素濃度が高いためにシリコン基板4の表面に
まで欠陥7が到達してしまう。 FIG. 2 is a cross-sectional view of a silicon wafer subjected to IG treatment to remove surface defects. For example, the concentration of oxygen in a silicon crystal is 19× 10 cm
-3 , and an N-type substrate 4 having an antimony concentration of 1×10 15 cm -3 is prepared (FIG. 2a). First, heat treatment is performed at a temperature of 1200°C for 3 hours to diffuse oxygen on the surface of the silicon substrate 4 outward, lowering the concentration of oxygen near the surface.Furthermore, heat treatment is performed at a temperature of 750°C for 10 hours to grow internal defect nuclei 5. (Figure 2b). Thereafter, internal defects 6 are formed in the silicon substrate 4 by various heat treatments for forming a semiconductor element (FIG. 2c). In this example, the defects 7 reach the surface of the silicon substrate 4 because the oxygen concentration in the silicon crystal is high.
一般的に、半導体素子を形成するための熱処理
が高温、長時間になるに従い、あるいはシリコン
基板中の酸素の濃度が極度に高い場合には表面に
まで内部欠陥が伸張してくることがある。また、
酸素濃度が低すぎる場合には、内部欠陥が形成さ
れないことがある。いずれにしろ適当な酸素濃度
IG処理を選択する必要があり、選択を誤ると、
製品のリーク電流を引き起こす原因となつてい
る。 Generally, as the heat treatment for forming semiconductor elements becomes high temperature and long, or when the concentration of oxygen in the silicon substrate is extremely high, internal defects may extend to the surface. Also,
If the oxygen concentration is too low, internal defects may not form. In any case, appropriate oxygen concentration
You need to select IG processing, and if you choose incorrectly,
This causes product leakage current.
第3図は、IG技術と同様に表面欠陥を除去す
る技術であるエピタキシヤルウエハを使つた場合
のシリコン基板と、エピタキシヤル層の断面図で
ある。 FIG. 3 is a cross-sectional view of a silicon substrate and an epitaxial layer when an epitaxial wafer is used, which is a technique for removing surface defects similar to the IG technique.
先ず、例えば、酸素濃度が16×1017cm-3、アン
チモンの濃度が1×1015cm-3のN型シリコン基板
8を用意する(第3図a)。次に既知の方法例え
ば四塩化シリコンを使用し1170℃で厚さ10μ比抵
抗5ΩcmのN型シリコン結晶9をエピタキシヤル
成長する(第3図b)。しかるときシリコン基板
の酸素析出核(内部欠陥核)は溶解してその密度
は非常に少なくなつてしまう。次に半導体素子形
成のための熱処理を施すことによりエピタキシヤ
ル層9には酸素が含まれていないので無欠陥層と
なるが、シリコン基板8にも内部欠陥は形成され
ない(第3図c)。もしくは、極く僅かに形成さ
れるだけであり、ゲツタリング効果がなく汚染に
対して弱く製品のリーク電流を引き起こす。 First, for example, an N-type silicon substrate 8 having an oxygen concentration of 16×10 17 cm -3 and an antimony concentration of 1×10 15 cm -3 is prepared (FIG. 3a). Next, an N-type silicon crystal 9 having a thickness of 10 .mu.m and a resistivity of 5 .OMEGA.cm is epitaxially grown at 1170.degree. C. using a known method, for example, using silicon tetrachloride (FIG. 3b). At that time, the oxygen precipitated nuclei (internal defect nuclei) in the silicon substrate dissolve and their density becomes extremely low. Next, by performing a heat treatment for forming a semiconductor element, the epitaxial layer 9 becomes a defect-free layer since it does not contain oxygen, and no internal defects are formed in the silicon substrate 8 (FIG. 3c). Alternatively, it is only formed in a very small amount, has no gettering effect, is susceptible to contamination, and causes product leakage current.
以上のように、従来の方法では半導体素子形成
のための熱履歴に合せて酸素濃度、内部欠陥形成
のための熱処理を選択する必要があつた。極く僅
かでも最適値をはずれるとシリコン基板表面にま
で欠陥が発生してしまつたり、ゲツタリング効果
がなくなつてしまい半導体素子を劣化させ歩留り
の低下、品質の低下を招く問題があつた。 As described above, in the conventional method, it was necessary to select the oxygen concentration and the heat treatment for forming internal defects according to the thermal history for forming the semiconductor element. If even a slight deviation from the optimum value occurs, defects may occur even on the surface of the silicon substrate, or the gettering effect may be lost, leading to deterioration of the semiconductor element, leading to a decrease in yield and quality.
本発明は上記欠点を除き、特にシリコン結晶に
含まれる酸素の濃度を〔Oi〕、ボロンの濃度を
〔B〕、N型不純物の濃度を〔D〕としたとき
〔D〕>〔B〕≧〔Oi〕≧14×1017cm-3のN型基板にシ
リコンエピタキシヤル結晶を成長し、デバイスプ
ロセスを経るだけで基板には極めて高密度の内部
欠陥が形成されエピタキシヤル層およびエピタキ
シヤル層表面には欠陥が形成されることなく半導
体素子のリーク電流を極めて低く抑える事ができ
半導体素子の劣化を防ぎ高歩留り高品質の半導体
装置を得ることができる。 The present invention eliminates the above-mentioned drawbacks, and in particular, when the concentration of oxygen contained in the silicon crystal is [Oi], the concentration of boron is [B], and the concentration of N-type impurity is [D], [D]>[B]≧ [Oi]≧14×10 17 cm -3 Silicon epitaxial crystal is grown on an N-type substrate, and by simply going through the device process, an extremely high density of internal defects is formed on the substrate, and the epitaxial layer and the surface of the epitaxial layer are The leakage current of the semiconductor element can be suppressed to an extremely low level without the formation of defects, and deterioration of the semiconductor element can be prevented and a high-yield, high-quality semiconductor device can be obtained.
本発明はシリコン結晶中の酸素の濃度を
〔Oi〕、ボロンの濃度を〔B〕とすると、〔B〕≧
〔Oi〕≧14×1017としたときシリコン結晶中に極め
て高密度の内部欠陥が形成され易いことを見出し
た。しかしN型シリコン結晶を必要とする半導体
装置にはこのままでは適用できないがN型不純物
の濃度を〔D〕として〔D〕>〔B〕≧〔Oi〕≧14×
1017とすることで適用可となる。 In the present invention, when the concentration of oxygen in the silicon crystal is [Oi] and the concentration of boron is [B], [B]≧
It has been found that when [Oi]≧14×10 17, extremely high density internal defects are likely to be formed in the silicon crystal. However, it cannot be applied as is to semiconductor devices that require N-type silicon crystal, but if the concentration of N-type impurity is [D], [D]>[B]≧[Oi]≧14×
It becomes applicable by setting 10 to 17 .
本発明の製造方法は、シリコン結晶中に含まれ
る酸素の濃度を〔Oi〕、ボロンの濃度を〔B〕、
N型不純物の濃度を〔D〕としたとき〔D〕>
〔B〕≧〔Oi〕≧14×1017cm-3のN型基板上にシリコ
ンエピタキシヤル結晶を成長する工程と、該シリ
コンエピタキシヤル結晶に半導体装置を構成する
素子を形成する工程とを含むことを特徴とするも
のである。 In the manufacturing method of the present invention, the concentration of oxygen contained in the silicon crystal is [Oi], the concentration of boron is [B],
When the concentration of N-type impurity is [D], [D]>
[B] ≧ [Oi] ≧ 14 × 10 17 cm -3 Includes a step of growing a silicon epitaxial crystal on an N-type substrate, and a step of forming an element constituting a semiconductor device on the silicon epitaxial crystal. It is characterized by this.
以下実施例に基づき本発明を詳細に説明する。 The present invention will be described in detail below based on Examples.
第4図は本発明の方法を実施した場合のシリコ
ン基板およびシリコンエピタキシヤル層の断面図
である。まず、例えば酸素の濃度が15×1017cm
-3、ボロンの濃度が3×1018cm-3、アンチモンの
濃度が6×1018cm-3のN型シリコン基板10を用
意する(第4図a)。次に既知の方法で、例えば
四塩化シリコンを使用し1170℃の温度で厚さ
10μm、比抵抗5Ω−cmのN型シリコン結晶11
を成長する(第4図b)。次に半導体素子を形成
するための工程を経る(第4図c)。しかる時に
は各種熱処理が加えられるのでN型基板10内に
内部欠陥12が形成される。このとき〔B〕≧
〔Oi〕≧14×1017cm-3であるためにエピタキシヤル
ウエハにもかかわらず極めて高密度に内部欠陥1
2が形成される。また、エピタキシヤル層11は
酸素が含まれていないので内部欠陥は発生せず半
導体素子形成領域(エピタキシヤル層11)は完
全な無欠陥層とできる。 FIG. 4 is a cross-sectional view of a silicon substrate and a silicon epitaxial layer when the method of the present invention is carried out. First, for example, the concentration of oxygen is 15 × 10 cm
-3 , an N-type silicon substrate 10 having a boron concentration of 3×10 18 cm -3 and an antimony concentration of 6×10 18 cm -3 is prepared (FIG. 4a). Then, in a known manner, for example using silicon tetrachloride and at a temperature of 1170°C, the thickness is
N-type silicon crystal 11 with a resistivity of 10 μm and a resistivity of 5 Ω-cm
(Figure 4b). Next, a process for forming a semiconductor element is performed (FIG. 4c). At such times, various heat treatments are applied, so that internal defects 12 are formed in the N-type substrate 10. At this time [B]≧
[Oi]≧14×10 17 cm -3 , so even though it is an epitaxial wafer, internal defects 1 are extremely dense.
2 is formed. Furthermore, since the epitaxial layer 11 does not contain oxygen, no internal defects occur and the semiconductor element forming region (epitaxial layer 11) can be a completely defect-free layer.
なお、上記実施例の説明はシリコン基板中の酸
素の濃度〔Oi〕=15×1017cm-3、ボロンの濃度
〔B〕=3×18cm、アンチモンの濃度〔D〕=6×
1018であるが〔D〕>〔B〕≧〔Oi〕≧14×1017であ
れば良い。また、エピタキシヤル成長方法、成長
層の厚さおよび比抵抗は問わない。 The above embodiment is explained based on the following conditions: oxygen concentration [Oi] in the silicon substrate = 15 x 10 17 cm -3 , boron concentration [B] = 3 x 18 cm, and antimony concentration [D] = 6 x
10 18 , but it is sufficient if [D]>[B]≧[Oi]≧14× 1017 . Further, the epitaxial growth method, the thickness and specific resistance of the grown layer are not limited.
以上詳細に説明したように本発明によれば、表
面無欠陥層を確実に形成でき、内部欠陥は極めて
高密度に形成できると共にプロセスの許容範囲が
広くなり、形成した半導体素子のリーク電流を極
めて低くおさえることができ、高歩留り、高品質
の半導体装置を得ることができる。 As explained in detail above, according to the present invention, a surface defect-free layer can be reliably formed, internal defects can be formed at an extremely high density, the process tolerance is widened, and the leakage current of the formed semiconductor element can be extremely reduced. The cost can be kept low, and a high yield and high quality semiconductor device can be obtained.
第1図a〜b、第2図a〜c及び第3図a〜c
は従来の製造方法による主要工程概略断面図、第
4図a〜cは本発明の一実施例による製造方法の
主要工程概略断面図である。
1,4,8,10……シリコン基板、2,6,
12……内部欠陥、3,7……表面欠陥、5……
内部欠陥核、9,11……エピタキシヤル結晶。
Figure 1 a-b, Figure 2 a-c and Figure 3 a-c
4A to 4C are schematic cross-sectional views of main steps in a conventional manufacturing method, and FIGS. 4A to 4C are schematic cross-sectional views of main steps in a manufacturing method according to an embodiment of the present invention. 1, 4, 8, 10... silicon substrate, 2, 6,
12...Internal defect, 3,7...Surface defect, 5...
Internal defect nucleus, 9, 11...Epitaxial crystal.
Claims (1)
〔Oi〕、ボロンの濃度を〔B〕、N型不純物の濃度
を〔D〕と表わしたとき、〔D〕>〔B〕≧〔Oi〕≧
14×1017cm-3のN型基板上にシリコンエピタキシ
ヤル結晶を成長させる工程と、該シリコンエピタ
キシヤル結晶に半導体装置を構成する素子を形成
する工程とを含むことを特徴とする半導体装置の
製造方法。[Claims] 1. When the concentration of oxygen contained in a silicon crystal is expressed as [Oi], the concentration of boron as [B], and the concentration of N-type impurity as [D], [D]>[B] ≧〔Oi〕≧
A semiconductor device comprising the steps of growing a silicon epitaxial crystal on an N-type substrate of 14×10 17 cm -3 and forming an element constituting the semiconductor device on the silicon epitaxial crystal. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16445482A JPS5954220A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16445482A JPS5954220A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5954220A JPS5954220A (en) | 1984-03-29 |
JPS6312376B2 true JPS6312376B2 (en) | 1988-03-18 |
Family
ID=15793477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16445482A Granted JPS5954220A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5954220A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63104322A (en) * | 1986-10-21 | 1988-05-09 | Toshiba Corp | Epitaxial wafer |
JP2725460B2 (en) * | 1991-01-22 | 1998-03-11 | 日本電気株式会社 | Manufacturing method of epitaxial wafer |
JP3384506B2 (en) * | 1993-03-30 | 2003-03-10 | ソニー株式会社 | Semiconductor substrate manufacturing method |
JP5637871B2 (en) | 2011-01-13 | 2014-12-10 | 株式会社椿本チエイン | Conveyor chain |
-
1982
- 1982-09-21 JP JP16445482A patent/JPS5954220A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5954220A (en) | 1984-03-29 |
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