JPS63104322A - Epitaxial wafer - Google Patents
Epitaxial waferInfo
- Publication number
- JPS63104322A JPS63104322A JP25025586A JP25025586A JPS63104322A JP S63104322 A JPS63104322 A JP S63104322A JP 25025586 A JP25025586 A JP 25025586A JP 25025586 A JP25025586 A JP 25025586A JP S63104322 A JPS63104322 A JP S63104322A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- lifetime
- epitaxial
- layer
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 9
- 229910052742 iron Inorganic materials 0.000 abstract description 4
- 229910052804 chromium Inorganic materials 0.000 abstract description 3
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 21
- 239000007789 gas Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産！Ｊとの利用分野）
本発明は、１ピタ４−シャル気相成艮法によってシリコ
ンウェーハの表面にエピタキシャル位を付若ざぜたエピ
タギシャルシリコンウェーハに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Application with Production!J) The present invention relates to an epitaxial silicon wafer in which an epitaxial position is added to the surface of the silicon wafer by a 1-pitch vapor deposition method.
（従来の技術）
シリコノウ１−ハの表面にエピタキシャル層を付着させ
る方法としては、通常エビタギシレル気相成長法が用い
られている。このエピタキシャル気相成長法は、石英ガ
ラス製の反応管内にナセブターを置き、この上に半導体
基板を成せた後、まず、反応管内にＨ２ガスを流し、反
応管の外部に配設された高周波二」イルによって基板を
高温（約１１００〜１２００℃》に加熱し、次に、３：
（板をこの温度に保持しながら、Ｈ２にＨＣｌを加えた
混合ガスを流して基板の表面を数ミクロン気相−ロッチ
ングした後、Ｈ２とＨＣｊとの混合ガスを止め、ＳｉＣ
ｌ２と１４２との混合ガス等の反応ガスを流して基板に
半導体（例えばＳｉ）をエピタキシャル成長させるもの
である。(Prior Art) As a method for depositing an epitaxial layer on the surface of the silicon layer 1-c, the vapor phase epitaxy method is usually used. In this epitaxial vapor phase growth method, a quartz glass reactor is placed inside a reaction tube, and a semiconductor substrate is formed on this. First, H2 gas is flowed into the reaction tube, and a high frequency The substrate is heated to a high temperature (approximately 1,100 to 1,200 degrees Celsius) by heating, and then 3:
(While keeping the board at this temperature, a mixed gas of H2 and HCl was flowed to create a few micron gas-phase locking on the surface of the substrate, then the mixed gas of H2 and HCj was stopped, and the SiC
A reactive gas such as a mixed gas of 12 and 142 is flowed to epitaxially grow a semiconductor (for example, Si) on a substrate.
（発明が解決しようとする問題点）
しかしながら、低抵抗率のＮ形シリコンウェーハからな
る基板を使用してエビタキシ１・ル苦を形成する時、酸
素温度が１．２ｘ １０ ａｔｏｍ／ ｃｍ ３以下
のシリコンウェーハにおいては基板中の転移密度が小さ
いために基板にエピタキシトル層中の重金属（Ｆｅ 、
Ｎｉ 、Ｃｒ等）かびツタリングされにくく、このため
エピタキシトル層の転移密度が下がりにくいのでライフ
タイムを長くし得ない。従って、このシリコンウェーハ
から作られた素子は動作速度が遅いという欠点がある。(Problems to be Solved by the Invention) However, when forming an epitaxial layer using a substrate made of a low resistivity N-type silicon wafer, the oxygen temperature is lower than 1.2 x 10 atoms/cm3. In silicon wafers, heavy metals (Fe, Fe,
(Ni, Cr, etc.) is difficult to cause mold and ivy, and therefore the dislocation density of the epitaxial layer is difficult to reduce, making it impossible to lengthen the lifetime. Therefore, devices made from silicon wafers have the disadvantage of slow operating speed.
本発明の目的は、低抵抗率のＮ形シリコン単結晶ウェー
ハから製造される従来のエピタキシャルウェーハが有す
る以上の欠点を取り除き、良好な動作速度を有するＬＳ
Ｉ素子に供し得るエピター１；シャルウニー八を提供す
ることにある。It is an object of the present invention to eliminate the disadvantages of conventional epitaxial wafers manufactured from N-type silicon single crystal wafers with low resistivity, and to provide an LS with good operating speed.
The object of the present invention is to provide an epiter (1) that can be used for an I element.
（問題点を解決するための手Ｉ”２）
本発明の前記目的は、次の構成によって達成される。即
Ｉ５、本発明の構成は、抵抗率が０．１Ωｃｍ以下であ
ると共に酸素濃度が１．２Ｘ １０１８〜２．Ｏ×１０
ａｔＯｍ／＋ＩＲ” Ｎ形シリコン単結晶つェーへ
にエピタキシャル層を付着させたエピタキシャルウェー
ハである。(Measures for solving the problem I"2) The above object of the present invention is achieved by the following configuration. In other words, I5, the configuration of the present invention has a resistivity of 0.1 Ωcm or less and an oxygen concentration of 1.2X 1018~2.Ox10
atOm/+IR” This is an epitaxial wafer in which an epitaxial layer is attached to an N-type silicon single crystal wafer.
（作用）
半導体中で電流となるキャリアは、熱エネルギ、光エネ
ルギによって生起され、不純物、格子欠陥等に衝突する
と消滅する。ライフタイムとは各キャリアの生起から消
滅までの平均時間をいい、転移密度が大きく格子欠陥が
多いとそれだけキトリアが格子欠陥に衝突し安くなるた
め、キャリアのライフタイムは短くなる。一方、半導体
中の電子が動く速さは電界の強さとｅτ／２ｍ＊に比例
しくＣは電子の１１荷、τはライフタイム、ｍ＊は電子
の右効買量を示す）、ライフタイムが長ければ電子が早
く動きそれだけ信号の伝達時間が短くなって結局は素子
の動作速度が速くなる。逆に、ライフタイムが短いシリ
コンウェーハは、そのシリコンウェーハによって製造し
た素子の動作速度が遅くなり、超ＬＳＩには使用し得な
くなる。(Function) Carriers that become current in a semiconductor are generated by thermal energy or light energy, and disappear when they collide with impurities, lattice defects, etc. Lifetime refers to the average time from generation to disappearance of each carrier, and the higher the dislocation density and the greater the number of lattice defects, the more chytria collides with the lattice defects and becomes cheaper, so the carrier lifetime becomes shorter. On the other hand, the speed at which electrons move in a semiconductor is proportional to the strength of the electric field and eτ/2m* (where C is the 11 charge of the electron, τ is the lifetime, and m* is the right-handed purchase amount of the electron), and the lifetime is The longer it is, the faster the electrons move, the shorter the signal transmission time, and the faster the device operates. Conversely, a silicon wafer with a short lifetime will cause the operating speed of devices manufactured using the silicon wafer to be slow, making it impossible to use it for VLSI.
本発明のエピタキシャルウェーハは、抵抗率が０．１Ω
口以下であると共に酸素濃度が１．２Ｘ １０１８〜２
．０×１０１８ ａｔｏｍ／ｃｍ３Ｎ形シリコン単結
晶つ工−ハにエピタキシャル層を付着させているが故に
、基板中に転移を発生させ得るので基板にエピタキシャ
ル層中の重金属（Ｆｅ 、Ｎｉ 、Ｃｒ等）がブックリ
ングされ易く、このためエピタキシャル層の転移密度が
下がり易いのでエピタキシャル層のライフタイムを長り
シ得る。The epitaxial wafer of the present invention has a resistivity of 0.1Ω.
The oxygen concentration is 1.2X 1018~2
．． Since the epitaxial layer is attached to a 0x1018 atom/cm3 N-type silicon single crystal substrate, heavy metals (Fe, Ni, Cr, etc.) in the epitaxial layer may cause dislocation in the substrate. The epitaxial layer is easily booked, and therefore the dislocation density of the epitaxial layer is likely to be reduced, so that the lifetime of the epitaxial layer can be extended.
因みに、エピタキシャル成長時において、酸素濃度が１
．２Ｘ １０ ａｔｏＩｎ／ ｃｍ ”以下のシリコ
ンウェーハでは、前述と逆の理由でエピタキシトル層の
ライフタイムを長くし得ず、酸素濃度が２．０×１０１
８１８ａｔＯｍ／ｃｍ３以上のシリコンウェーハでは基
板内の転移密度が必要以上に増大化し易く、エピタキシ
ャル層まで転移が波及する。このため、エピタキシトル
層中の転移密度も増大し、エピタキシャル層のライフタ
イムが短くなる。Incidentally, during epitaxial growth, the oxygen concentration is 1
．． In silicon wafers with a diameter of 2X 10 atoIn/cm or less, the lifetime of the epitaxial layer cannot be extended for the opposite reason to the above, and the oxygen concentration is 2.0 × 101
In silicon wafers with a density of 818 atOm/cm3 or more, the dislocation density within the substrate tends to increase more than necessary, and the dislocations spread to the epitaxial layer. Therefore, the dislocation density in the epitaxial layer also increases, and the lifetime of the epitaxial layer becomes shorter.
また、エピタキシトル層長を施す前に、シリコンウェー
ハ内部に格子欠陥を生起するための熱処理を行なえば、
大きなゲッタリング効果が得られ、エピタキシャル成長
時にエピタキシャル層の転移密度を低クシ１ワ、エピタ
キシャル層のライフタイムを長くし得る。In addition, if heat treatment is performed to generate lattice defects inside the silicon wafer before applying the epitaxial layer length,
A large gettering effect can be obtained, the dislocation density of the epitaxial layer can be lowered during epitaxial growth, and the lifetime of the epitaxial layer can be extended.
（具体例）
抵抗率０．０１Ωｃｍであって酸素濃度ｅｘ １１０１
７ａｔｏ／ｃ＃＋３のＮ形シリコン単結晶つェーハ群Ａ
と、抵抗率０，０１Ωｃｍであって酸素濃度１．４ｘ
１１０１８ａｔｏ／Ｃｌ１１３のＮ形シリコン単結晶つ
ェーハ群Ｂを同時にエビタギシャル成長を行なった後、
同時に２５６ＫＤＲＡＭの製造工程において、２５６Ｋ
Ｄ ＲＡ Ｍ素子を製造したところ、ウェーハ群Ａ
の歩留りは９．７％であったのに対し、ウェーハ群Ｂの
歩留りは５２．３％であった。この結果を表にすると次
のようになる。(Specific example) Resistivity 0.01Ωcm and oxygen concentration ex 1101
7ato/c#+3 N-type silicon single crystal wafer group A
And the resistivity is 0.01Ωcm and the oxygen concentration is 1.4x.
After simultaneously growing the N-type silicon single crystal Zeha group B of 11018ato/Cl113,
At the same time, in the manufacturing process of 256K DRAM, 256K
When DRAM devices were manufactured, wafer group A
The yield of wafer group B was 9.7%, while the yield of wafer group B was 52.3%. The results are tabulated as follows.
表
因みに、前述の歩留りは、検査に合格した素子数を前述
の製造工程に流した素子数で除した値の％表示であり、
この場合、前述の検査は、当該素子によって製作された
ＭＯ３型ダイオードの破壊電圧によって判定される。Incidentally, the above-mentioned yield is expressed as a percentage of the value obtained by dividing the number of devices that passed the inspection by the number of devices sent through the above-mentioned manufacturing process.
In this case, the above-mentioned test is determined by the breakdown voltage of the MO3 type diode manufactured by the device.
（本発明の効果）
本発明のエピタキシャルウェーハは、エピタキシャル層
中の転移密度が低くエピタキシャル層のライフタイムが
長いため、超ＬＳＩ素子用エビタギシャルウェーハとし
て使用し得る。(Effects of the Present Invention) The epitaxial wafer of the present invention has a low dislocation density in the epitaxial layer and a long lifetime of the epitaxial layer, so it can be used as an epitaxial wafer for VLSI devices.
Claims (1)
２×１０＾１＾８〜２．０×１０＾１＾８ａｔｏｍ／ｃ
ｍ＾３のＮ形シリコン単結晶ウェーハにエピタキシャル
層を付着させたエピタキシャルウェーハ。The resistivity is 0.1 Ωcm or less and the oxygen concentration is 1.
2 x 10^1^8 ~ 2.0 x 10^1^8 atom/c
An epitaxial wafer with an epitaxial layer attached to a m^3 N-type silicon single crystal wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25025586A JPS63104322A (en) | 1986-10-21 | 1986-10-21 | Epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25025586A JPS63104322A (en) | 1986-10-21 | 1986-10-21 | Epitaxial wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104322A true JPS63104322A (en) | 1988-05-09 |
Family
ID=17205160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25025586A Pending JPS63104322A (en) | 1986-10-21 | 1986-10-21 | Epitaxial wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104322A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022624A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04192338A (en) * | 1990-11-22 | 1992-07-10 | Toshiba Corp | Insulated-gate field-effect transistor |
| EP0496382A2 (en) * | 1991-01-22 | 1992-07-29 | Nec Corporation | Intrinsic gettering for a semiconducteur epitaxial wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5717125A (en) * | 1980-07-04 | 1982-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5954220A (en) * | 1982-09-21 | 1984-03-29 | Nec Corp | Manufacture of semiconductor device |
| JPS60148127A (en) * | 1984-01-13 | 1985-08-05 | Nec Corp | Manufacture of semiconductor substrate |
-
1986
- 1986-10-21 JP JP25025586A patent/JPS63104322A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5717125A (en) * | 1980-07-04 | 1982-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5954220A (en) * | 1982-09-21 | 1984-03-29 | Nec Corp | Manufacture of semiconductor device |
| JPS60148127A (en) * | 1984-01-13 | 1985-08-05 | Nec Corp | Manufacture of semiconductor substrate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH022624A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH04192338A (en) * | 1990-11-22 | 1992-07-10 | Toshiba Corp | Insulated-gate field-effect transistor |
| EP0496382A2 (en) * | 1991-01-22 | 1992-07-29 | Nec Corporation | Intrinsic gettering for a semiconducteur epitaxial wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3524679B2 (en) | High purity CVD-SiC semiconductor heat treatment member and method of manufacturing the same | |
| JP3381816B2 (en) | Semiconductor substrate manufacturing method | |
| Kunii et al. | Solid-phase epitaxy of CVD amorphous Si film on crystalline Si | |
| JP2006066722A (en) | EPITAXIAL SiC FILM, MANUFACTURING METHOD THEREFOR AND SiC SEMICONDUCTOR DEVICE | |
| JP2010034330A (en) | Epitaxial wafer and method of manufacturing the same | |
| JPWO2003009365A1 (en) | Method for manufacturing silicon wafer, method for manufacturing silicon epitaxial wafer, and silicon epitaxial wafer | |
| JP3915252B2 (en) | Method for manufacturing silicon carbide semiconductor substrate | |
| JPH05291097A (en) | Silicon substrate and manufacture thereof | |
| JPS63104322A (en) | Epitaxial wafer | |
| JP2003151984A (en) | Silicon epitaxial wafer and manufacturing method thereof | |
| JP7231120B2 (en) | Epitaxial wafer manufacturing method | |
| JP4270713B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| JP2014027028A (en) | SiC EPITAXIAL SUBSTRATE MANUFACTURING DEVICE, METHOD FOR MANUFACTURING SiC EPITAXIAL SUBSTRATE, AND SiC EPITAXIAL SUBSTRATE | |
| JP3578396B2 (en) | Semiconductor disk having crystal lattice defects and method of manufacturing the same | |
| JP3888065B2 (en) | Quartz crucible | |
| JP3922674B2 (en) | Silicon wafer manufacturing method | |
| JP2739469B2 (en) | Method for growing SiC film | |
| CN112885708B (en) | Preparation method of silicon carbide homoepitaxial material | |
| JPH02260521A (en) | Article having polycrystalline si semiconductor thin film and manufacture thereof | |
| JPS63116420A (en) | Semiconductor substrate | |
| JPH10209055A (en) | Thin film epitaxial wafer and manufacturing method of the same | |
| JPS6012775B2 (en) | Method for forming a single crystal semiconductor layer on a foreign substrate | |
| JPH0521303A (en) | Semiconductor substrate and manufacture thereof | |
| CN115295412A (en) | High-temperature rapid heat treatment process and device for silicon carbide device | |
| Yang et al. | Defects and Impurities in Silicon Materials |