JPS60245235A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid deterioration in quality of epitaxial layer through high temperature heat processing by forming an N type impurity layer on a semiconductor substrate and executing, after forming an N type epitaxial layer thereon, the heat processings at a low and an intermediate temperature. CONSTITUTION:An N<+> type impurity diffusion layers 2a, 2b are formed on a CZ, N type semiconductor substrate 1 by thermal diffusion of Sb and an N type epitaxial layer 3 is formed thereon in the thickness of 15mum by the epitaxial growth method. A fault 4 is formed by executing heat processings for 30hr at 700 deg.C (low temperature) and 6hr at 1,000 deg.C (intermediate temperature). Such heat processings at low and intermediate temperature lowers oxygen concentration on the substrate 1 and reduces surface diffusion of oxygen by high temperature heat processing. As a result, oxygen concentration of epitaxial layer 3 does not exceed a critical value for generation of fault and the epitaxial layer is held as the faultfree region showing lesser change of resistivity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor devices, and provides a high quality N-type shrimp wafer.

Conventional Structure and Problems Generally, N-type Si substrates are often used in -eMos and the like. However, in the case of substrates manufactured using the normal C2 method, convection of the raw material melt occurs during crystal pulling.

Concentric impurity concentration unevenness occurs within the wafer surface. This variation is about ±8% according to the S, R, method. Currently, this is not so much of a problem for devices with gate lengths of 2 μm or more, but in the near future, as device integration increases and gate lengths become submicron.
Problems such as affecting variations in threshold voltage will likely come to light. However, even this degree of resistivity variation is perceived as fixed pattern noise in solid-state imaging devices that are sensitive to Si crystal quality, and is a factor in deteriorating image quality.

To solve this problem, Ebiwa, which has no periodic impurity distribution within the substrate plane, is optimal. But 2 normal - 0 MO
N/N as a latch-up countermeasure used in 8.
When applied to the shrimp wafer 10 MOs process, defects occur on one surface, causing deterioration of device characteristics. Particularly in solid-state imaging devices, the above-mentioned defects become white scratches and cause a significant decrease in yield. This is because supersaturated oxygen contained in the shrimp substrate diffuses into the epitaxial layer due to the high temperature heat treatment. As a countermeasure for this, we use the so-called intrinsic on the shrimp board.

It has been found that it is sufficient to perform gettering (IC) treatment to lower the oxygen concentration of the substrate.

However, at present, in CZ and N type substrates.

Experimental results have shown that sufficient treatment is difficult for substrates with high impurity concentrations, especially highly doped sb substrates.

An N-type substrate on which pIcr is effective, that is, on which a high density of bulk defects can be easily generated, has a resistivity of 1 to several tens of ohms and is P-doped.

Therefore, the corner quality N/N+ does not deteriorate even with high-temperature heat treatment to prevent latte-up required for CMOS.
Shrimp wafers are desired.

Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned drawbacks, and provides a method for manufacturing a semiconductor device that has a highly concentrated impurity layer on the substrate and does not cause quality deterioration of the epitaxial layer due to high-temperature heat treatment. It is something to do.

Structure of the Invention The present invention provides a high concentration N2! ! ! Forms an impurity layer.

After forming an N-type epitaxial layer thereon, 600
1 to several tens of hours at ~80o0C, 1. This is a method for manufacturing a semiconductor device that includes a step of performing OOo'c processing for several hours or more.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention.

CZ, N-type semiconductor substrate 1 is formed with N-impurity diffusion layers 2a, 2b by SbO thermal diffusion, or by ion implantation, and an N-type epitaxial layer 3 is formed thereon. is grown to 16 μm.

and -700'C, 30 hours (low temperature) and 1000°C
Defect 4 was removed by heat treatment for 16 hours (medium temperature).
form. Note that the low-temperature treatment conditions are fluid, as they are controlled by the history of the interstitial oxygen concentration, the wax pulling conditions, etc., as well as the temperature for one hour.

Even if the semiconductor device is subjected to heat treatment at 11200 DEG C. for 26 hours, the defects found near the surface of the epitaxial layer 3 after high-temperature heat treatment, which were a problem in the conventional example, no longer occur. This is because by performing the heat treatment at low and medium temperatures, defects 4 in which oxygen is precipitated only in the semiconductor substrate 1 are formed, thereby reducing the interstitial oxygen concentration. 7. direction.

In the 10H impurity region 2a, defects are less likely to occur than in the inside of the substrate 1, but since the thickness is as thin as 6 to 10 μm, the amount of oxygen contained therein is smaller than that in the substrate 1. As described above, the oxygen concentration of the two substrates 1 was lowered, and the amount of surface diffusion of oxygen due to the high-temperature heat treatment was able to be reduced. As a result, the oxygen concentration in the epitaxial layer 3 does not exceed the defect generation critical value, and the epitaxial layer 3 is maintained as a defect-free region with little change in resistivity.

Although the cross-sectional structure is fd N/N /N, it is no different from an N/N Ehiwafer as a measure against CMOS latch-up.

In addition, a high concentration impurity layer is provided below the epitaxial layer 3, and in combination with the defect region therebelow, a large gettering effect can be expected. The concentration of the high concentration impurity layer can be freely controlled according to the characteristics of the device and the thickness of the shrimp film. Furthermore, compared to CZ, N-type wafers, and N/N shrimp wafers, a potential barrier is created between the shrimp layer, which is one active layer, and the substrate by the N impurity diffusion layer 2a.

It becomes difficult for condensed signals from the bulk to mix in. Also.

As shown in FIG. 2, when performing die pounding on the back contact electrode 7, if the conductive paste 6 wraps around the side surface of the semiconductor device 6 and comes into contact with the soapy impurity layer 2a, N/N Electrical contact is improved compared to shrimp wafers, etc. Note that the N impurity layer is As'(H
A similar effect can be obtained when forming using the same method.

Effects of the Invention As described above, the method for manufacturing a semiconductor device of the present invention eliminates the periodic distribution of resistivity in the active layer, prevents the influence of oxygen contained in the shrimp substrate, and furthermore eliminates the effect of high concentration impurities in the substrate. This can also be expected to sufficiently ensure the quality of semiconductor devices required when increasing the density of elements.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention, and FIG. 2 is a schematic cross-sectional view when the semiconductor device according to the present invention is mounted on a die. 1...CZ, N-type semiconductor substrate-2a, 2b...
...1N impurity layer, 3...N type epitaxial layer, 4
... Bulk defect, 5 ... Conductive paste,
6...Crunchy conductor device, 7...Back contact electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1゜Figure 2

Claims (1)

[Claims] A step of forming a highly concentrated N-type impurity layer on an N-type semiconductor substrate with a CZ having a specific resistance of 1 to several tens of Ω; a step of forming an epitaxial layer of the same conductivity type as the semiconductor substrate; A method for manufacturing a semiconductor device, comprising a process of processing at 800°C for one to several tens of hours, and a process of processing at about 1000°C for several hours or more.