JPS6066857A - Manufacture of solid-state image pickup element - Google Patents
Manufacture of solid-state image pickup elementInfo
- Publication number
- JPS6066857A JPS6066857A JP58175466A JP17546683A JPS6066857A JP S6066857 A JPS6066857 A JP S6066857A JP 58175466 A JP58175466 A JP 58175466A JP 17546683 A JP17546683 A JP 17546683A JP S6066857 A JPS6066857 A JP S6066857A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type
- solid
- atmosphere
- rare gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 9
- 238000003384 imaging method Methods 0.000 claims description 12
- 230000007547 defect Effects 0.000 abstract description 15
- 238000011282 treatment Methods 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract 2
- 238000005247 gettering Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000001629 suppression Effects 0.000 description 3
- 241000238557 Decapoda Species 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 241001662103 Cryptocarya corrugata Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】 l”(−業」二の利用外gff 本発明は撮像素子の製造方法に関するものである。[Detailed description of the invention] gff The present invention relates to a method of manufacturing an image sensor.
i+7−来例の構成どその問題点
縦型オーバーフロードレイン(以1” V−OFDとよ
ぶ)構造固体撮像素子1−J:固体撮1す−イ、子の残
された問題点である耐ブルーミング抑制能方向上、スミ
ア低減に有力な構造で、小型化あるいは高密度化に適し
ていることから固体撮像集子の標べ11溝造となりつつ
ある。i+7-Problems with the previous configuration Vertical overflow drain (hereinafter referred to as 1" V-OFD) structure solid-state image sensor 1-J: Solid-state image sensor 1-i, anti-blooming, which is a remaining problem In terms of suppression ability, the 11-groove structure is becoming the standard for solid-state imaging collectors because it is effective in reducing smear and is suitable for miniaturization or high density.
以下図面を参照しながら、従来のV −OF D477
7造固体撮像素子について説明を行う。第1図υ:J2
従来のV−OFD構造固体撮像素子の断面概略図を示す
ものである。同図において、1は出発材不1であるN型
Si基板、2はN型Si基板1にイオン注入、ドライブ
インで形成した固体撮保斗5子の能動領域となるP型ウ
ェル、v(d N J<+2 S L基板1 k(二印
加する正電圧である。以上の構;:’Htt二」′、・
いて、”:1ずV−OF D構造固体撮像素子のブルー
ミング抑制動作はN型Si基板1にVを印加すること
に」:り行なわれる。その時の受光部l:のボデン/ヤ
ルの概略図を第2図に示す。dはホトグイ番−ドN1拡
散層、eはP型ウェルの部分を人1−.、q k−J、
ポテンシャルプロファイルを表す。同図から明らかなよ
うに、N7!i1.!81基板1の比抵抗の違いに、1
:ってP型ウェルの不純物濃度プロファイルが異ナルコ
とにより同図のポテンシャルの山Pの高さが異なる。V
−、OF D固体撮像素子においては山Pの高さがブ
ルーミング抑制能力と直接関係している。With reference to the drawings below, the conventional V-OF D477
The 7-Series solid-state image sensor will be explained. Figure 1 υ: J2
1 is a schematic cross-sectional view of a conventional V-OFD structure solid-state imaging device. In the figure, 1 is an N-type Si substrate which is the starting material 1, 2 is a P-type well which is the active region of the solid-state sensor 5 formed by ion implantation and drive-in into the N-type Si substrate 1, and v( d N J<+2 S L substrate 1 k (2 positive voltages applied. The above structure;:'Htt2'',・
Therefore, the blooming suppression operation of the V-OF D structure solid-state imaging device is performed by applying V to the N-type Si substrate 1. A schematic diagram of the light receiving section l: at that time is shown in FIG. d is the photo-coated N1 diffusion layer, e is the P-type well portion. , q k−J,
Represents a potential profile. As is clear from the figure, N7! i1. ! 81 Due to the difference in resistivity of substrate 1, 1
: The height of the peak P of the potential in the figure differs depending on the impurity concentration profile of the P-type well. V
-, In the OFD solid-state image sensor, the height of the peak P is directly related to the ability to suppress blooming.
)11Pが低いとブルーミング抑制能力が大きくなる。) When 11P is low, the ability to suppress blooming increases.
このことに、IIIPの高さがバラツキつけ0丁、ブル
ーミング抑制能力もバラツクということである。一般に
CZ法によるSi基板eユ製造方法により同一基板内で
10〜15%の同心円状の周期的バラツキを有すること
が知られている。P型つェル形成Qよ面内バラツキの少
ないイオン注入eこ、1:り行なわjするため、P型ウ
ェルの不純物濃度プロファイルシよ基板比抵抗に対応し
/こ形成バラツキを生じる。In addition, there is no variation in the height of IIIP, and there is also variation in blooming suppression ability. Generally, it is known that the Si substrate manufacturing method using the CZ method has a concentric periodic variation of 10 to 15% within the same substrate. Since the ion implantation is performed with less in-plane variation than the P-type well formation Q, the impurity concentration profile of the P-type well has variations in formation corresponding to the substrate resistivity.
その結果、V−OFDを動作させると、基板比抵抗ノ・
うに対応した同心円状の固定パターン雑音が人わiする
。こitによりV−OFD構造固体撮像素−rが本来持
−・ているブルーミング抑制能力を十分に引き出せてい
ないのが現状である。丑だP型つェル形成時の高温熱処
理によりCZ Si ノ+に板中に含寸れる酸素が表面
近傍に拡散し、欠陥を発生させる。これは固体撮像装置
においては画像欠陥である白傷の原因の1つとなる3、
そのため、V−OFD構造固体撮像素子の性能を十分C
(引き出せる素子が強く望丑れていた。As a result, when the V-OFD is operated, the substrate resistivity
The concentric fixed pattern noise that corresponds to the sound is very noticeable. Due to this, the current situation is that the V-OFD structure solid-state image sensor-r is not able to fully utilize its inherent ability to suppress blooming. Due to the high-temperature heat treatment during the formation of the P-type well, the oxygen contained in the CZ Si plate diffuses near the surface, causing defects. This is one of the causes of white scratches, which are image defects in solid-state imaging devices3.
Therefore, the performance of the V-OFD structure solid-state image sensor can be sufficiently improved by C.
(I was really looking forward to the elements that could be drawn out.
発明の目的
本発明は」二組欠点にπ、み、V OFD4g;’、冒
−・1休撮像素子で”/−OFD動作時の国定パターン
卸看″ダ−を防止し、白傷の発生をも防止することを目
的とした固体撮像素子の製造方法を提供するものである
。OBJECTS OF THE INVENTION The present invention prevents the occurrence of white flaws by preventing the occurrence of "national pattern inspection" during OFD operation with a V OFD 4G; The present invention provides a method for manufacturing a solid-state image sensor that also aims to prevent the above problems.
発明の構成
この目的を達成するために、本発明の固体撮像素子の製
造方法はイントリンシックゲッター(以下IGとよぶ)
処理を施したCZN型基根基板上記基板と同程度の比抵
抗のエピタキシャル層を形成し、その内にP型ウェルを
形成することから構成されている。Structure of the Invention In order to achieve this object, the method for manufacturing a solid-state image sensor of the present invention uses an intrinsic getter (hereinafter referred to as IG).
The processed CZN type base substrate is constructed by forming an epitaxial layer having a resistivity comparable to that of the above substrate, and forming a P-type well within the epitaxial layer.
実施例の説明
以下本発明の一実施例について四面を参照しながら説明
する。第3図は本発明の一実施例における半導体装置の
製造方法により形成された概略断面図を示すものである
。同図において31は出発4A利であるN J9jj基
板、35はN型基板31土に形成したN型エビタギシャ
ル層、3AJ、、lN型エピタキシャル層35」二にイ
オン注入、ドライブインにJ:り形成しだ固体撮像装置
、Rの能動領域となるP型ウェル、36ばN型基板31
を後述する熱処理を施すことにより形成した基板内微小
欠陥、37は前記の熱処理により形成した無欠陥領域で
ある。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to its four aspects. FIG. 3 shows a schematic cross-sectional view formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 31 is a starting 4A substrate, 35 is an N-type epitaxial layer formed on the N-type substrate 31, 3AJ, 1N-type epitaxial layer 35'' is ion implanted into the second layer, and J is formed in the drive-in layer. Shida solid-state imaging device, P-type well serving as the active region of R, 36 and N-type substrate 31
37 is a defect-free region formed by the heat treatment described above.
次に、本発明の固体撮像素子の製造方法について説明す
る。Next, a method for manufacturing a solid-state image sensor according to the present invention will be explained.
J、ず比(1(抗1〜数1oΩcmのN型Si〕、じ板
31に第1の工程において、1060℃以上の高n1□
t、花ガス雰囲気中で1〜数十時間、第2の工程におい
て、e o o ”C,〜800℃の低温希ガスあるい
は酸木雰囲気中で1o〜数十時間、第3の工程において
、1o○○℃の中温、希ガス4うるい11酸素雰囲気中
で数時間の熱処理を行う。第1の二ロ呈は基板表面Jニ
リ酸素を外方拡散するだめ、第2の工程は基板31内部
に欠陥36の核形成をさせるため、第3の工程は第2の
工程で形成された欠陥36の核成長をさせるためになさ
れる。次に以上の工程によって出来た酸化膜除去ののち
、基板31と同じ比抵抗のエピタキシャル層を形成し、
次にイオン注入、ドライブインにより固体撮像素子の能
動領域であるP型ウェル32を形成する。J, Z ratio (1 (N-type Si with resistance of 1 to several 10Ωcm)), high n1□ of 1060°C or higher in the first step
t, in a flower gas atmosphere for 1 to several tens of hours, in the second step, e o o "C, in a low-temperature rare gas or acid wood atmosphere at ~800 ° C. for 1 to several tens of hours, in the third step, Heat treatment is performed for several hours at a medium temperature of 1000° C. in a rare gas 4 humid oxygen atmosphere. The third step is performed to allow the defects 36 formed in the second step to grow as nuclei.Next, after removing the oxide film formed by the above steps, the substrate is removed. Form an epitaxial layer with the same resistivity as 31,
Next, a P-type well 32, which is an active region of the solid-state imaging device, is formed by ion implantation and drive-in.
本実施例によれば、周体撮保素−トに要求さJl−る特
性を満たすエピタキシャル層の比抵11+’+:と同じ
比抵抗のGZN型基板を用いるので以下の利点が生じる
。第1にエピタキシャル成長時のオートドープがないた
め、エピタキシャル層の比抵抗制御がなんら喝−別の処
理を施さなくとも芥易にfJ:る。第2にn / n”
−エピウェーハにおいて間:辿と4、る製造プロセスの
熱処理による高濃度基板不純物のエピタキシャル層への
拡散vこ、1:って生じる実効的エピタキシャル層幅の
減少を、8慮する必要がなくなる。According to this embodiment, since a GZN type substrate having the same resistivity as the epitaxial layer 11+'+: which satisfies the characteristics required for a peripheral image sensor is used, the following advantages occur. First, since there is no autodoping during epitaxial growth, the resistivity of the epitaxial layer can be easily controlled without any special treatment. Second n/n”
- There is no need to take into account the reduction in the effective epitaxial layer width that occurs during the epitaxial wafer due to the diffusion of high concentration substrate impurities into the epitaxial layer due to heat treatment during the manufacturing process.
そのため、エピタキシャル層を?i9: <できるので
エビ成長時の熱処理時間を短くてき、エピ族J+ II
:4の誘起欠陥を押えることができるとともに、コスト
而でも有利である。第3にP型つェル形成J11に必夛
な高7114処理によp発生する欠陥を防1にするため
に行う前述の第一、第二、第三〇三工程の熱処理、いわ
ゆるrG処理工程において、N型不純物濃度の高い基板
を用いると基板内部欠陥が形成しにくいことが実験的に
確められた。しかし本発明による比抵抗(1〜数1oΩ
on)の基板を用いると確実に内部欠陥を形成すること
ができ、後のP型つェル形成時のドライブインによって
起こる基板内部酸素が表面に拡f¥& Lエビ層表面近
傍に発生ずる欠陥を確実に防11−できることが実験的
に確認さh/こ。第4Vこエピタキシャル層と基板の比
抵抗が同一 であるかし、基板深さ方向にボテンシャル
勾配をもたない。そのことにより基板内部で発生した擬
似信シシ黴:ポテンシャル差によって活性層内に混入す
ることはない。なおP型基板上にN型ウェルを形成する
場合VCも本発明の方法は当然に実施できる。Therefore, the epitaxial layer? i9: <Since it is possible to shorten the heat treatment time during shrimp growth, it is possible to reduce the heat treatment time during shrimp growth.
:4 induced defects can be suppressed, and it is also advantageous in terms of cost. Thirdly, the heat treatment of the first, second, and 303rd steps described above is carried out in order to prevent defects caused by the high 7114 treatment necessary for P-type well formation J11, the so-called rG treatment. It has been experimentally confirmed that when a substrate with a high concentration of N-type impurities is used in the process, it is difficult to form defects inside the substrate. However, the specific resistance according to the present invention (1 to several 10Ω
By using a substrate of (on), internal defects can be reliably formed, and oxygen inside the substrate caused by drive-in during later P-type well formation will spread to the surface and generate near the surface of the F&L layer. It has been experimentally confirmed that defects can be reliably prevented. The resistivity of the fourth V epitaxial layer and the substrate are the same, and there is no potential gradient in the depth direction of the substrate. As a result, pseudo-magnetic mold generated inside the substrate will not be mixed into the active layer due to the potential difference. Note that the method of the present invention can naturally be applied to VC when an N-type well is formed on a P-type substrate.
1だ実用」一基板とエピタキシャル層の比抵抗の111
11み1″?−ぜは1〜数10Ωmの範1mでは問題に
ならない。1 for practical use” The specific resistance of one substrate and epitaxial layer is 111.
11mm 1''?-ze is not a problem in the range of 1m to several tens of Ωm.
発明の効果
以上のように本発明の固体撮像集子の製造方法によれば
、いわゆるIG処理を施こすことにより、基板内部に欠
陥を発生させ、酸素を欠陥に束縛させることができる。Effects of the Invention As described above, according to the method of manufacturing a solid-state imaging collector of the present invention, by performing the so-called IG treatment, defects can be generated inside the substrate and oxygen can be bound to the defects.
その結果、−、H”’:f!+A処理による表面拡散酸
素濃度を欠陥発生臨界値以1・−にすることができる。As a result, the surface diffused oxygen concentration by the -, H"':f!+A treatment can be reduced to 1.- below the defect generation critical value.
これによって固体撮像装置の白キズの原因である表面欠
陥発生を防止できる。1だP型ウェルをエピタキシャル
層内に形成することにより基板の比延4′)’C分布ム
ラVζ起因する縦型オーバーフロードレイン動作時にお
ける固定パターンク(1音。This can prevent the occurrence of surface defects that cause white scratches on solid-state imaging devices. By forming a P-type well in the epitaxial layer, the substrate ratio 4')'C distribution unevenness Vζ causes a fixed pattern during vertical overflow drain operation.
を防止でき、縦型オーバーフ[ゴードレインイ’:’;
造固体撮像素子の性能を最大限に引き出すことができる
。Vertical overflow can be prevented.
The performance of the solid-state image sensor can be maximized.
第1図は縦型オーバーフロードレイン構造固体撮像素子
の概略断面図、第2同C,ホトダイオード下P型ウェル
のV−OFD動作時のボテンシャルプロファイル、第3
図は木発すJVCJニーで製造さ)7゜た固体撮像、+
、子の概略断面図である。
31・・・・N型シリコン基板、32 ・・・・P型つ
エノペ 35・ −・N型エビタギシャルノ1〈。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図Figure 1 is a schematic cross-sectional view of a solid-state imaging device with a vertical overflow drain structure, Figure 2 is a schematic cross-sectional view of a solid-state imaging device with a vertical overflow drain structure, Figure 2 is a potential profile of the P-type well under the photodiode during V-OFD operation, and Figure 3
The figure is manufactured by JVCJ knee) 7° solid-state imaging, +
, is a schematic cross-sectional view of the child. 31... N-type silicon substrate, 32... P-type Tsuenope 35... N-type Evita Gisharno 1〈. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
板に1060℃以上の温度で、希ガス雰囲気中で1時間
以上熱処理する工程と、600〜SOO°0の〃、11
度で箱ガスあるいは酸素雰囲気中で10時間以上熱処理
する工程と、1000℃の温度で希ガスあるいは酸素雰
囲気中で熱処理を行う工程と、l’l!I ite基板
表面の酸化膜を除去する工程と、1)11記基板−1−
にj)η記基板と同程度の比抵抗のエビタギシャル層を
形成する工程と、前記エビタギシトル層の内に他方;j
’l電型のウェルを形成することを!1に徴とする固体
撮像2(・、子の製造方法。CZ method: A step of heat treating a conductivity type substrate with a specific resistance of 1 to several tens of Ωcm at a temperature of 1060°C or higher in a rare gas atmosphere for 1 hour or more, and a process of 600°C to SOO°0 of 11
A process of heat treatment for 10 hours or more in a box gas or oxygen atmosphere at a temperature of 1000℃, a process of heat treatment in a rare gas or oxygen atmosphere at a temperature of 1000℃, and l'l! Step of removing the oxide film on the surface of the I ite substrate, and 1) No. 11 substrate-1-
(j) forming an evitagital layer with a resistivity comparable to that of the substrate;
'To form a well of type l! 1. Solid-state imaging with characteristics 2. Manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58175466A JPH0789555B2 (en) | 1983-09-22 | 1983-09-22 | Method of manufacturing solid-state image sensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58175466A JPH0789555B2 (en) | 1983-09-22 | 1983-09-22 | Method of manufacturing solid-state image sensor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6066857A true JPS6066857A (en) | 1985-04-17 |
JPH0789555B2 JPH0789555B2 (en) | 1995-09-27 |
Family
ID=15996549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58175466A Expired - Lifetime JPH0789555B2 (en) | 1983-09-22 | 1983-09-22 | Method of manufacturing solid-state image sensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0789555B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010087512A (en) * | 2008-09-29 | 2010-04-15 | Magnachip Semiconductor Ltd | Silicon wafer, and method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5087594A (en) * | 1973-12-03 | 1975-07-14 | ||
JPS5766666A (en) * | 1980-10-13 | 1982-04-22 | Matsushita Electronics Corp | Solid state image pickup device |
JPS58102528A (en) * | 1981-12-14 | 1983-06-18 | Toshiba Corp | Treatment of semiconductor wafer |
JPS58159334A (en) * | 1982-03-17 | 1983-09-21 | Toshiba Corp | Treating method for semiconductor wafer |
-
1983
- 1983-09-22 JP JP58175466A patent/JPH0789555B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5087594A (en) * | 1973-12-03 | 1975-07-14 | ||
JPS5766666A (en) * | 1980-10-13 | 1982-04-22 | Matsushita Electronics Corp | Solid state image pickup device |
JPS58102528A (en) * | 1981-12-14 | 1983-06-18 | Toshiba Corp | Treatment of semiconductor wafer |
JPS58159334A (en) * | 1982-03-17 | 1983-09-21 | Toshiba Corp | Treating method for semiconductor wafer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010087512A (en) * | 2008-09-29 | 2010-04-15 | Magnachip Semiconductor Ltd | Silicon wafer, and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0789555B2 (en) | 1995-09-27 |
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