JPH0470771B2 - - Google Patents

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Publication number
JPH0470771B2
JPH0470771B2 JP16976383A JP16976383A JPH0470771B2 JP H0470771 B2 JPH0470771 B2 JP H0470771B2 JP 16976383 A JP16976383 A JP 16976383A JP 16976383 A JP16976383 A JP 16976383A JP H0470771 B2 JPH0470771 B2 JP H0470771B2
Authority
JP
Japan
Prior art keywords
substrate
opening
film
hcl
facet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16976383A
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Japanese (ja)
Other versions
JPS6060716A (en
Inventor
Akihiko Ishitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP16976383A priority Critical patent/JPS6060716A/en
Publication of JPS6060716A publication Critical patent/JPS6060716A/en
Publication of JPH0470771B2 publication Critical patent/JPH0470771B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 本発明は絶縁膜領域を有する単結晶基板上に選
択的にシリコンエピタキシヤル層を成長させるよ
うな半導体基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor substrate in which a silicon epitaxial layer is selectively grown on a single crystal substrate having an insulating film region.

従来の半導体デバイスでは、シリコン基板にイ
オン注入又は不純物拡散法を用いて所望のP型又
はN型の伝導型にして能動素子とし、能動素子間
の分離はPN接合あるいは部分酸化(LOCOS)
法を用いていた。しかるに接合の浮遊容量の増大
や部分酸化工程の寸法変化があり、素子の高速
化、高密度化の障害となつていた。
In conventional semiconductor devices, a silicon substrate is made into a desired P-type or N-type conductivity type by using ion implantation or impurity diffusion to become an active element, and isolation between active elements is achieved by using a PN junction or partial oxidation (LOCOS).
was using the law. However, there is an increase in the stray capacitance of the junction and a dimensional change due to the partial oxidation process, which has been an obstacle to increasing the speed and density of devices.

上記の欠点を補う技術としてSOS(Si on
Sapphire)を基板に用いる方法がある。基板が
絶縁体であるため浮遊容量が少なく、素子の高速
化に有利である。一方、基板とシリコンエピタキ
シヤル層は異種接合されているので格子定数の不
整合による基板シリコン界面の格子欠陥が多く、
リーク電流の発生が欠点となつていた。
SOS (Si on) is a technology that compensates for the above drawbacks.
There is a method using Sapphire as a substrate. Since the substrate is an insulator, there is little stray capacitance, which is advantageous for increasing the speed of the device. On the other hand, since the substrate and the silicon epitaxial layer are bonded with different types, there are many lattice defects at the substrate-silicon interface due to lattice constant mismatch.
The drawback was the generation of leakage current.

さらに新しい絶縁基板上のシリコン膜の単結晶
化技術としてグラフオエピタキシイ技術とブリツ
ジングエピタキシイ技術がある。
Furthermore, there are graphite epitaxy technology and bridging epitaxy technology as new single crystallization technologies for silicon films on insulating substrates.

前者はアプライドフイズイツクスレターズ第35
巻第1番71〜74頁1979年(Aplied Physics
Letters,Vol.35,No.1、pp71〜74 1979)に記載
されており、石英基板に溝加工を施し、多結晶シ
リコンのCVD膜を基板全面に成長しレーザー照
射によつて単結晶化しようとするものである。
The former is Applied Fixtures Letters No. 35.
Volume 1, pages 71-74, 1979 (Applied Physics
Letters, Vol. 35, No. 1, pp. 71-74 1979), a method is described in which a groove is formed on a quartz substrate, a CVD film of polycrystalline silicon is grown on the entire surface of the substrate, and it is made into a single crystal by laser irradiation. That is.

後者はジヤパンジヤーナル オブ アプライド
フイジイツクス第19巻第1頁L23〜L26頁1980年
(Japan Journal of Applid Physics,Vol.19,
No.1,ppL23〜L26,1980)に記載されており、
それによると半導体単結晶基板に部分的に絶縁膜
を形成し、さらに多結晶シリコン膜を基板の全面
に堆積し、レーザー照射により基板上を種結晶と
する再生結晶化を施し絶縁基板上にも単結晶層を
形成しようとするものである。しかしながらいず
れの方法も単結晶化の程度、絶縁膜上の結晶欠陥
等に問題があり実用に耐えるデバイス特性を得る
までに至つていない。
The latter is published in Japan Journal of Applied Physics, Vol. 19, Pages 1, L23-L26, 1980 (Japan Journal of Applied Physics, Vol. 19,
No. 1, ppL23-L26, 1980),
According to this, an insulating film is formed partially on a semiconductor single crystal substrate, a polycrystalline silicon film is further deposited on the entire surface of the substrate, and re-crystallization is performed using the substrate as a seed crystal by laser irradiation. The aim is to form a single crystal layer. However, each method has problems with the degree of single crystallization, crystal defects on the insulating film, etc., and has not reached the point where it has reached the point where device characteristics that can withstand practical use are obtained.

これらの技術に対して選択エピタキシヤル技術
がある。これは半導体単結晶基板に部分的に絶縁
膜を形成し、その絶縁膜上には堆積しないで露出
した基板領域のみにエピタキシヤル成長し素子の
能動領域とするものである。このエピタキシヤル
方法は同種接合であるため極めて高品質な結晶性
を示し、しかも簡便で量屋性に富んだ優れた特性
をもつ。
In contrast to these techniques, there is a selective epitaxial technique. In this method, an insulating film is partially formed on a semiconductor single crystal substrate, and epitaxial growth is performed only on the exposed substrate region without depositing on the insulating film, thereby forming the active region of the device. Since this epitaxial method uses homogeneous bonding, it exhibits extremely high quality crystallinity, and has excellent characteristics such as being simple and easy to manufacture in bulk.

しかし従来の選択エピタキシヤに用いられる基
板は単結晶基板上に絶縁膜を形成した後、絶縁膜
を部分的に開口して形成していたので絶縁膜とエ
ピタキシヤル膜との界面は界面張力の影響を強く
受けてフアセツトが形成される。例えば(100)
基板を用いると(113)面を有する4回対称のフ
アセツトが生成される。(111)面基板を用いると
別の方位の(111)面が現れる。(110)面基板を
用いると(111)面が現れる。このように従来構
成による基板上に形成された絶縁ゲート電界効果
型トランジスタは表面の凹凸のためゲート絶縁膜
の耐圧が低く配線の断線も起り易いという欠点が
あつた。
However, the substrate used in conventional selective epitaxy is formed by forming an insulating film on a single crystal substrate and then partially opening the insulating film, so the interface between the insulating film and the epitaxial film is affected by interfacial tension. A facet is formed by being strongly affected by For example (100)
The use of a substrate produces a 4-fold symmetrical facet with (113) planes. When a (111) plane substrate is used, a (111) plane with a different orientation appears. When a (110) plane substrate is used, a (111) plane appears. As described above, an insulated gate field effect transistor formed on a substrate with a conventional structure has a drawback that the gate insulating film has a low withstand voltage and wires are easily disconnected due to the unevenness of the surface.

本発明は単結晶基板方位に依存しないで極めて
平坦な表面が得られる選択エピタキシヤ成長基板
を得る方法を提供するものであり、本発明は次の
3つの原理に基づくものである。
The present invention provides a method for obtaining a selective epitaxy growth substrate that provides an extremely flat surface independent of the orientation of the single crystal substrate, and is based on the following three principles.

フアセツトの大きさはエピ成長膜厚に比例す
る。そのメカニズムは、100基板の場合第1図
に示すように、開口部の低面から(100)面が成
長速度αで成長し、側壁近傍では成長開始と同時
に成長速度βの遅いフアセツト面が発生して、以
後それらの交点である点X,Yが成長と共に右上
方に移動して、フアセツトの発達をもたらすもの
である。実際、第1図において、(100)面をy=
αtとし、フアセツト面をy=(tanθ)x+βt/
cosθとすると、フアセツト幅Wとエピ成長膜厚αt
の関係は W=(tanθ)(1−β/αcosθ)・αt (1) となり、フアセツト幅Wとエピ成長膜αtが比例関
係にある実験結果第2図と一致する。
The size of the facet is proportional to the epitaxial film thickness. The mechanism is that, as shown in Figure 1 in the case of a 100 substrate, the (100) plane grows at a growth rate α from the lower side of the opening, and near the sidewalls, a facet with a slow growth rate β occurs at the same time as the growth starts. Thereafter, the points X and Y, which are the intersection points of these, move upward and to the right as the child grows, resulting in the development of the facet. In fact, in Figure 1, the (100) plane is y=
Let αt be the facet plane y=(tanθ)x+βt/
If cos θ, facet width W and epitaxial growth film thickness αt
The relationship is W=(tanθ)(1-β/αcosθ)·αt (1), which agrees with the experimental result shown in FIG. 2 in which the facet width W and the epitaxially grown film αt are in a proportional relationship.

フアセツトの大きさは注入するHCl量に依存す
る。(1)式に示すように、フアセツトの大きさは成
長速度の結晶方位依存性を示すβ/αに依存す
る。同時に、結晶方位による成長速度の比はHCl
の注入量にも依存する。第3図は(100)面の成
長速度を基準とし、そこから結晶方位が離れるに
つれ成長速度がどのように変化していくかを、
HClの量をパラメータにして、見た図である。横
軸は(100)面と他の面がなす角度であり、(111)
面は約50度である。HClを注入しない場合は
(100)と(111)の成長速度の比は0.5であるが、
1.31/min注入すると0.1に低下する。従つて、
HCl注入量を増すほどフアセツトは大きくなる。
The size of the facets depends on the amount of HCl injected. As shown in equation (1), the size of the facet depends on β/α, which indicates the crystal orientation dependence of the growth rate. At the same time, the ratio of growth rate due to crystal orientation is
It also depends on the amount of injection. Figure 3 shows how the growth rate changes as the crystal orientation moves away from the (100) plane growth rate.
This is a view using the amount of HCl as a parameter. The horizontal axis is the angle between the (100) plane and other planes, and the (111)
The plane is about 50 degrees. When HCl is not injected, the ratio of growth rates of (100) and (111) is 0.5, but
When injected at 1.31/min, it decreases to 0.1. Therefore,
The facet becomes larger as the HCl injection amount increases.

Sih2Cl2/H2/HClにおける選択エピタキシヤ
成長では、ウエーハー全面積に対する開口部の合
計面積の割合いによつて必要なHCl注入量が異
る。HClを注入しなくてもSiH2Cl2/H2系では開
口部近傍にはSiは核発生しない。この理由は、一
つには、SiH2Cl2から分解してできるHClが存在
するので、もともとある程度の選択性があるこ
と、もう一つには、開口部付近とフイールド酸化
膜上とは反応種であるSiCl2の濃度勾配があると
考えられることである。いずれにしても、HClの
注入は、開口部から離れたフイールド酸化膜上の
Siの核発生を抑制するために必要であり、開口部
面積が増してフイールド酸化膜の部分が少なくな
れば、注入HCl量は少くてよいのである。実際第
4図に示すように、横軸にウエーハー全面積に対
する開口部の合計面積の比σをとり、縦軸に選択
エピタキシヤ成長する(フイールド酸化膜上にSi
の核が発生しない)最少HCl注入量をとると、比
σの値が大きいほどHCl注入量は少なくても選択
エピタキシヤ成長が可能である。比σが約0.8以
上であれば、HClの注入量は必要ない。
In selective epitaxial growth using Sih 2 Cl 2 /H 2 /HCl, the required amount of HCl injection varies depending on the ratio of the total area of the openings to the total area of the wafer. In the SiH 2 Cl 2 /H 2 system, Si does not nucleate near the opening even if HCl is not injected. One reason for this is that HCl, which is formed by decomposition from SiH 2 Cl 2 , exists and therefore has a certain degree of selectivity, and the other reason is that there is a reaction between the area near the opening and the top of the field oxide film. It is thought that there is a concentration gradient of the species SiCl 2 . In any case, the HCl injection is performed on the field oxide away from the opening.
This is necessary to suppress the generation of Si nuclei, and if the opening area increases and the field oxide film portion decreases, the amount of HCl injected can be reduced. In fact, as shown in Figure 4, the horizontal axis represents the ratio σ of the total area of the openings to the total area of the wafer, and the vertical axis represents the selective epitaxial growth (Si
If the minimum amount of HCl injection is taken (no nuclei are generated), the larger the value of ratio σ, the more selective epitaxial growth is possible even with a smaller amount of HCl injection. If the ratio σ is about 0.8 or higher, no injection amount of HCl is necessary.

実際のデバイス作成用選択エピタキシヤル成長
においては、エピタキシヤ成長膜厚はある程度欲
しいが、フアセツトはできるだけ小さくしたい。
また、開口部面積は基板全体の面積に比べてそれ
ほど大きくないという場合が多い。上述の知見に
基くデバイスを作成する目的で設けた開口部の他
にデバイス作成を目的としない開口部を設けて比
σを増し、HCl注入量をできるだけ減らせばフア
セツトを許容される大きさにまで抑制でき、平坦
な選択エピタキシヤル成長を実現できる。すなわ
ち、ウエーハー全面積に対する開口部の合計面積
の比σとフアセツトの幅Wの関係は第5図のよう
な関係にある。エピタキシヤ成長膜厚を変えると
フアセツト幅は大きくなるが、比σを増してHCl
注入量を減らせべ、フアセツトの大きさはデバイ
ス作成上ほとんど無視できる程度にまで小さくな
る。例えばCMOSを目的として選択エピタキシ
ヤ成長する場合、膜厚はせいぜい2μmである。実
用上フアセツト幅は、ゲート配線が断線しないた
めに、3000Å程度以下にしたい。このとき、比σ
を50%以上にし、HCl注入量を0.32/minに減
らせば所望の選択エピタキシヤ成長ができる。以
下に本発明を実施例に従つて詳細に説明する。
In actual selective epitaxial growth for device fabrication, a certain level of epitaxial growth film thickness is desired, but the facet is desired to be as small as possible.
Furthermore, the area of the opening is often not so large compared to the area of the entire substrate. In addition to the openings created for the purpose of creating devices based on the above findings, openings not intended for device creation can be created to increase the ratio σ and reduce the amount of HCl injection as much as possible to bring the facet to an acceptable size. It is possible to achieve flat selective epitaxial growth. That is, the relationship between the ratio σ of the total area of the openings to the total area of the wafer and the width W of the facet is as shown in FIG. Changing the epitaxial growth film thickness increases the facet width, but increases the ratio σ and increases the HCl
The injection volume can be reduced and the facet size can be reduced to an almost negligible level for device fabrication. For example, when selective epitaxial growth is performed for the purpose of CMOS, the film thickness is at most 2 μm. In practical terms, the facet width should be about 3000 Å or less to prevent the gate wiring from breaking. At this time, the ratio σ
The desired selective epitaxial growth can be achieved by increasing the HCl injection rate to 50% or more and reducing the HCl injection rate to 0.32/min. The present invention will be explained in detail below based on examples.

第6図a,bは本発明による半導体基板の製造
方法をその製造工程を順を追つて示した模式的断
面図である。
FIGS. 6a and 6b are schematic cross-sectional views showing the manufacturing process of a semiconductor substrate manufacturing method according to the present invention in order.

まず、例えば1Ω・cm程度の比抵抗を有する
(100)シリコン基板1の上に1000℃で熱酸化し、
約2μmの膜厚のSiO2膜を堆積した後通常の写真
蝕刻技術と反応性イオンエツチング技術で、第6
図aに示すようにSiO2膜パターン2を形成する。
能動領域として用いる開口部15と、デバイス作
製を目的としない比σを増すための開口部25を
この工程で作製する。開口部25は100μm×
100μmの矩形パターンで基板全面に分布させて設
けた。この基板において、開口部15の合計面積
はウエーハ全面積に対して19.6%であるが、開口
部25を設けたため55%になつている。SiH2Cl2
と水素から構成されるガス系にHClをおよそ1vol
%程度加え、900℃から1100℃の温度範囲で選択
的にエピタキシヤ成長すると、単結晶Si膜5は
SiO2膜2の表面には堆積しないで露出したシリ
コン基板上にのみ成長する(第6図b)。成長後
フアセツト幅を測定したところ約2500Åであつ
た。
First, a (100) silicon substrate 1 having a resistivity of, for example, about 1 Ω cm is thermally oxidized at 1000°C.
After depositing a SiO 2 film with a thickness of approximately 2 μm, the sixth
As shown in Figure a, a SiO 2 film pattern 2 is formed.
An opening 15 used as an active region and an opening 25 for increasing the ratio σ, which is not intended for device fabrication, are formed in this step. Opening 25 is 100μm×
A rectangular pattern of 100 μm was distributed over the entire surface of the substrate. In this substrate, the total area of the openings 15 is 19.6% of the total area of the wafer, but because the openings 25 are provided, the total area is 55%. SiH2Cl2 _
Approximately 1 vol of HCl is added to the gas system consisting of
% and selectively epitaxially grows in the temperature range of 900°C to 1100°C, the single crystal Si film 5 becomes
It does not deposit on the surface of the SiO 2 film 2, but grows only on the exposed silicon substrate (FIG. 6b). When the facet width was measured after growth, it was approximately 2500 Å.

なお高温で選択エピタキシヤ成長するとSiO2
膜2が剥がれることがあるが、SiO2膜2の側壁
に薄いSi3N4膜を形成してから成長すると剥がれ
ることがない。また側壁に薄いポリシリコン膜を
形成してから成長するとフアセツト幅がより小さ
くなり、上記実施例の場合では約2000Åにするこ
とができる。
Furthermore, if selective epitaxy is grown at high temperature, SiO 2
The film 2 may peel off, but if a thin Si 3 N 4 film is formed on the side wall of the SiO 2 film 2 and then grown, this will not occur. Further, if a thin polysilicon film is formed on the sidewalls and then grown, the facet width becomes smaller, and in the case of the above embodiment, it can be made approximately 2000 Å.

以上述べたように本発明は、デバイスを作製し
ない開口部を設けることで基板の全面積に対する
開口部の割合を増やして50%以上とすることによ
つて従来得られなかつた平坦な選択エピタキシヤ
ル成長膜が得られる方法を提供するものであり、
その工業的価値は大きい。
As described above, the present invention increases the ratio of the opening to 50% or more of the total area of the substrate by providing an opening in which no device is fabricated, thereby achieving a flat selective epitaxial layer that could not be obtained conventionally. Provides a method for obtaining a grown film,
Its industrial value is great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はフアセツトの形成過程を説明するため
の模式図である。第2図はエピタキシヤル膜厚と
フアセツト幅Wの関係の実験結果を示す図であ
る。第3図は(100)面の成長速度を基準とし、
そこから結晶方位が離れるにつれ成長速度がどの
ように変化していくかを、HClの量をパラメータ
にして、見た図である。第4図はウエーハー全面
積に対する開口部の合計面積の比と選択エピタキ
シヤル成長する最少HCl注入量の関係を示す図で
ある。第5図は面積比とフアセツト幅Wの関係を
示す図で、HCl注入量は第4図における比に対す
る最少HCl量である。第6図a,bは本発明にお
ける半導体基板の製造工程を説明するための概略
断面図で、1は(100)シリコン基板、2はSiO2
絶縁膜パターン、5は選択エピタキシヤル成長し
た単結晶シリコンである。15は能動領域として
用いる開口部、25はデバイス作製を目的としな
い開口部。
FIG. 1 is a schematic diagram for explaining the process of forming a facet. FIG. 2 is a diagram showing experimental results regarding the relationship between epitaxial film thickness and facet width W. Figure 3 is based on the growth rate of the (100) plane,
This is a diagram showing how the growth rate changes as the crystal orientation moves away from it, using the amount of HCl as a parameter. FIG. 4 is a diagram showing the relationship between the ratio of the total area of openings to the total area of the wafer and the minimum amount of HCl implanted for selective epitaxial growth. FIG. 5 is a diagram showing the relationship between the area ratio and the facet width W, and the HCl injection amount is the minimum HCl amount with respect to the ratio in FIG. 6a and 6b are schematic cross-sectional views for explaining the manufacturing process of a semiconductor substrate in the present invention, where 1 is a (100) silicon substrate, 2 is a SiO 2
Insulating film pattern 5 is single crystal silicon grown selectively epitaxially. 15 is an opening used as an active region, and 25 is an opening not intended for device fabrication.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン単結晶基板に絶縁膜を設け、次に該
絶縁膜に開口部を設けて基板単結晶シリコンを露
出させ、次にクロルシランを流してこの開口部に
選択的にシリコン膜をエピタキシヤル成長させる
半導体基板の製造方法において、デバイスを作製
しない開口部を設けることで基板の全面積に対す
る開口部の割合を増やし50%以上にして前記選択
エピタキシヤル成長を行うことを特徴とした半導
体基板の製造方法。
1. An insulating film is provided on a silicon single crystal substrate, then an opening is provided in the insulating film to expose the substrate single crystal silicon, and then chlorosilane is flowed to selectively epitaxially grow a silicon film in this opening. A method for manufacturing a semiconductor substrate, characterized in that the selective epitaxial growth is performed by increasing the ratio of the opening to the total area of the substrate to 50% or more by providing an opening in which no device is to be formed. .
JP16976383A 1983-09-14 1983-09-14 Manufacture of semiconductor substrate Granted JPS6060716A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16976383A JPS6060716A (en) 1983-09-14 1983-09-14 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16976383A JPS6060716A (en) 1983-09-14 1983-09-14 Manufacture of semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS6060716A JPS6060716A (en) 1985-04-08
JPH0470771B2 true JPH0470771B2 (en) 1992-11-11

Family

ID=15892397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16976383A Granted JPS6060716A (en) 1983-09-14 1983-09-14 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS6060716A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358921A (en) * 1986-08-29 1988-03-14 Fujitsu Ltd Manufacture of semiconductor device
JPH02142117A (en) * 1988-11-22 1990-05-31 Mitsubishi Electric Corp Manufacture of semiconductor integrated circuit
JP6022816B2 (en) * 2012-06-12 2016-11-09 猛英 白土 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPS6060716A (en) 1985-04-08

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