JPH04326576A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04326576A
JPH04326576A JP9649491A JP9649491A JPH04326576A JP H04326576 A JPH04326576 A JP H04326576A JP 9649491 A JP9649491 A JP 9649491A JP 9649491 A JP9649491 A JP 9649491A JP H04326576 A JPH04326576 A JP H04326576A
Authority
JP
Japan
Prior art keywords
oxide film
silicon
film
gate
gate oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9649491A
Other languages
Japanese (ja)
Inventor
Yoshiaki Suzuki
芳明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9649491A priority Critical patent/JPH04326576A/en
Publication of JPH04326576A publication Critical patent/JPH04326576A/en
Pending legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To obtain a semiconductor device which has a gate oxide film with a uniform thickness and a superior quality by transforming a silicon layer to a silicon oxide film by the thermal oxidation method to form a gate oxide film after new silicon layer is piled up and adhered on the silicon surface. CONSTITUTION:After a field oxide film 2 for insulating isolation is selectively formed on a silicon substrate 1, a single-crystalline silicon layer 3 having about half in thickness of desired silicon oxide film is piled up on the substrate 1. At this time, a single crystal silicon film is formed on the substrate 1 and a polycrystalline silicon film on the film 2, respectively. Next, the layer 3 is transformed to a silicon oxide film by the thermal oxidation method to form a gate oxide film 4. Then a gate electrode, etc., composed of the polycrystalline silicon are formed on the film 4. Therefore, the gate oxide film, which has the uniform film thickness even in the area adjacent to the film 2 or so far away from it and the film quality equivalent to that of the silicon oxide film through thermal oxidation of the silicon surface, can be obtained easily.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にMOS型半導体素子を有する半導体装置のゲ
ート酸化膜の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate oxide film of a semiconductor device having a MOS type semiconductor element.

【0002】0002

【従来の技術】MOS型半導体素子を有する半導体装置
においては、ダイナミックRAMに代表されるように高
性能化,高集積化が進み、半導体装置の構成要素である
MOS型半導体素子のゲート酸化膜も薄膜化されてきて
いる。
2. Description of the Related Art Semiconductor devices having MOS type semiconductor elements, as typified by dynamic RAM, have become more sophisticated and highly integrated. Films are becoming thinner.

【0003】従来、このゲート酸化膜の製造方法は、図
4(a)に示すように、シリコン基板1にフィールド酸
化膜2を形成したのち、露出したシリコン基板1を、例
えば水蒸気などの酸化性雰囲気で熱処理を施し、シリコ
ン基板1の表面を所望の厚さまで酸化し、図4(b)に
示すように、ゲート酸化膜4Bに変換する方法であった
。こうして得られる酸化シリコン膜の品質は、酸化する
シリコン結晶の表面の品質が影響することが知られてお
り、ゲート酸化膜4Bを形成するための熱酸化に先立ち
、所謂犠牲酸化と呼ばれる熱処理工程を追加するのが一
般的である。これは、通常シリコン基板に含まれる酸素
のうち、表面近くのものが熱処理によりシリコン基板外
に外方拡散を起こし、その濃度が低下し、酸素はシリコ
ン表面で析出しなくなり、ゲート酸化膜である酸化シリ
コン膜中に酸素析出物が存在しないため、その品質は向
上する。
Conventionally, as shown in FIG. 4(a), the method for manufacturing a gate oxide film involves forming a field oxide film 2 on a silicon substrate 1, and then subjecting the exposed silicon substrate 1 to an oxidizing agent such as water vapor. The method was to perform heat treatment in an atmosphere, oxidize the surface of the silicon substrate 1 to a desired thickness, and convert it into a gate oxide film 4B as shown in FIG. 4(b). It is known that the quality of the silicon oxide film obtained in this way is affected by the quality of the surface of the silicon crystal to be oxidized, and prior to the thermal oxidation to form the gate oxide film 4B, a heat treatment process called so-called sacrificial oxidation is carried out. It is common to add This is because, among the oxygen normally contained in a silicon substrate, oxygen near the surface diffuses out of the silicon substrate due to heat treatment, its concentration decreases, and oxygen no longer precipitates on the silicon surface, forming a gate oxide film. Since no oxygen precipitates are present in the silicon oxide film, its quality is improved.

【0004】さらに、この種のゲート酸化膜の形成方法
として、選択的にシリコン基板を露出させた後、CVD
法あるいはスパッタリング法等により、酸化シリコン膜
を堆積被着する方法もある。
Furthermore, as a method for forming this type of gate oxide film, after selectively exposing the silicon substrate, CVD is performed.
There is also a method of depositing a silicon oxide film by a method such as a method or a sputtering method.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置の製造工程におけるゲート酸化膜の
形成方法は、いずれも以下に示すような欠点を有する。 先ず、シリコン基板表面を熱酸化して、ゲート酸化膜で
ある、酸化シリコン膜を形成する方法では、図4(b)
に示したように、素子分離用のフィールド酸化膜2との
境界付近A部の膜厚が薄くなるという問題がある。これ
は、フィールド酸化膜2の形成後のゲート酸化膜4Bを
形成するための熱酸化の際に、フィールド酸化膜端から
十分離れてシリコン基板が露出している部分では、酸化
膜が直接シリコン基板と反応するのに対し、フィールド
酸化膜近傍ではフィールド酸化膜を酸化種が拡散しては
じめてシリコン基板と反応するための時間的遅れが生じ
るためである。
However, all of the above-described conventional methods for forming a gate oxide film in the manufacturing process of a semiconductor device have the following drawbacks. First, in the method of thermally oxidizing the silicon substrate surface to form a silicon oxide film, which is a gate oxide film, as shown in FIG. 4(b).
As shown in FIG. 2, there is a problem in that the film thickness of the portion A near the boundary with the field oxide film 2 for element isolation becomes thinner. This is because during thermal oxidation to form gate oxide film 4B after field oxide film 2 is formed, the oxide film is directly exposed to the silicon substrate in areas where the silicon substrate is exposed at a sufficient distance from the edge of the field oxide film. This is because, in contrast, in the vicinity of the field oxide film, there is a time delay in which the oxidizing species reacts with the silicon substrate only after it has diffused through the field oxide film.

【0006】このフィールド酸化膜との境界付近の膜厚
のフィールド酸化膜から十分に離れた所の膜厚に対する
比率である薄膜化率は、フィールド酸化膜端部の形状に
よって若干左右されるが、本願発明者が実験したところ
によればおおよそ、80%であった。すなわち、20n
mのゲート酸化膜を形成する場合、フィールド酸化膜と
の境界付近A部の酸化シリコン膜の厚さは16nmしか
得られないことになる。すると、ゲート酸化膜の絶縁耐
圧は薄い部分で決まって、何ら欠陥のない酸化シリコン
膜であっても前述の例では約16Vとなってしまい、2
0nmの酸化シリコン膜本来の耐圧20Vは得られない
ことになる。
The thinning rate, which is the ratio of the film thickness near the boundary with the field oxide film to the film thickness at a sufficient distance from the field oxide film, is slightly influenced by the shape of the edge of the field oxide film. According to experiments conducted by the inventor of the present application, it was approximately 80%. That is, 20n
In the case of forming a gate oxide film of m, the thickness of the silicon oxide film at part A near the boundary with the field oxide film is only 16 nm. Then, the dielectric strength voltage of the gate oxide film is determined by the thin part, and even for a silicon oxide film without any defects, it would be about 16V in the above example, and 2
The inherent breakdown voltage of 20 V for a 0 nm silicon oxide film cannot be obtained.

【0007】また、ゲート酸化膜の形成に先立ち、犠牲
酸化が行なわれるが、シリコン基板の結晶表面の品質の
影響をある程度取り除くことができるが、上述した問題
点は解決されない。半導体装置の特性を満足するための
ゲート酸化膜の厚さは、フィールド酸化膜から十分に離
れた所の膜厚で決まるため、上記のような酸化シリコン
膜をゲート酸化膜として有すると、半導体装置の製造歩
留りの低下を引き起こす。
Further, sacrificial oxidation is performed prior to the formation of the gate oxide film, and although the influence of the quality of the crystal surface of the silicon substrate can be removed to some extent, the above-mentioned problems are not solved. The thickness of the gate oxide film that satisfies the characteristics of the semiconductor device is determined by the thickness of the film at a sufficient distance from the field oxide film, so if the silicon oxide film described above is used as the gate oxide film, This causes a decrease in manufacturing yield.

【0008】また、酸化シリコン膜の品質の一つの指標
である酸化シリコン膜中に流し込める電荷量でみると、
その電荷量は膜の厚さに依存し、膜厚が薄くなると伴に
指数関数的に減少することが本願発明者の実験により判
明しており、例えば厚さ15nmの酸化シリコン膜に流
し込める電荷量と厚さ12nmの酸化シリコン膜とを比
較すると、12nmの酸化シリコン膜には15nmの酸
化シリコン膜に流し込める電荷量の約70%しか流し込
めない。従って上述したゲート酸化膜を有する半導体装
置ではその信頼性の低下をも引き起こすという問題があ
る。
[0008] Furthermore, in terms of the amount of charge that can be poured into the silicon oxide film, which is one indicator of the quality of the silicon oxide film,
The amount of charge depends on the thickness of the film, and it has been found through experiments that the amount of charge decreases exponentially as the film thickness becomes thinner.For example, the amount of charge that can be poured into a silicon oxide film with a thickness of 15 nm has been found to be Comparing the amount of charge with a 12 nm thick silicon oxide film, only about 70% of the amount of charge that can be poured into a 15 nm silicon oxide film can be poured into a 12 nm silicon oxide film. Therefore, there is a problem in that the reliability of the semiconductor device having the above-mentioned gate oxide film is lowered.

【0009】また、フィールド酸化膜との境界付近で薄
くなる問題点と、シリコン基板の結晶表面の酸素に起因
する問題点を同時に解決する方法として、酸化シリコン
膜をCVD法あるいはスパッタリング法により堆積被着
する方法がある。しかし、一般的にこの様な方法で形成
した酸化シリコン膜は、シリコンを熱酸化して得られる
酸化シリコン膜に比べその膜質は劣り、絶縁耐圧で比較
すると電界強度で1MV/cm以上劣化しているのが現
実である。従って、半導体装置の性能を満足する膜厚で
は、製造歩留りや信頼性を確保できないという問題点が
ある。
In addition, as a method for simultaneously solving the problem of thinning near the boundary with the field oxide film and the problem caused by oxygen on the crystal surface of the silicon substrate, a silicon oxide film is deposited by CVD or sputtering. There is a way to wear it. However, silicon oxide films formed by this method are generally inferior in film quality to silicon oxide films obtained by thermally oxidizing silicon, and when compared with dielectric strength, the electric field strength deteriorates by more than 1 MV/cm. The reality is that there are. Therefore, there is a problem that manufacturing yield and reliability cannot be ensured even with a film thickness that satisfies the performance of the semiconductor device.

【0010】本発明はかかる問題点に鑑みてなされたも
のであって、ゲート酸化膜のフィールド酸化膜近傍での
薄膜化を防止し、膜質の優れた酸化シリコン膜をゲート
酸化膜とするMOS型半導体素子を有する半導体装置の
製造方法を提供することを目的としている。
The present invention has been made in view of these problems, and it prevents thinning of the gate oxide film in the vicinity of the field oxide film, and provides a MOS type in which a silicon oxide film with excellent film quality is used as the gate oxide film. An object of the present invention is to provide a method for manufacturing a semiconductor device having a semiconductor element.

【0011】[0011]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、シリコン基板上に素子形成領域を分離するフ
ィールド酸化膜を形成する工程と、前記素子形成領域の
前記シリコン基板表面にシリコン層を形成する工程と、
前記シリコン層を酸化しゲート酸化膜を形成する工程と
を含むものである。
Means for Solving the Problems A method for manufacturing a semiconductor device of the present invention includes the steps of forming a field oxide film on a silicon substrate to separate element formation regions, and forming a silicon layer on the surface of the silicon substrate in the element formation regions. a step of forming;
The method includes a step of oxidizing the silicon layer to form a gate oxide film.

【0012】0012

【実施例】次に本発明について図面を参照して詳細に説
明する。図1(a)〜(c)は本発明の第1の実施例を
説明するための半導体チップの断面図であり、特にダイ
ナミックRAMにおけるメモリーセルの転送ゲートに適
用した場合を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings. FIGS. 1A to 1C are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, particularly showing the case where the semiconductor chip is applied to a transfer gate of a memory cell in a dynamic RAM.

【0013】先ず、図1(a)に示すように、既知の方
法で絶縁分離用のフィールド酸化膜2をシリコン基板1
上に選択的に形成する。次に図1(b)に示すように、
このシリコン基板1の表面に所望の酸化シリコン膜の厚
さの約半分、例えば8nmの厚さの単結晶シリコン層3
を既知の方法、例えばシランガスを用いたエピタキシャ
ル成長法により堆積する。この時、シリコン基板1の表
面には単結晶シリコン膜が、そしてフィールド酸化膜2
上には多結晶シリコン膜が形成される。
First, as shown in FIG. 1(a), a field oxide film 2 for insulation isolation is formed on a silicon substrate 1 by a known method.
selectively formed on top. Next, as shown in Figure 1(b),
On the surface of this silicon substrate 1, a single crystal silicon layer 3 having a thickness of about half of the desired silicon oxide film, for example, 8 nm, is formed.
is deposited by a known method, for example, epitaxial growth using silane gas. At this time, a single crystal silicon film is formed on the surface of the silicon substrate 1, and a field oxide film 2 is formed on the surface of the silicon substrate 1.
A polycrystalline silicon film is formed thereon.

【0014】その後図1(c)に示すように、シリコン
基板1を通常の水素及び酸素ガスの雰囲気下におき、熱
酸化法により堆積したシリコン層3を厚さ20nmの酸
化シリコン膜に変換してゲート酸化膜4を形成する。以
下通常の方法によりゲート酸化膜4上に多結晶シリコン
からなるゲート電極等を形成し、転送ゲートトランジス
タを構成する。
Thereafter, as shown in FIG. 1(c), the silicon substrate 1 is placed in a normal hydrogen and oxygen gas atmosphere, and the deposited silicon layer 3 is converted into a 20 nm thick silicon oxide film by thermal oxidation. A gate oxide film 4 is then formed. Thereafter, a gate electrode made of polycrystalline silicon and the like are formed on the gate oxide film 4 by a conventional method to form a transfer gate transistor.

【0015】このようにゲート酸化膜4は、一様に堆積
被着したシリコン層3を熱酸化して得られた酸化シリコ
ン膜であるため、フィールド酸化膜近傍でも、十分離れ
た所でも同じ膜厚で、且つシリコン表面を熱酸化して得
られる酸化シリコン膜と同等の品質のゲート酸化膜が得
られる。
As described above, since the gate oxide film 4 is a silicon oxide film obtained by thermally oxidizing the uniformly deposited silicon layer 3, the same film is formed both near the field oxide film and at a sufficiently distant location. A gate oxide film that is thick and has the same quality as a silicon oxide film obtained by thermally oxidizing the silicon surface can be obtained.

【0016】図2(a),(b)は、本実施例及び従来
例により作成した場合の転送ゲート・トランジスタのゲ
ート絶縁耐圧分布を示す図である。ここではシリコン表
面を熱酸化することによりフィールド酸化膜から十分離
れた所で厚さが20nmとなる様に形成したゲート絶縁
耐圧分布を示す。図2(a),(b)から明らかなよう
に、本実施例の方法においては、厚さ20nmの酸化シ
リコン膜本来の耐圧である20V付近に集中して分布し
ている。これに対して従来の方法においては16V付近
に集中しており、従来例ではゲート酸化膜に厚さの薄い
部分ができていることが分かる。
FIGS. 2A and 2B are diagrams showing gate dielectric breakdown voltage distributions of transfer gate transistors produced according to this embodiment and the conventional example. Here, the gate dielectric breakdown voltage distribution is shown, which was formed by thermally oxidizing the silicon surface to have a thickness of 20 nm at a sufficient distance from the field oxide film. As is clear from FIGS. 2A and 2B, in the method of this embodiment, the distribution is concentrated around 20V, which is the original withstand voltage of a 20 nm thick silicon oxide film. In contrast, in the conventional method, the voltage is concentrated around 16 V, and it can be seen that in the conventional method, a thin portion is formed in the gate oxide film.

【0017】また、本実施例で得られた、ダイナミック
RAMを定格電圧の1.5倍の電源電圧によりスクリー
ニング・テストを実施したところ、98%以上の歩留り
が得られたのに対し、従来の方法で製造したものは69
%の歩留りしか得られなかった。これは、酸化シリコン
膜に注入可能な電荷量と一致する。
Furthermore, when the dynamic RAM obtained in this example was subjected to a screening test using a power supply voltage 1.5 times the rated voltage, a yield of more than 98% was obtained, whereas the conventional 69 products manufactured by the method
% yield was obtained. This matches the amount of charge that can be injected into the silicon oxide film.

【0018】以上のように、本第1の実施例によれば、
ゲート酸化膜の絶縁耐圧が向上し、高性能かつ高品質の
半導体装置を高歩留りで得ることができる。
As described above, according to the first embodiment,
The dielectric breakdown voltage of the gate oxide film is improved, and high performance and high quality semiconductor devices can be obtained at a high yield.

【0019】尚、上記実施例では、シリコン層3として
単結晶シリコンを用いたが、多結晶シリコン層や非晶質
シリコン層でも同様の効果が得られる。又、ゲート電極
として、多結晶シリコンを用いたが、他の材料でも本発
明の効果に何らさしつかえないことは明らかである。
In the above embodiment, single crystal silicon was used as the silicon layer 3, but the same effect can be obtained with a polycrystalline silicon layer or an amorphous silicon layer. Further, although polycrystalline silicon is used as the gate electrode, it is clear that other materials may be used without sacrificing the effects of the present invention.

【0020】図3(a),(b)は本発明の第2の実施
例を説明するための半導体チップの断面図である。
FIGS. 3A and 3B are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

【0021】先ず、図3(a)に示すように、既知の方
法で絶縁分離用のフィールド酸化膜2をシリコン基板1
上に選択的に形成し、ゲート領域のシリコン基板の表面
を露出させる。次に、このシリコン基板1のシリコン表
面が露出している領域のみに、所望の酸化シリコン膜の
厚さの約1/2、例えば8nmの厚さの単結晶のシリコ
ン層5を堆積被着する。この堆積被着方法は、ジクロル
シラン(SiH2 Cl2 )と塩酸(HCl)ガスを
用いた選択エピタキシャル成長法により達成することが
できる。
First, as shown in FIG. 3(a), a field oxide film 2 for insulation isolation is formed on a silicon substrate 1 by a known method.
selectively formed on the silicon substrate to expose the surface of the silicon substrate in the gate region. Next, a single crystal silicon layer 5 having a thickness of about 1/2 of the desired silicon oxide film, for example 8 nm, is deposited only on the exposed silicon surface area of the silicon substrate 1. . This deposition method can be achieved by selective epitaxial growth using dichlorosilane (SiH2 Cl2) and hydrochloric acid (HCl) gas.

【0022】その後図3(b)に示すように、通常の水
素及び酸素ガスの雰囲気下の熱酸化法により、堆積した
単結晶シリコン層5を厚さ20nmの酸化シリコン膜に
変換し、ゲート酸化膜4Aを形成する。以下通常の方法
により多結晶シリコンをゲート電極とするMOS型半導
体装置を製造する。
Thereafter, as shown in FIG. 3(b), the deposited single crystal silicon layer 5 is converted into a 20 nm thick silicon oxide film by a thermal oxidation method in an ordinary hydrogen and oxygen gas atmosphere, and gate oxidation is performed. A film 4A is formed. Thereafter, a MOS type semiconductor device using polycrystalline silicon as a gate electrode is manufactured by a conventional method.

【0023】本第2の実施例では第1の実施例と同じ効
果が得られ、さらに必要とするゲート部分のみにゲート
酸化膜を形成することができる利点がある。
The second embodiment provides the same effects as the first embodiment, and has the additional advantage that the gate oxide film can be formed only on the necessary gate portions.

【0024】[0024]

【発明の効果】以上説明したように本発明の方法は、シ
リコン表面に新たにシリコン層を堆積被着した後、この
シリコン層を熱酸化法で酸化シリコン膜に変換すること
でゲート酸化膜を形成するために、フィールド酸化膜近
傍でも十分離れた所でも同じ膜厚で、かつシリコン表面
を熱酸化して得られる酸化シリコン膜と同等の品質のゲ
ート酸化膜が得られる。さらに、堆積被着するシリコン
層には酸素を含まないため、シリコン基板を直接熱酸化
する際に問題となるシリコン基板表面の酸素濃度を全く
考慮する必要がない。このように本発明の方法によれば
、高性能、高品質の半導体装置を高歩留りで得ることが
できる。
As explained above, the method of the present invention deposits a new silicon layer on the silicon surface and then converts this silicon layer into a silicon oxide film using a thermal oxidation method to form a gate oxide film. In order to form a gate oxide film, it is possible to obtain a gate oxide film that has the same thickness both near the field oxide film and at a sufficiently distant location, and has the same quality as a silicon oxide film obtained by thermally oxidizing the silicon surface. Furthermore, since the deposited silicon layer does not contain oxygen, there is no need to consider the oxygen concentration on the surface of the silicon substrate, which is a problem when directly thermally oxidizing the silicon substrate. As described above, according to the method of the present invention, high-performance, high-quality semiconductor devices can be obtained at a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1の実施例を説明するための半導体
チップの断面図。
FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

【図2】実施例と従来例を用いた場合のゲート絶縁耐圧
分布を示す図。
FIG. 2 is a diagram showing gate dielectric breakdown voltage distribution when using an example and a conventional example.

【図3】本発明の第2の実施例を説明するための半導体
チップの断面図。
FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

【図4】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。
FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1    シリコン基板 2    フィールド酸化膜 3    シリコン層 4,4A,4B    ゲート酸化膜 5    単結晶シリコン層 1 Silicon substrate 2 Field oxide film 3 Silicon layer 4, 4A, 4B Gate oxide film 5 Single crystal silicon layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  シリコン基板上に素子形成領域を分離
するフィールド酸化膜を形成する工程と、前記素子形成
領域の前記シリコン基板表面にシリコン層を形成する工
程と、前記シリコン層を酸化しゲート酸化膜を形成する
工程とを含むことを特徴とする半導体装置の製造方法。
1. A step of forming a field oxide film on a silicon substrate to separate an element formation region, a step of forming a silicon layer on the surface of the silicon substrate in the element formation region, and a step of oxidizing the silicon layer and gate oxidation. 1. A method for manufacturing a semiconductor device, comprising the step of forming a film.
JP9649491A 1991-04-26 1991-04-26 Manufacture of semiconductor device Pending JPH04326576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9649491A JPH04326576A (en) 1991-04-26 1991-04-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9649491A JPH04326576A (en) 1991-04-26 1991-04-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04326576A true JPH04326576A (en) 1992-11-16

Family

ID=14166643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9649491A Pending JPH04326576A (en) 1991-04-26 1991-04-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04326576A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176742A (en) * 1993-12-20 1995-07-14 Nec Corp Manufacture of semiconductor device and semiconductor device
JP2005051225A (en) * 2003-07-10 2005-02-24 Internatl Rectifier Corp Method for forming thick oxide on silicon or silicon carbide for semiconductor device
US7232728B1 (en) 1996-01-30 2007-06-19 Micron Technology, Inc. High quality oxide on an epitaxial layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142278A (en) * 1975-06-02 1976-12-07 Nec Corp Insulated-gate type fet
JPS62199052A (en) * 1986-02-27 1987-09-02 Oki Electric Ind Co Ltd Manufacture of mos type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142278A (en) * 1975-06-02 1976-12-07 Nec Corp Insulated-gate type fet
JPS62199052A (en) * 1986-02-27 1987-09-02 Oki Electric Ind Co Ltd Manufacture of mos type semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176742A (en) * 1993-12-20 1995-07-14 Nec Corp Manufacture of semiconductor device and semiconductor device
US7232728B1 (en) 1996-01-30 2007-06-19 Micron Technology, Inc. High quality oxide on an epitaxial layer
JP2005051225A (en) * 2003-07-10 2005-02-24 Internatl Rectifier Corp Method for forming thick oxide on silicon or silicon carbide for semiconductor device
US7754550B2 (en) 2003-07-10 2010-07-13 International Rectifier Corporation Process for forming thick oxides on Si or SiC for semiconductor devices

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