JPH04102375A - Thin film transistor - Google Patents

Abstract

PURPOSE:To form a highly reliable TFT of high yield without lowering driving characteristics bar forming a gate insulating film of at least two-layer structure of oxide. CONSTITUTION:After an active layer 2 is formed on a quartz substrate 1, a first oxide film 3 and a second oxide film 4 are formed. A gate part is covered with a resist, a poly-Si gate electrode is dry-etched, gate SiO2 (both the two layers) is wet-etched and source/drain parts 2', 2'' are exposed. After P<+> is implanted, activation is performed. A layer insulating film 6 is deposited, a window is opened and an Al electrode 7 is attached. Generation of a pin hole is restrained through two oxide film formation processes and a highly reliable TFT having equivalent driving characteristics as a conventional one can be acquired.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to thin film transistors (TPTs).

[Prior art]

In order to improve the voltage resistance of the gate insulating film, it has already been proposed to form the gate insulating film into a double structure consisting of Si, N4 and SiO□.

(Y, 0hji, T, Kusaka, A, t
(iraiwa, K., Yagi, K., Muka
i and O, Kasahara: ”Re1i
ability of nano-meter
k multi-1ayer dielectri
c on poly-crystallinesi
licon,” Proc, of Interna
tional Re1iability Physics
s Symposium (1987) p. 55) However, when Si and N4 are formed on SiO□, which is the gate insulating film of a thin film transistor (TPT) whose basic material is polycrystalline silicon (PolySi), the film formation method is In a plasma process such as the PCVD method, hydrogen plasma during film formation causes hysteresis, which causes malfunction in transistor operation. Furthermore, since the etching methods for the nitride film and the oxide film are different, when processing the gate insulating film, there is a problem of a decrease in yield due to an increase in the number of steps and a concomitant decrease in processing accuracy during etching. Furthermore, when driving a normal TPT, the thinner the gate insulating film and the larger the capacitance, the better the opening characteristics.However, in the two-layer structure with the Si3N4 film, the capacitance of the Si3N4 layer is larger than the capacitance of 5io2i. This structure, which is equivalent to arranging 3102 layers in series, is greatly influenced by the thickness of the 3102 layer, which has a small capacitance. Therefore, SiO
□It is unavoidable to create a two-layer structure where the layers are made thinner than necessary.

〔the purpose〕

An object of the present invention is to eliminate the above-mentioned disadvantages and at the same time form a TPT with high reliability and high yield without degrading the driving characteristics of the thin film transistor due to the two-layer structure.

〔composition〕

The present invention relates to a thin film transistor, in which a gate insulating film of the thin film transistor provided on an insulating substrate has at least a two-layer structure of oxide. Note that in the present invention, it is preferable that the thickness of at least the oxide film of the gate insulating film on the side closer to the active layer is 500 Å or less.

Figure 4 shows the conventional structure of TDDB (Time Depeudowt Die) with Si and NJSi022 layer structure.
electric breakdown) characteristics. S
It can be seen that the two-layer structure has a longer service life for stress time by about four orders of magnitude compared to the iO□ single layer.

The structure of the present invention is shown in FIG. 1. By making the TPT gate insulating film made of Po1ySi as a basic material into a 5in2 two-layer structure, it has a lifespan comparable to that of Si, N, /SiO2 shown in FIG. 4. In Figure 4, the upper gate insulating film is a 5i film formed by deposition by ECR, CVD, etc.
The lower gate insulating film is preferably a thermal oxide film or an anodic oxide film. In this case, since the floating characteristics vary greatly depending on the quality and thickness of the lower gate insulating film, it is important to optimize this layer. Figure 3 shows the process for SiO□ single layer and double layer (in this case, the base is a thermal oxide film of 500 layers) with a total film thickness of 900 layers. A comparison of n and gate leakage current is shown. By forming 5in2 into two layers, the gate leakage current is reduced by one order of magnitude or less compared to the conventional structure. Ion showing maneuverability
7.95 x 10-'A is 5.5 x
Although there was a decrease of about 30% to 10-'A, it became clear that it was possible to maintain a practically problem-free level. Here, the thickness of the underlying SiO□ was set at 500, but it was found that making it thinner than this would improve Ion and gate leakage current, which would be more convenient. This means that a base 5in2 film of 500 Å or less is sufficient as long as it has a thickness that guarantees transistor characteristics (the thickness of the entire 5in2 film is constant). A method of forming these structures is shown in FIG. ■PolyS on the insulating substrate 1
After forming and processing i2, ■ thermal oxide film 3, DePOa film 4
and the gate electrode 5 are sequentially deposited, 1) after being processed into a predetermined shape, 2) impurities are diffused and activated in the gate and/or source and drain by a method such as ion implantation, and 2) the glabella insulating film 6 is deposited. , After contact hole formation, ■
AQ is deposited and processed to form the electrode 7 and complete the TPT.

〔Example〕

LPCVD method on quartz substrate 1 at 20℃, 0.1torr
r, 5iH4100% Te approximately 1000 people (7) Poly
After depositing Si and forming active layer 2, dry 02100
0'C11 o'clock! A thermal oxide film 3 of approximately 500 layers is formed (formation of the first oxide film 3). Then, low temperature oxide film (LTO) or high temperature oxide film (HTO) is formed by LPCVD.
method (Sil (4102: 80/20secM, approximately 10
A second oxide film 4 is formed using a method (000 persons), and a PolySi 5 is further formed under the same conditions as before. in this case,
Only the film thickness will be increased to 3,000 people. Next, cover the gate part with resist and perform SFI; 30secM, 0, 1
Torr 1'Po1ySi gate electrode was dry etched and the gate 5iO was etched with HF:H20=1:6.30''.
2 (both layers) are wet-etched to expose the source and drain parts 2' and 2''.Then, P is etched by ion implantation.
After implanting l with IE15■-2, activate it at 900°C for 130 minutes.
H4102=80/ 5000 people's eyebrows #l at 200secM! A rim film 6 is deposited and contact holes are made by wet etching (under the same conditions as described above). -Finally Afl
was formed to a thickness of 1 μm by sputtering, and an electrode 7 of a predetermined shape was formed by dry etching (c2F6+5ic14 system).
Process and complete.

〔effect〕

In the present invention, the oxide film forming process is performed twice in order to form two layers. Therefore, even if there are pinholes in each layer, 1
Since the locations where pinholes occur are different between the first layer and the second layer, the occurrence of pinholes is suppressed. 1 for this
In the case of layers, no matter how thick they are, pinholes cannot be completely eliminated.

The thin film transistor of the present invention makes it possible to provide a TPT that is more reliable than conventional products and has drive characteristics equivalent to conventional products.

This TPT is extremely useful as a semiconductor device such as an optical reader.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the basic configuration of the TPT of the present invention, and FIG.
Diagram A shows the Io
n (Nch) (X 10-'A ], and B indicates the gate leakage current of both. Fig. 3 shows an example of the manufacturing process of the TPT of the present invention with ■ to ■. Fig. 4 shows the conventional TPT. Si3N
Examples of TDDB characteristics of various insulating films on 4/5i022 layer structure type Po1y-5i are shown. 1... Insulating substrate 2... Po1ySi (active layer) 2', 2''... Source, drain part 3... Thermal oxide film (lower gate insulating film) 4... Depo
Oxide film (upper gate M edge film) 5...gate electrode
6... Interlayer insulating film 7... 11 Electrode Patented Kenjin Co., Ltd. Figure 3 Figure 4 Stress 1 (Sl

Claims (1)

[Scope of Claims] 1. A thin film transistor characterized in that a gate insulating film of the thin film transistor provided on an insulating substrate has at least a two-layer structure of oxide. 2. The thin film transistor according to claim 1, wherein the oxide film of the gate insulating film at least on the side closer to the active layer has a thickness of 500 Å or less.