JPS6159873A - Thin film field effect transistor and manufacture thereof - Google Patents
Thin film field effect transistor and manufacture thereofInfo
- Publication number
- JPS6159873A JPS6159873A JP18171784A JP18171784A JPS6159873A JP S6159873 A JPS6159873 A JP S6159873A JP 18171784 A JP18171784 A JP 18171784A JP 18171784 A JP18171784 A JP 18171784A JP S6159873 A JPS6159873 A JP S6159873A
- Authority
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- Japan
- Prior art keywords
- layer
- silicon compound
- semiconductor layer
- compound semiconductor
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 239000010409 thin film Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 77
- 150000003377 silicon compounds Chemical class 0.000 claims abstract description 42
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 229910001120 nichrome Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- -1 hydrogen compound Chemical class 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置にかかわり、と夛わけ非晶質シリコ
ン、微結晶シリコン等のシリコン化合物半導体薄膜を用
いた薄膜電界効果トランジスタおよび製造方法（以降Ｔ
ＰＴと略す）に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and more particularly to thin film field effect transistors and manufacturing methods (hereinafter referred to as T
(abbreviated as PT)).
従来例の構成とその問題点
第１図は、従来開発された半導体の活性＠域に非晶質ン
ソコン化合物半導体水素化合物、フ、素化合物、ゲルマ
ニウム［−化合物ｅｔｃをもちいだＴＦＴの工程断面図
である。まず、第１図（ａｌに示すように、絶縁性基板
１上にゲートとなる第１の金、回層２（たとえばＭｏ
、 Ｃｒ 、 ＮｉＣｒ等）を選択的に被着形成する。Structure of a conventional example and its problems Figure 1 is a cross-sectional view of the process of a TFT that uses an amorphous compound semiconductor, a hydrogen compound, an elemental compound, a germanium [- compound, etc.] in the active region of a conventionally developed semiconductor. It is. First, as shown in FIG. 1 (al), a first gold layer 2 (for example, Mo
, Cr, NiCr, etc.) are selectively deposited.
ついで全面に第１の絶縁層３（たとえば窒化シリコン、
酸化シリコン等）、非晶質シリコン化合物半導体層４た
とえば水素化非晶質シリコン（以降ｉ層と略す）、そし
て第２の絶縁層５を順次被着する。Next, a first insulating layer 3 (for example, silicon nitride,
(silicon oxide, etc.), an amorphous silicon compound semiconductor layer 4 such as hydrogenated amorphous silicon (hereinafter abbreviated as i-layer), and a second insulating layer 5 are sequentially deposited.
次に第１図（ｂ）に示したように第２の絶縁層５を第１
の金属層２と重なった部分でＴＦＴのチャンネルとなる
べき部分は少なくとも残し、そうして１層４を選択びフ
にほとんど露出した後に全面に不純物を含む非単結晶シ
リコン化合物半導体層６たとえばＰをドープしたｎ型非
晶質シリコン層（以降ｎ＋層と略す）を被着する。その
後、第１図（Ｃ）に示したように、ｎ＋６ 、ｉ層４．
を選択的に除去して、第２の絶縁層を残した部分５を含
む島状の非晶質シリコン層（６′＋ ４′）を形成する
。Next, as shown in FIG. 1(b), the second insulating layer 5 is
At least a portion of the layer 4 that overlaps with the metal layer 2, which should become the channel of the TFT, is left, and after the first layer 4 is almost completely exposed, a non-single-crystal silicon compound semiconductor layer 6 containing impurities is formed on the entire surface, for example, P. An n-type amorphous silicon layer (hereinafter referred to as n+ layer) doped with n-type amorphous silicon is deposited. Thereafter, as shown in FIG. 1(C), the n+6, i-layer 4.
is selectively removed to form an island-shaped amorphous silicon layer (6'+4') including a portion 5 in which the second insulating layer remains.
さらに、第１の金、次層２への接続を与えるための開口
部７を第１の絶縁層３に形成した後に、全面に第２の金
属ＦＩ９を被着し、１．多４上に被着されたｎ＋層６り
上を含んで第１の絶縁層３上にはソース・ドレイン配線
８を、また曲記開口部７を含んで第１の絶縁層３上には
ゲート配線９を形成する。最後にソース・ドレイン配線
８をマスクとして第２の絶縁層５′上のｎ＋層を除去し
て第１図（ｄ）に示すように従来の薄膜電界効果トラン
ジスタが完成する。Furthermore, after forming an opening 7 in the first insulating layer 3 for providing a connection to the first gold layer 2, a second metal FI9 is deposited over the entire surface, 1. A source/drain wiring 8 is provided on the first insulating layer 3 including the n+ layer 6 deposited on the layer 4, and a source/drain wiring 8 is provided on the first insulating layer 3 including the opening 7. Gate wiring 9 is formed. Finally, using the source/drain wiring 8 as a mask, the n+ layer on the second insulating layer 5' is removed to complete a conventional thin film field effect transistor as shown in FIG. 1(d).
従来のＴＰＴでは、半導体の活性＠域に非晶質シリコン
層４′をもちいているため、有効電子移動度が０．１〜
１．○、、ｌ／Ｖ、ｓｅｃと低い。それでも高速動作や
大きなＯＮ電流を必要としない液晶セルと組み合せるこ
とによって画像表示装置を構成するＴＦＴのスイッチン
グアレイを得ることはできる。しかし半導体の活性領域
に非晶、質シリコンを用いる限り、画像入力信号処理回
路を構成するに充分な応答速度が得られない。Conventional TPT uses an amorphous silicon layer 4' in the active @ region of the semiconductor, so the effective electron mobility is 0.1~
1. ○, l/V, sec is low. Even so, it is possible to obtain a TFT switching array that constitutes an image display device by combining it with a liquid crystal cell that does not require high-speed operation or a large ON current. However, as long as amorphous silicon is used in the active region of the semiconductor, a response speed sufficient for constructing an image input signal processing circuit cannot be obtained.
ところで、微結晶シリコン化合物半導体の有効電子易動
度は、非晶質シリコン化合物半導体のものの数倍程度大
きい。従って、半導体の活性＠域としてゲート絶縁膜に
続いて微結晶シリコン化合物半導体を被着形成すれば良
いのだが、この場合。Incidentally, the effective electron mobility of a microcrystalline silicon compound semiconductor is several times larger than that of an amorphous silicon compound semiconductor. Therefore, in this case, it is sufficient to deposit a microcrystalline silicon compound semiconductor following the gate insulating film as the active region of the semiconductor.
■微結晶シリコン化合物半導体をグロー放電分解法によ
っ製膜する場合、製膜条沖の高周波電力が大きく（後述
）、ゲート絶縁膜と半導体層との界面のダメージが大き
いこと、■グロー放電とともに基板表面温度が上昇し、
水素分子及び原子が膜中から扱けることの二つの原因で
、界面坐位密度がかなり大きくなり電気的特性が不安定
で劣悪である。■When forming a microcrystalline silicon compound semiconductor film by glow discharge decomposition method, the high frequency power outside the film formation layer is large (described later), and the interface between the gate insulating film and the semiconductor layer is severely damaged. The surface temperature increases,
Due to the two reasons that hydrogen molecules and atoms can be handled from within the film, the interfacial sitting density becomes considerably large and the electrical properties are unstable and poor.
発明の目的
本発明は、半導体の活性領域に電子易動度の大きい微結
晶シリコン化合物半導体をうまくもちいて、従来の方法
では実現できなかった高速動作を可能にするだめの改菩
すべき一つのテーマとして、薄膜電界効果トランジスタ
の電子易動度を高めることが目的である。Purpose of the Invention The present invention utilizes a microcrystalline silicon compound semiconductor with high electron mobility in the active region of a semiconductor to achieve high-speed operation that could not be achieved with conventional methods. The purpose of this research is to increase the electron mobility of thin film field effect transistors.
発明の構成
本発明によるＴＰＴは、電子易動度を高めるために、半
導体層に微結晶シリコン化合物をもちいる際絶縁膜と微
結晶シリコン化合物層との間に、非晶質シリ・コン化合
物層をもうけだ。Structure of the Invention The TPT according to the present invention includes an amorphous silicon compound layer between an insulating film and a microcrystalline silicon compound layer when a microcrystalline silicon compound is used as a semiconductor layer in order to increase electron mobility. I made a profit.
これにより従来より優れていた絶縁膜と非晶質シリコン
化合物半導体層との界面準位密度を小さくたもちつつ、
微結晶シリコン化合物半導体の製作時の物理化学現象を
利用して、非晶質シリコン化合物半導体と微結晶シリコ
ン化合物半導体との界面学位を良好にし、エネルギー学
位密度の低下をはかると伴に、電子易動度の大きい微結
晶シリコン化合物半導体を導入し、電子易動度の高いＴ
ＦＴを製作した。As a result, while maintaining the interface state density between the insulating film and the amorphous silicon compound semiconductor layer, which was superior to the conventional one,
Utilizing physical and chemical phenomena during the production of microcrystalline silicon compound semiconductors, we aim to improve the interface between amorphous silicon compound semiconductors and microcrystalline silicon compound semiconductors, reduce energy density, and improve electronic compatibility. Introducing a microcrystalline silicon compound semiconductor with high mobility, T
I made FT.
実施例の説明
第２図は、本発明の一実施例における半導体装置の工程
断面図を示すものである。なお同一機能の各部について
は、第１図と同じ番号を付す。DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Note that parts with the same functions are given the same numbers as in FIG. 1.
まず第２図（ｄ）に示すように絶縁性基板１例えばガラ
ス板上にゲート電極及びゲート配線となる第１の金属層
２例えばＣｒ 、 ＮｉＣｒ 、 Ｍｏなどを選択的に
被着形成する。次いで全面にまずゲート絶縁層３として
例えば窒化ンリコン層、酸化シリコン層などを、次に第
１の半導体層として非晶質シリコン化合物半導体層１４
（以降１１と略す）例えば水素化非晶質シリコン２７ノ
素化非晶質シリコン、炭化非晶質シリコンなどを、続い
て第２の半導体層とし微結晶シリコン化合物半導体層２
４（以降１２と略す）例えば水素化微結晶シリコン。First, as shown in FIG. 2(d), a first metal layer 2 such as Cr, NiCr, Mo, etc., which will become a gate electrode and gate wiring, is selectively deposited on an insulating substrate 1, such as a glass plate. Next, a gate insulating layer 3 such as a silicon nitride layer or a silicon oxide layer is formed on the entire surface, and then an amorphous silicon compound semiconductor layer 14 is formed as a first semiconductor layer.
(hereinafter abbreviated as 11) For example, hydrogenated amorphous silicon 27, hydrogenated amorphous silicon, carbide amorphous silicon, etc. are then used as the second semiconductor layer, and a microcrystalline silicon compound semiconductor layer 2
4 (hereinafter abbreviated as 12), for example, hydrogenated microcrystalline silicon.
フッ素化微結晶ンリコンなどを、さらに続いて第２の絶
縁層５例えば窒化シリコン、酸化シリコンなどを順次被
着する。Fluorinated microcrystalline silicon or the like is successively deposited, followed by a second insulating layer 5 such as silicon nitride or silicon oxide.
これら絶縁膜及び半導体膜の被着方法は、容量結合型高
周波グロー放電法による。原料ガスとしては、絶縁層３
，５に窒化ンリコン層を得るならＳｔＨ、ＮＨ３，Ｎ２
の混合ガスを使用し、非晶質シリコン化合物半導体
層１４（１１）に水素化非晶質シリコン層を得るならＳ
ｉＨａを使用し、真空度０．６ Ｔｏｒｒ 、基板温
度３００℃、高周波電力１２Ｗ（電極直径３０ｃｒｎ）
＋電極距離２１閲で得られる。また微結晶シリコン化合
物半導体層２４（ｉ２層）に水素化微結晶シリコンを得
るなら、５１Ｈ４，５５ｃｃｒｎｒ Ｈ２１５０Ｓｃｃ
ｍの混合ガスを使用し、真空度１．４Ｔｏｒｒ 、基板
温度２６０℃。The method for depositing these insulating films and semiconductor films is a capacitively coupled high frequency glow discharge method. As the raw material gas, the insulating layer 3
, 5 to obtain a silicon nitride layer, StH, NH3, N2
If a hydrogenated amorphous silicon layer is obtained in the amorphous silicon compound semiconductor layer 14 (11) using a mixed gas of S.
Using iHa, vacuum degree 0.6 Torr, substrate temperature 300℃, high frequency power 12W (electrode diameter 30crn)
+ Electrode distance obtained by 21 views. Moreover, if hydrogenated microcrystalline silicon is to be obtained in the microcrystalline silicon compound semiconductor layer 24 (i2 layer), 51H4, 55ccrnr H2150Scc
Using a mixed gas of m, the degree of vacuum was 1.4 Torr, and the substrate temperature was 260°C.
１３、５６）Ｋ ノ高周波電力２５０Ｗ（電極直径３０
ｃｒｎ）、電極間距離２２酎で得られる。13,56) K high frequency power 250W (electrode diameter 30
crn), obtained with an interelectrode distance of 22 mm.
次に第２図（ｂ）に示したように、第２の絶縁層５を第
１の金属層２と重なった所でＴＦＴのチャンネルとなる
べき部分は少なくとも残して、１１層１４と１２層２４
を選択的にほとんどの部分を露出させた後に全面に不純
物を含む非単結晶シリコン化合物半導体層（以降は仮り
にｎ＋−μＣ層と略す）６を被着する。例えばＰをドー
プしたｎ型水素化微結晶シリコ７層６を被着する場合、
その条件は、ＳｉＨ６ｓｃｃｒｎ、 Ｈ２１５０ｓｃ
ｃＩｎ、 ＰＲ。Next, as shown in FIG. 2(b), the 11th layer 14 and the 12th layer are formed, leaving at least a portion where the second insulating layer 5 overlaps with the first metal layer 2 to become the channel of the TFT. 24
After selectively exposing most parts, a non-single-crystal silicon compound semiconductor layer (hereinafter abbreviated as n+-μC layer) 6 containing impurities is deposited on the entire surface. For example, when depositing a P-doped n-type hydrogenated microcrystalline silicon 7 layer 6,
The conditions are SiH6sccrn, H2150sc
cIn, P.R.
０、０５ ｓ ＣＣｒｎ の混合ガスを使用し、真空
度１．４Ｔｏｒｒ 、基板温度２５０℃、高周波電力２
００Ｗ（電極直径３０ ｃｍ ）、電極距離２１叫であ
る。A mixed gas of 0.05 s CCrn was used, the degree of vacuum was 1.4 Torr, the substrate temperature was 250°C, and the high frequency power was 2.
00W (electrode diameter 30 cm), electrode distance 21 cm.
得られた膜の比抵抗は１ｏ Ω／口、活性エネルギー０
．０２ ｅＶであった。The specific resistance of the obtained film was 10 Ω/mouth, and the active energy was 0.
．． 02 eV.
その後、第２図（Ｃ）に示したように、ｎ＋−μＣ層６
．１２層２４．１１層１４を選択的に除去して、第２の
絶縁層を残した部分５′を含み島状に形成する。Thereafter, as shown in FIG. 2(C), the n+-μC layer 6
．． 12 layers 24 and 11 layers 14 are selectively removed to form an island shape including a portion 5' where the second insulating layer remains.
さらに第１の金属層２への接続を与えるための開口部７
を第１の絶縁層３に形成した後に、全面に第２の金属層
９例えばＡＱ 、 Ｃｒ 、 ＮｉＣｒ 、Ａｕなどを
被着し、 １１層１４′ 、１２層２４′上に被着され
たｎ＋−μＣ層６り上を少なくとも一部含んで、第１の
絶縁層３上にはソース・ドレイン配線８を、また卯記開
口部７を含んで第１の絶縁層３上にはゲート配ａ９を形
成する。Opening 7 for further providing a connection to the first metal layer 2
After forming on the first insulating layer 3, a second metal layer 9 such as AQ, Cr, NiCr, Au, etc. is deposited on the entire surface, and the n+ layer deposited on the 11th layer 14' and the 12th layer 24'. - A source/drain wiring 8 is provided on the first insulating layer 3, including at least a portion of the upper surface of the μC layer 6, and a gate wiring a9 is provided on the first insulating layer 3, including the opening 7. form.
最後にソース・ドレイン配線８をマスクとして、第２の
絶縁層５′ 上のｎ＋−μＣ層を除去して、第２図（ｄ
）に示すように本発明のＲ膜電界効果トランジスタが完
成する。Finally, using the source/drain wiring 8 as a mask, the n+-μC layer on the second insulating layer 5' is removed, and the layer shown in FIG.
), the R film field effect transistor of the present invention is completed.
第１の半導体層として７１１Ｍする非晶質シリコン化合
物半導体層１４の膜厚は、２０００Å以上では従来の半
導体活性領域に非晶質シリコン化合物半導体のみをもち
いたＴＰＴの特性とさほどかわらず、また前記第１の半
導体層１４の膜厚が２ωÅ以下では従来の半導体活性領
域に微結晶シリコン化合物半導体のみをもちいたＴＰＴ
と同様、ゲート絶縁膜と半導体層との界面学位密度がか
なり大きく、電気的特性の大きな改善は見られなかった
。When the film thickness of the amorphous silicon compound semiconductor layer 14 of 711M as the first semiconductor layer is 2000 Å or more, the characteristics are not much different from those of conventional TPT using only an amorphous silicon compound semiconductor in the semiconductor active region. When the thickness of the first semiconductor layer 14 is 2ωÅ or less, conventional TPT using only a microcrystalline silicon compound semiconductor in the semiconductor active region is used.
Similarly, the interface density between the gate insulating film and the semiconductor layer was quite large, and no significant improvement in electrical characteristics was observed.
しかしゲート絶縁膜に続く第１の半導体層として非晶質
シリコン化合物半導体層１４（ここでは水素化非晶質シ
リコンをもちいた）の膜厚を５００人波着し、第２の半
導体層として微結晶シリコン本発明によるＴＦＴでは、
絶縁膜と半導体層との界面単位密度を低く保つため、ま
ず第１の半導体層として非晶質ンリコン化合物半専体層
を被着した。またそのＴＰＴの空え層が大きく広がり、
第２の半導体層にまで広がることを利用して、第２の半
導体層に、電子易動度の大きい微結晶シリコン化合物半
導体をもちい前記目的を達成した。However, the film thickness of the amorphous silicon compound semiconductor layer 14 (here, hydrogenated amorphous silicon was used) was increased to 500 nm as the first semiconductor layer following the gate insulating film, and In the crystalline silicon TFT according to the present invention,
In order to keep the interfacial unit density between the insulating film and the semiconductor layer low, a semi-exclusive layer of an amorphous phosphor compound was first deposited as the first semiconductor layer. In addition, the empty layer of TPT has expanded greatly,
Taking advantage of the fact that it spreads to the second semiconductor layer, the above object was achieved by using a microcrystalline silicon compound semiconductor with high electron mobility for the second semiconductor layer.
尚、第１の半導体層として具体的に用いた水素化非晶質
シリコン層は、たとえば高周波電力１２Ｗで製作され、
次に続く第２の半導体層として具体的に用いた水素化微
結晶シリコン膜は、たとえば高周波電力２５０Ｗと約２
０倍の電力で製作されるが、第１の半導体層の膜厚が５
００人の場合第２の半導体層被着時の水素プラズマを主
体とするプラズマに、絶縁膜と第１の半導体層との界面
は影響を受けずに、第１の半導体層と第２の半導体層と
の界面となる表面は、前記プラズマにさらされ欠陥が補
償されるため、エネルギー学位密度の大きな増大を伴な
わずに、連続的に第２の半導体層が被着される。また第
２の半導体層被着に要する時間は十数分間と短時間であ
り、そのプラズマによる基板表面温度もさほど上昇しな
いので電気的特性の優れた有効電子易動度の大きいＴＰ
Ｔが得られた。Note that the hydrogenated amorphous silicon layer specifically used as the first semiconductor layer was manufactured using, for example, a high frequency power of 12 W.
The hydrogenated microcrystalline silicon film specifically used as the subsequent second semiconductor layer has a high frequency power of 250 W and about 2
It is manufactured with 0 times the power, but the thickness of the first semiconductor layer is 5
In the case of 00 people, the interface between the insulating film and the first semiconductor layer is not affected by the plasma mainly composed of hydrogen plasma when the second semiconductor layer is deposited, and the first semiconductor layer and the second semiconductor layer are The surface which forms the interface with the layer is exposed to the plasma and defects are compensated for, so that the second semiconductor layer can be deposited successively without a significant increase in the energy density. In addition, the time required for depositing the second semiconductor layer is as short as ten minutes, and the substrate surface temperature due to the plasma does not rise significantly.
T was obtained.
第１図ｆ−）〜（ｄ）は従来の工程断面図、第２図（ａ
）〜（ｄ）は本発明の一実施例のＴＦＴの概略工程断面
７である。
１・・・・・絶縁性基板、２・・・・・・第１の金属層
、３・・・・・・第１の絶縁層、１４ 、１４’・・・
・・・非晶質シリコン化合物半導体層、５．ｄ・・・・
・・第２の絶縁層、ら。
６（・・・・・非単結晶ンリコ／化合物半導作、＠、８
・・・・・・ンース・ドレイン配線、９・・・・・・ゲ
ー１１．２４１２４′・・・・・・微結晶シリコン化合
物半導体層。
代理人の氏名 弁理士 中 尾 軟 男 ほか１名第１
図
第１図
５′Figure 1 f-) to (d) are cross-sectional views of the conventional process, and Figure 2 (a)
) to (d) are schematic process cross-sections 7 of a TFT according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... First metal layer, 3... First insulating layer, 14, 14'...
...Amorphous silicon compound semiconductor layer, 5. d...
...Second insulating layer, et al. 6 (...Non-single crystal non-crystalline/compound semiconductors, @, 8
. . . drain wiring, 9 . . . 11.24124' . . . Microcrystalline silicon compound semiconductor layer. Name of agent: Patent attorney Souo Nakao and 1 other person
Figure 1 Figure 5'
Claims (2)
的に形成され、第１の絶縁層を介して第１の金属層を含
む絶縁性基板上に、第１の半導体層として非晶質シリコ
ン化合物半導体層、第２の半導体層として微結晶シリコ
ン化合物半導体層の二層が島状に選択形成され、前記二
層からなる島状の半導体層上で第１の金属層と一部重な
り合うように形成された１対の不純物を含む非単結晶シ
リコン化合物半導体層をソース・ドレインとし、このソ
ース・ドレインを除く前記二層からなる島状の半導体層
上には第２の絶縁層が選択形成され、前記不純物を含む
非単結晶シリコン層よりなるソース・ドレイン上に第２
の金属層よりなるソース・ドレイン配線が形成されてい
ることを特徴とする薄膜電界効果トランジスタ。(1) A first metal layer serving as a gate is selectively formed on an insulating substrate, and a first semiconductor layer is formed on the insulating substrate containing the first metal layer via the first insulating layer. Two layers, an amorphous silicon compound semiconductor layer and a microcrystalline silicon compound semiconductor layer as a second semiconductor layer, are selectively formed in an island shape, and the first metal layer and the first metal layer are formed on the island-shaped semiconductor layer consisting of the two layers. A pair of impurity-containing non-single-crystal silicon compound semiconductor layers formed so as to partially overlap are used as a source and a drain, and a second insulating layer is formed on the island-shaped semiconductor layer consisting of the two layers except for the source and drain. is selectively formed, and a second layer is formed on the source/drain made of the non-single crystal silicon layer containing impurities.
A thin film field effect transistor characterized in that source/drain wiring is formed of a metal layer.
する工程と、全面に第１の絶縁層、第１の半導体層とし
て非晶質シリコン化合物半導体層、第２の半導体層とし
て微結晶シリコン化合物半導体層、第２の絶縁層を順次
形成する工程と、第１の金属層と重なった部分で、チャ
ンネルとなるべき部分は、少なくとも第２の絶縁層を残
す工程と、全面に不純物を含む非単結晶シリコン化合物
半導体層を形成する工程と、前記第２の絶縁層を残した
部分を含んで不純物を含む非単結晶シリコン化合物半導
体層と前記第２、第１の半導体層である微結晶シリコン
化合物半導体層、非晶質シリコン化合物半導体層の三層
を島状に形成する工程と、前記第２の絶縁層を残した部
分以外の前記三層よりなる島部の少なくとも一部を含ん
で第２の金属層を選択的に被着形成する工程と、前記第
２の金属層をマスクとして第２の絶縁層上の不純物を含
む非単結晶シリコン化合物半導体層を除去する工程とか
らなる薄膜電界効果トランジスタの製造方法。(2) A step of selectively depositing a first metal layer on an insulating substrate, and forming the first insulating layer on the entire surface, an amorphous silicon compound semiconductor layer as the first semiconductor layer, and a second semiconductor layer. a step of sequentially forming a microcrystalline silicon compound semiconductor layer and a second insulating layer as layers; a step of leaving at least the second insulating layer in a portion that overlaps with the first metal layer and is to become a channel; forming a non-single-crystal silicon compound semiconductor layer containing impurities over the entire surface; a non-single-crystal silicon compound semiconductor layer containing impurities including a portion where the second insulating layer is left; and the second and first semiconductors. A step of forming three layers, a microcrystalline silicon compound semiconductor layer and an amorphous silicon compound semiconductor layer, into an island shape, and at least the island portion made of the three layers other than the portion where the second insulating layer is left. selectively depositing a second metal layer on the second insulating layer, using the second metal layer as a mask, and removing the impurity-containing non-single-crystal silicon compound semiconductor layer on the second insulating layer; A method for manufacturing a thin film field effect transistor comprising steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18171784A JPS6159873A (en) | 1984-08-31 | 1984-08-31 | Thin film field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18171784A JPS6159873A (en) | 1984-08-31 | 1984-08-31 | Thin film field effect transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6159873A true JPS6159873A (en) | 1986-03-27 |
Family
ID=16105632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18171784A Pending JPS6159873A (en) | 1984-08-31 | 1984-08-31 | Thin film field effect transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6159873A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214476A (en) * | 1985-03-19 | 1986-09-24 | Agency Of Ind Science & Technol | Thin-film transistor |
| JPH021174A (en) * | 1988-03-04 | 1990-01-05 | Hitachi Ltd | Thin-film field-effect element |
| US4979006A (en) * | 1988-05-30 | 1990-12-18 | Seikosha Co., Ltd. | Reverse staggered type silicon thin film transistor |
| EP0535979A2 (en) * | 1991-10-02 | 1993-04-07 | Sharp Kabushiki Kaisha | A thin film transistor and a method for producing the same |
| JPH0728092A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Production of driving circuit built-in type liquid crystal display device |
| EP0744776A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method preparing same |
| US5796116A (en) * | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
| US5808316A (en) * | 1995-05-25 | 1998-09-15 | Central Glass Company, Limited | Microcrystal silicon thin film transistor |
| US5834345A (en) * | 1995-09-28 | 1998-11-10 | Nec Corporation | Method of fabricating field effect thin film transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5886776A (en) * | 1981-11-19 | 1983-05-24 | Matsushita Electric Ind Co Ltd | Manufacture of mos type transistor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
-
1984
- 1984-08-31 JP JP18171784A patent/JPS6159873A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5886776A (en) * | 1981-11-19 | 1983-05-24 | Matsushita Electric Ind Co Ltd | Manufacture of mos type transistor |
| JPS59113667A (en) * | 1982-12-20 | 1984-06-30 | Fujitsu Ltd | Manufacture of thin film transistor |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61214476A (en) * | 1985-03-19 | 1986-09-24 | Agency Of Ind Science & Technol | Thin-film transistor |
| JPH055186B2 (en) * | 1985-03-19 | 1993-01-21 | Kogyo Gijutsu Incho | |
| JPH021174A (en) * | 1988-03-04 | 1990-01-05 | Hitachi Ltd | Thin-film field-effect element |
| US4979006A (en) * | 1988-05-30 | 1990-12-18 | Seikosha Co., Ltd. | Reverse staggered type silicon thin film transistor |
| EP0535979A2 (en) * | 1991-10-02 | 1993-04-07 | Sharp Kabushiki Kaisha | A thin film transistor and a method for producing the same |
| JPH0728092A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Production of driving circuit built-in type liquid crystal display device |
| US5796116A (en) * | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
| US6271062B1 (en) | 1994-07-27 | 2001-08-07 | Sharp Kabushiki Kaisha | Thin film semiconductor device including a semiconductor film with high field-effect mobility |
| EP0744776A2 (en) * | 1995-05-25 | 1996-11-27 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method preparing same |
| US5808316A (en) * | 1995-05-25 | 1998-09-15 | Central Glass Company, Limited | Microcrystal silicon thin film transistor |
| US5834796A (en) * | 1995-05-25 | 1998-11-10 | Central Glass Company, Limited | Amorphous silicon thin film transistor and method of preparing same |
| US5834345A (en) * | 1995-09-28 | 1998-11-10 | Nec Corporation | Method of fabricating field effect thin film transistor |
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