JPS63200572A - Manufacture of thin film semiconductor device - Google Patents

Abstract

PURPOSE:To improve the leakage current and the dielectric strength characteristic of a thin film semiconductor device by increasing the thicknesses of a source region and a drain region larger than that of a channel region, selectively melting the drain region only to the source region to preferably contact it therewith at the time of beam annealing. CONSTITUTION:A semiconductor film 2 is deposited on an insulating substrate 1, annealed with an energy beam 11 to crystallize the film 2, thereby obtaining a recrystalline semiconductor film 21. A semiconductor film 3 having a small specific resistance is deposited on the film 21, and an N<+> type a-Si is deposited, for example, by a plasma CVD method in case of an N-channel TFT. The source, drain sections remain by a photolithographic technique, and the other is removed by etching. The films 3, 21 are partly etched by the etching so that the thicknesses of the regions 4, 5 become larger than that of the region 6. The regions 4, 5 are selectively melted by the beam 11 to improve the contact. Thereafter, a gate electrode 8, a source electrode 9 and a drain electrode 10 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a method of fabricating thin film transistors (TPT) on insulators.

[Summary of the invention]

In the process of manufacturing TPT on an insulator by beam annealing, the present invention has the advantage that when the source and drain regions are beam annealed to lower their resistance, the film thickness of the source and drain regions is smaller than the film thickness of the channel region. By melting only the source and drain regions so that they are thicker, for example twice as thick, the contact between the source and drain portions becomes better, making it possible to improve characteristics such as reducing leakage current and increasing breakdown voltage.

[Conventional technology and its problems]

Process diagrams of the conventional embodiment are shown in FIG. 2 (al to dl).

In the step of FIG. 2 fbl, when etching the second semiconductor film that will become the source and drain regions, the film thickness of the source region 4 and drain region 5 is is approximately the same as the film thickness of the channel region 6. Therefore, when the second semiconductor film 3 is annealed with the beam energy 11, it becomes impossible to selectively melt only the source region 5 and the drain region 6. Therefore, the contact between the source and drain portions was insufficient, and the characteristics of the manufactured TPT were such that leakage current was large and the withstand voltage between the source and drain was low.

[Means for solving problems]

In order to solve the above problems, the present invention has the following features:
[As shown in 01, source region 4 and drain region 5
The film thickness of the channel region 6 was made thicker than that of the channel region 6, and the source and drain portions were beam annealed so that the source region 4 and the drain region 5 were selectively melted.

[Effect]

FIG. 1 (in bl, source region 4 and drain region 5
As the film thickness of the channel region 6 becomes larger than that of the channel region 6, the difference in absorption of the beam energy 11 becomes larger. Therefore, it becomes possible to selectively melt only the source and drain regions.

〔Example〕

The present invention will be explained below with reference to the drawings. Figure 1 (al~
(dl is a cross-sectional view for explaining the process of the first embodiment of the present invention. FIG. Examples of the insulating substrate 1 include quartz, alkali-free glass, glass containing impurities such as alkali, and the surface thereof coated with an insulating material to prevent diffusion of impurities from the glass.

Here, a glass substrate that can be used in a 550°C process is used.

Next, as an example of the first semiconductor film 2, there are various films and a deposition force=3- method, but here, a method of depositing a-3i by a plasma CVD method will be explained. The deposition temperature was set between room temperature and approximately 400°C, and the source gas was mainly silane (SiH).
t) or disilane (Sitl (6)) is used.The film thickness is set between 500 and 3000.

Next, an example in which the first semiconductor film 2 is annealed with beam energy 11 will be described. There are many energy sources for annealing, such as lasers, electron beams, lamps, heaters, etc., but here we will describe an annealing method using an Ar laser.

In general, a-3T deposited by plasma CVD contains hydrogen gas, so performing pre-annealing to remove this gas improves the crystallinity after recrystallization annealing, which will be described later. It is known that the pre-annealing method can remove the hydrogen gas in a-5i at a temperature of about 500° C. or higher, and any annealing method that can raise the temperature to above this temperature can be used. For example, it can be carried out in a vacuum or in a nitrogen or inert gas atmosphere by scanning the energy beam 11 of a static laser with an energy density that does not melt the a-3i. In addition, at 550℃ in a nitrogen atmosphere,
One hour is enough. Subsequently, recrystallization annealing is performed. Similar to the pre-annealing described above, a-
Energy beam 11 at an energy density that melts 5t
to be scanned. As a result, the first semiconductor film 2 is crystallized and becomes a recrystallized semiconductor film 21.

In FIG. 1(b), a resistivity of 0.0.
This is a step of depositing the second semiconductor film 3 with a thickness of 1Ω or less, leaving the second semiconductor film 3 in the source and drain regions by etching, and forming the source region 4 and drain w4+A5 by beam annealing. As an example of the second semiconductor film 3, when manufacturing an N-channel TPT, an N-type impurity is added,
When manufacturing a P-channel TPT, P-type impurities are added. Here, N-channel TPT will be explained. Although there are various deposition methods such as CVD and sputtering methods, a method of depositing N1 a-5i using plasma CVD method will be described. The deposition temperature was between room temperature and about 300°C, and 0.1% to 1% of phosphine (PH3) was added to the raw material gas, silane (SiHn). 0 from t+m.
Deposit between 1 μm. In the case of P"a-3i, diborane (B2H6) is added to SiH4 and deposited. Next, using photolithography, only the source and drain portions are left and the rest is etched away. The etching method is as follows: Dry or wet is fine, but tetrafluoromethane (
This can be easily done by plasma etching using a mixed gas of CF4) and oxygen (0□). In this etching, a part of the second semiconductor film 3 and the recrystallized semiconductor film 21 are etched,
The film thickness of the source region 4 and drain region 5 is the same as that of the channel region 6.
The film thickness should be at least twice as thick as the film thickness. Then, the source region 4 and drain region 5 are annealed with beam energy 11 to lower their resistance, form a recrystallized low-resistance semiconductor film 22, and improve contact between the source and drain portions. During this annealing, the temperature distribution of the recrystallized semiconductor film 21 becomes as shown in FIGS. 3(al) and (b).

The thick source region 4 and drain region 5 absorb a large amount of the beam and can be selectively melted.

FIG. 1 (C1 is a step in which the recrystallized low-resistance semiconductor film 22 is etched by photolithography to perform element isolation, and the gate insulating film 7 is deposited. The etching method can be easily performed by the plasma etching described above. The gate insulating film 7 is formed by forming a silicon oxide film (SiOx) or a silicon nitride film (SiNx) by various CVD methods, sputtering methods, etc.
etc. can be deposited. Here, SiO'x is plasma C
A method of depositing by VD method will be explained. The deposition temperature is between room temperature and 300° C., and raw material gases mainly use SiH4 and NtO. The film thickness is deposited between 500 and 3000.

FIG. 1 Tdl is a step of forming a gate electrode 8, a source electrode 9, and a drain electrode 10 after forming contact holes for the source and drain portions by photolithography.

Deposition methods for each electrode include sputtering and vapor deposition.
The ingredients are also Aj! There are metal silicides such as -5i, Mo-5i, and W-3i. - An example is the method of depositing AA-5t between 0.5 μm and 1 μm by magnetron sputtering.

FIG. 4 is a sectional view showing a part of the process of the second embodiment of the present invention, and the process corresponds to FIG. 1 fbl.

By making the thickness of the second semiconductor film 3 that becomes the source and drain the same as or greater than that of the recrystallized semiconductor film 21, the film thickness ratio can be doubled or more without etching the recrystallized semiconductor film 21. . Subsequently, source region 4 and drain region 5 can be selectively melted by annealing using energy beam 11.

〔Effect of the invention〕

As described above, this invention makes the film thickness of the source region and drain region larger than the film thickness of the channel region during TPT fabrication, so that only the drain region and the source region are selectively melted during beam annealing. Improve your contacts.

Therefore, the leakage current and breakdown voltage characteristics of the TPT are improved.

[Brief explanation of the drawing]

1(a) to Td+ are sectional views showing the steps of the first embodiment of the present invention, FIG. 2 ia) to fdl are sectional views explaining the conventional method, and FIG. An explanatory diagram showing the temperature distribution of the recrystallized semiconductor film during annealing, and FIG. 4 are cross-sectional views showing a part of the process of the second embodiment of the present invention. 1... Insulating substrate 2... First Semiconductor film 3...
Second semiconductor film 4... Source region 5... Drain region 6... Channel region 7... Gate insulating film 8.
... Gate electrode 9 ... Source electrode 10 ... Drain electrode 11 ... Beam energy 21 ... Recrystallized semiconductor film 22 ... Recrystallized low resistance semiconductor film or higher

Claims (2)

[Claims] (1) (a) Depositing an amorphous or polycrystalline first semiconductor film on an insulating substrate, and then annealing the first semiconductor film with an energy beam to form a recrystallized semiconductor film; (b) (c) over-etching the recrystallized semiconductor film when depositing and patterning a second semiconductor film having a resistivity of 0.1 Ωcm or less on the recrystallized semiconductor film; (c) etching the source and drain regions with an energy beam; The second semiconductor film is annealed and melted to lower the resistance of the entire source and drain regions to form a recrystallized low resistance semiconductor film, and a gate insulating film is deposited on the entire surface of the recrystallized low resistance semiconductor film. (d) forming contact holes in the source and drain regions by photolithography to fabricate a gate electrode, a source electrode, and a drain electrode. (2) The thickness of the recrystallized low-resistance semiconductor film formed in the source and drain regions is 2 times that of the recrystallized semiconductor film in the channel region.
A method for manufacturing a thin film semiconductor device according to claim 1, which is more than twice as large.