US6815269B2 - Thin-film transistor and method for manufacturing the same - Google Patents
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- US6815269B2 US6815269B2 US10/430,540 US43054003A US6815269B2 US 6815269 B2 US6815269 B2 US 6815269B2 US 43054003 A US43054003 A US 43054003A US 6815269 B2 US6815269 B2 US 6815269B2
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- 239000010409 thin film Substances 0.000 title claims abstract description 184
- 238000000034 method Methods 0.000 title claims description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000010408 film Substances 0.000 claims abstract description 241
- 239000013078 crystal Substances 0.000 claims abstract description 91
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 59
- 238000005224 laser annealing Methods 0.000 claims abstract description 19
- 239000000155 melt Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 48
- 238000002425 crystallisation Methods 0.000 claims description 39
- 238000002844 melting Methods 0.000 claims description 24
- 230000008018 melting Effects 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 15
- 238000005299 abrasion Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 23
- 238000010899 nucleation Methods 0.000 description 12
- 230000006911 nucleation Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000001419 dependent effect Effects 0.000 description 5
- 230000012010 growth Effects 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Definitions
- the present invention relates to a thin-film transistor (TFT) used in an active matrix type display or the like, and to a method for manufacturing a thin-film transistor.
- TFT thin-film transistor
- a general method for forming a polycrystalline silicon film is the excimer laser method of first forming an amorphous silicon film and then irradiating the amorphous silicon film with light from an excimer laser, so as to obtain a polycrystalline silicon film by melting and re-crystallizing the amorphous silicon film.
- a laser light beam with an irradiation aperture being around 300 mm by 0.4 mm is scanned in the short-axis direction with a pitch of several tens of ⁇ m.
- this apparatus because it is possible to form a polycrystalline silicon film in which sub-micron ordered crystal grains are randomly disposed, it is possible to mass produce thin-film transistors with a mobility of approximately 150 cm 2 /Vs with a high yield. In order to achieve higher performance in future TFTs, it is necessary to both increase the size of the crystal grains and control the position of the crystal grains.
- Japanese Patent No. 2689596 for example, there is disclosed a technology for achieving a polycrystalline silicon film with large coarse crystal grains, by using a two-layer amorphous silicon film to increase the grain size in the thin film part.
- the resulting complexity of the annealing apparatus not only results in the apparatus being expensive, but also in a reduction of up-time.
- the present invention adopts the following basic technical constitution.
- a first aspect of the present invention relates to a thin-film transistor which comprising a polycrystalline silicon film layer formed on a substrate, a gate electrode formed on the polycrystalline silicon film layer via a gate insulation layer and source and drain electrodes both being arranged on both sides of the gate electrode and being connected to the polycrystalline silicon film layer, and wherein a part of the polycrystalline silicon film layer comprising a thin-film part and a thick-film part and at least a part of the thin film part being minimally used as a channel part of the transistor, and further wherein the thin-film part comprising large coarse crystal grains.
- a second aspect of the present invention relates to a thin-film transistor which comprising a configuration as mentioned in the above-noted first aspect of the present invention and is further characterized in that the thick-film part comprising crystal grains a size of which is smaller than that of the large coarse crystal grains formed in the thin-film part.
- a third aspect of the present invention relates to a thin-film transistor which comprising a polycrystalline silicon film layer formed on a substrate, a gate electrode formed on the polycrystalline silicon film layer via a gate insulation layer and source and drain electrodes both being arranged on both sides of the gate electrode and being connected to the polycrystalline silicon film layer, and wherein a part of the polycrystalline silicon film layer comprising a thin-film part and a thick-film part and at least a part of the thin film part being minimally used as a channel part of the transistor, and further wherein at least a portion of the thin-film part is in fully melted condition, while at least a portion of the thick-film part is in not fully melted condition.
- a fourth aspect of the present invention relates to a thin-film transistor comprising:
- a polycrystalline silicon film comprising a thin-film part and a thick-film part, the thin-film part being minimally used as a channel part,
- polycrystalline silicon film is formed by laser annealing with an energy density that completely melts the thin-film part but does not completely melt the thick-film part.
- a fifth aspect of the present invention relates to a method for manufacturing a thin-film transistor which comprising a polycrystalline silicon film layer formed on a substrate, a gate electrode formed on the polycrystalline silicon film layer via a gate insulation layer and source and drain electrodes both being arranged on both sides of the gate electrode and being connected to the polycrystalline silicon film layer, the method comprising the steps of;
- a thin-film transistor with the thin-film part as at least a channel part.
- FIG. 1 is a cross-sectional view showing a first embodiment of a TFT according to the present invention, with FIG. 1 (A) to FIG. 1 (D) showing the progression of the manufacturing process.
- FIG. 2A is a plan view corresponding to FIG. 1D
- FIG. 2B is a cross-sectional view showing the next manufacturing process.
- FIG. 3A is a cross-sectional view showing a first comparison example
- FIG. 3B is a plan view showing a second comparison example.
- FIG. 4A is a cross-sectional view showing a second embodiment of a TFT according to the present invention
- FIG. 4B is a cross-sectional view showing a third embodiment of a TFT according to the present invention.
- FIG. 2 (B) one specific embodiment of a TFT of the present invention is shown in FIG. 2 (B).
- FIG. 2 (B) it is shown that a thin-film transistor 42 which comprising a polycrystalline silicon film layer 24 formed on a substrate 10 via an insulation film 21 , a gate electrode 36 formed on the polycrystalline silicon film layer 24 via a gate insulation layer 34 and source and drain electrodes 71 , 72 both being arranged on both sides of the gate electrode 36 and being connected to the polycrystalline silicon film layer 24 , and wherein a part of the polycrystalline silicon film layer 24 comprising a thin-film part 16 and a thick-film part 18 and at least a part of the thin film part 16 being minimally used as a channel part 37 of the transistor 42 , and further wherein the thin-film part 16 comprising large coarse crystal grains 26 as shown in FIG. 2 (A).
- FIG. 2 (B) further shows that the thick-film part 18 of the TFT 42 of the present invention comprises crystal grains 27 a size of which is smaller than that of the large coarse crystal grains 26 formed in the thin-film part 16 .
- the thin-film part 16 is in fully melted condition, while at least a portion of the thick-film part 18 is in not fully melted condition.
- the polycrystalline silicon film 24 is first formed to have the thin-film part 16 and a thick-film part 18 , and further the polycrystalline silicon film 24 is treated by laser annealing with an energy density that completely melts the thin-film part 16 but does not completely melt the thick-film part 18 .
- the energy density completely melting the thin-film part is an energy density at least as great as a micro-crystallization threshold value of the thin-film part 16
- the energy density not completely melting the thick-film part 18 is an energy density less than a micro-crystallization threshold value of the thick-film part 18 .
- the above-noted phrase “energy density that completes melts” used herein means an energy density that is at least as great as the micro-crystallization threshold value.
- the crystal grain diameter in the polycrystalline silicon film formed by laser annealing of the amorphous silicon film is dependent upon the laser energy.
- the diameter thereof becomes a very small value of 20 nm or smaller (with the exception that for some film thicknesses, rather than crystallizing after melting with irradiating laser light, become amorphous).
- the energy density at this point is known as the micro-crystallization threshold value.
- micro-crystallization will occur when the melting condition of an amorphous silicon film changes from incomplete melt to complete melt, and thereby the nucleation mechanism at the time of re-crystallization would change from heterogeneous nucleation with using a boundary surface formed between the substrate and the amorphous silicon film as a nucleation site, to homogeneous nucleation not having special nucleation sites.
- This change in the nucleation mechanism shows dependence on the temperature reached at the boundary between the substrate and the amorphous silicon film, the temperature distribution in the film thickness direction, and the film cooling rate and the like.
- the micro-crystallization threshold value therefore, changes and is dependent upon such parameters as the film thickness of the amorphous silicon film, the structure of the amorphous silicon film, the optical constants of the amorphous silicon film, and the pulse laser light wavelength and pulse width.
- the micro-crystallization threshold value of a polycrystalline silicon film that has once been laser-annealed is approximately 14% greater than that of the amorphous silicon film before laser annealing. When the energy density is further increased, film peeling occurs because of abrasion.
- the temperature in the thick-film part 18 is below the temperature of the micro-crystallization threshold value.
- the boundary between the substrate and the amorphous silicon film is the major location of the nucleation sites, and there is crystal growth from the boundary between the substrate and the amorphous silicon film progressing toward the amorphous silicon film surface.
- the thin-film transistor (TFT) of the present invention is further characterized in that the large coarse crystal grains 26 formed in the thin-film part 16 are grown along a direction parallel to a surface of the channel part 37 thereof, while the crystal grains 27 formed in the thick-film part 18 are grown along a direction from a surface of the substrate 10 to a surface of the polycrystalline silicon film layer 24 .
- the energy density is excessively high, so that not only the thin-film part but also the thick-film part is completely melted, the micro-crystallized construction is formed in both the thin-film part and the thick-film part.
- non-uniform crystal grains smaller than 1 ⁇ m are formed randomly both in the thin-film part 16 and the in the thick-film part 18 .
- the irradiation energy density is set so that it is at least the micro-crystallization threshold value of the thin-film part 16 and also does not reach the abrasion threshold value thereof, and further so that it is at least a value at which the entire amorphous silicon film in the thick-film part 18 is made polycrystalline in the film thickness direction but does not reach the micro-crystallization threshold value thereof.
- the energy density at which there is complete melt of the thin-film part 16 is an energy density at least as great as the micro-crystallization threshold value of the thin-film part 16
- the energy density at which there is not complete melt of the thick-film part 18 is an energy density that is less than the micro-crystallization threshold value of the thick-film part.
- the energy density at which the thin-film part 16 is completely melted is an energy density at least as great as the thin-film part micro-crystallization threshold value but less than the abrasion threshold value thereof
- the energy density at which there is not complete melt of the thick-film part 18 is an energy density that is at least as great as the poly-crystallization threshold value of the thick-film part and not as great as the micro-crystallization threshold value thereof.
- the source electrode 71 is formed on one of the thick-film parts 18 - 1 , while the drain electrode 72 being formed on another thick-film part 18 - 2 .
- an LDD region 38 and a part of a source-drain region 40 are formed in a part of the channel part 37 of the thin-film part 16 .
- a lightly doped drain (LDD) region 38 and part of a source-drain region 40 are formed in the thin-film part 16 .
- the LDD region 38 and part of the source-drain region 39 are also formed in a thin-film part having large coarse crystal grains, it is possible to achieve low leakage current in the LDD region 38 and low resistance in the source-drain region 40 .
- At least two rows 26 , 26 ′ of the crystal grains can be formed in the channel length direction of the thin-film part 16 , as shown in FIG. 2 (A).
- the two rows 26 , 26 ′ of crystal grains are formed in a channel length direction and in the thin-film part 42 .
- the two rows 26 and 26 ′ of crystal grains grow in the channel width direction in the thin-film part 16 .
- a channel part 16 of the TFT may be formed in only one row 26 ′ selected from the two rows 26 and 26 ′ of crystal grains.
- a length of the channel length direction of the thin-film part can be set at around 8 ⁇ m or less, in which case it is relatively easy to form large coarse crystal grains with a diameter up to 4 ⁇ m. If a length of the thin-film part in a channel length direction is made 8 ⁇ m or smaller, it is easy to form two rows of crystal grains in the channel width direction of the thin-film part as shown in FIG. 2 (A) and FIG. 2 (B).
- a micro-crystallization configuration 32 can also be formed between the two rows 26 and 26 ′ of the crystal grains of the thin-film part 16 serving as a channel part 37 along a border line 28 formed between the two rows of the crystal grains 26 and 26 ′, as shown in FIG. 3 (B).
- a method for manufacturing a TFT according to the present invention is a method for manufacturing a TFT as mentioned above.
- the amorphous silicon thin film has two types of film thicknesses, the irradiation intensity of the excimer laser light is an intensity that completely melts the thin-film part of the amorphous silicon thin film, and also that does not completely melt the thick-film part of the amorphous silicon thin film.
- This method provides a TFT having a channel region and an LDD region in the thin-film part.
- an SiO 2 film 12 that is an insulation film and forms an underlayer is formed followed by an amorphous silicon film 14 onto a glass substrate 10 (FIG. 1 (A)).
- the film thickness of both films is 100 nm.
- the glass substrate 10 and the like are dehydrogenated at 500° C. for 5 minutes, and conventional photolithography and dry etching are used to form a thin-film part 16 and a thick-film part 18 on the amorphous silicon film 14 (FIG. 1 (B)).
- the thin-film part 16 has a film thickness of 40 nm and a region width of 3 ⁇ m.
- the film thickness of the thick-film part 18 remains 100 nm.
- the surface of the amorphous silicon film 14 is irradiated with excimer laser light 15 (FIG. 1 (C)).
- the annealing apparatus used is a conventional mass-produced apparatus having 200 mm ⁇ 0.4 mm optics.
- the annealing conditions thereof are set so that the energy density is 430 mJ/cm 2 , which completely melts the thin-film part 16 , and the scanning pitch is made 40 ⁇ m.
- the phrase “energy density that completely melts” in this case means an energy density that is at least as great as the micro-crystallization threshold value.
- the crystal grain diameters in the polycrystalline silicon film 24 that is formed are dependent upon the laser energy density.
- the grain diameter increases.
- the diameter becomes a very small value of 20 nm or smaller (although for some film thicknesses, rather than crystallizing after melting with laser light, the film becomes amorphous).
- the energy density at this point is known as the micro-crystallization threshold value.
- micro-crystallization threshold value of an amorphous silicon film having a film thickness of 40 nm was 410 mJ/cm 2 .
- the substrate/silicon boundary 19 is the main nucleation site 20 , and crystal growth occurs from the substrate/silicon boundary 19 toward a surface of the amorphous silicon film 14 .
- crystal grains formed in the thick-film part 18 are serving as seed crystals 22 , so that large coarse crystal grains 26 growing in the lateral direction (film surface direction) are obtained.
- the large coarse crystal grains 26 therefore, can be said to be position-controlled in one dimension.
- the crystal grain boundary 28 is formed so as divided the thin-film part 16 in two portions.
- micro-crystallized constructions are formed in both the thin-film part 16 and the thick-film part 18 .
- the seed crystals are formed more on the thin-film part 16 side than at the boundary between the thin-film part 16 and the thick-film part 18 , the grain diameter of each one of the large coarse crystal grains 26 is reduced.
- the irradiation energy density is set so that it is at least the micro-crystallization threshold value of the thin-film part 16 and also does not reach the abrasion threshold value, and further so that it is at least a value at which the entire amorphous silicon film in the thick-film part 18 is made polycrystalline in the film thickness direction but does not reach the micro-crystallization threshold value.
- an irradiation energy density of 410 to 570 mJ/cm 2 results in a necessary irradiation control condition to obtain a polycrystalline silicon film 24 having uniform and position-controlled large coarse crystal grains 26 .
- the grain diameter of the large coarse crystal grains 26 are dependent upon the irradiation energy density and on the difference in film thicknesses between the thin-film part 16 and the thick-film part 18 , because they are mainly dependent upon the substrate temperature and the like, with the substrate at room temperature, the approximate limit is 2 ⁇ m.
- the approximate limit is 2 ⁇ m.
- a gate insulation film 34 , a gate electrode 36 , an LDD region 38 on both sides of the gate electrode 36 , and a source-drain region 40 are formed, as shown in FIG. 2 (B).
- a width of the gate electrode is 1.5 ⁇ m and the LDD length is 0.5 ⁇ m.
- an interlayer insulation film 34 and a source-drain electrode interconnect 71 , 72 are formed, thereby completing the TFT 42 .
- the TFT 42 is formed by a polycrystalline silicon film 24 having a thin-film part 16 and a thick-film part 18 , wherein the thin-film part 16 is used minimally as the channel part 37 .
- the polycrystalline silicon film is formed by laser annealing of an energy density whereby the thin-film part 16 is completely melted, but whereby the thick-film part 18 is not completely melted.
- a TFT 42 fabricated as described above has a crystal grain boundary 28 that is substantially perpendicular to the channel length direction which significantly prevents carrier movement, and this being controlled as a single plane, the mobility is high, and there is little variation between elements.
- the leakage current is also an extremely small value, on the order of an TFT on a single crystal silicon substrate.
- the thick-film part 18 is included within the source-drain region 40 .
- the leakage current is large, because the channel/source-drain terminals are formed in one and the same crystal grains in the channel length direction, the value of the leakage current is small compared with a conventional self-aligned polycrystalline silicon TFT.
- FIG. 4 (A) is a cross-sectional view showing a TFT according to a different embodiment of the present invention, which is described below.
- elements that are the same as shown in FIG. 2 (B) are assigned the same reference numerals and are not described herein.
- laser annealing is done at 400° C., and a polycrystalline silicon film 24 is formed having large coarse crystal grains in two rows of 3 ⁇ m.
- a gate insulation film 34 is formed using the polycrystalline silicon film 24 , a gate insulation film 34 , a gate electrode 48 , an LDD region 50 on both sides of the gate electrode 48 , and a source-drain region 52 are formed.
- a TFT 54 is fabricated with a channel length of 0.8 ⁇ m and an LDD region having an LDD length of 0.5 ⁇ m is formed on both sides.
- the channel part 49 by being formed within one of the large coarse crystal grains 26 , does not include the crystal grain boundary 28 that divides the thin-film part 16 in two portions.
- the crystal grain boundary 28 be in the source-drain region 52 , by the gate length, the LDD length, or photolithography precision in alingment, it is possible to have it included within either one of the LDD regions formed in the source side or the drain side.
- the crystal grain boundary 28 be in the LDD region 50 on the source side.
- FIG. 4 (B) is a cross-sectional view showing a separate embodiment of the TFT according to a the present invention, which is described below.
- a polycrystalline silicon film 24 is formed and which having large coarse crystal grains 26 arranged in two rows of 1.5 ⁇ m width.
- a gate insulation film 34 Using the polycrystalline silicon film 24 , a gate insulation film 34 , a gate electrode 56 , a LDD region 58 on one side of the gate electrode 56 , and a source-drain region 60 are formed.
- a TFT 62 having a channel length of 0.8 ⁇ m and a one-side LDD structure with an LDD length of 0.2 ⁇ m is fabricated.
- the channel part 57 in this case is formed within the large coarse crystal grains 26 on one side.
- the crystal grain boundary 28 that divides the thin-film part 16 in two parts does not exist in the channel part 57 and the LDD region 58 .
- a thin-film transistor with the thin-film part as at least a channel part.
- the process of forming a thin-film part and a thick-film part of an amorphous silicon film on a substrate comprises the steps of;
- the process of forming a thin-film part and a thick-film part of an amorphous silicon film on a substrate comprises the steps of;
- the energy density completely melting the thin-film part is an energy density at least as great as a micro-crystallization threshold value of the thin-film part, and wherein the energy density not completely melting the thick-film part is an energy density less than a micro-crystallization threshold value of the thick-film part.
- the energy density completely melting the thin-film part is an energy density at least as great as a micro-crystallization threshold value and less than an abrasion threshold value of the thin-film part and wherein the energy density not completely melting the thick-film part is an energy density at least as great as the poly-crystallization threshold value and less than the micro-crystallization threshold value of the thick-film part.
- the present invention is not restricted by the above-described embodiments, which are provided as examples.
- a channel part is formed with large coarse crystal grains grown from the boundary between the thin-film part and the thick-film part, so that it is possible by using a conventional laser annealing apparatus to easily achieve such performance as high carrier mobility and low leakage current.
- both of the LDD region and part of the source-drain region are formed to have the large coarse crystal grains, resulting in reduced leakage current in the LDD region and a low resistance in the source-drain region.
- the crystal grain boundary intersecting the channel length direction in the thin-film part is substantially one plane, resulting in an improvement in carrier mobility.
- the channel part is formed by only one of the two rows of crystal grains, the crystal grain boundary intersecting the channel length direction is substantially non-existent, thereby improving the carrier mobility.
- the channel length direction of the thin-film part By making the channel length direction of the thin-film part be 8 ⁇ m or smaller, it is relatively easy to form large coarse crystal grains of up to 4 ⁇ m, thereby facilitating the formation of two rows of crystal grains in the channel width direction in the thin-film part.
Abstract
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JP2002132310A JP4190798B2 (en) | 2002-05-08 | 2002-05-08 | Thin film transistor and manufacturing method thereof |
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US10/430,540 Expired - Lifetime US6815269B2 (en) | 2002-05-08 | 2003-05-06 | Thin-film transistor and method for manufacturing the same |
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US (1) | US6815269B2 (en) |
JP (1) | JP4190798B2 (en) |
KR (1) | KR100510934B1 (en) |
CN (1) | CN1319178C (en) |
TW (1) | TW595003B (en) |
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US20050104125A1 (en) * | 2000-09-05 | 2005-05-19 | Sony Corporation | Semiconductor thin film and method of fabricating semiconductor thin film, apparatus for fabricating single crystal semiconductor thin film, and method of fabricating single crystal thin film, single crystal thin film substrate, and semiconductor device |
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US8314428B2 (en) * | 2002-12-16 | 2012-11-20 | Samsung Display Co., Ltd. | Thin film transistor with LDD/offset structure |
US20050019995A1 (en) * | 2003-07-24 | 2005-01-27 | Mao-Yi Chang | [method of fabricating polysilicon film] |
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US20050019994A1 (en) * | 2003-07-24 | 2005-01-27 | Mao-Yi Chang | [method of fabricating polysilicon film] |
US7611577B2 (en) | 2004-03-31 | 2009-11-03 | Nec Corporation | Semiconductor thin film manufacturing method and device, beam-shaping mask, and thin film transistor |
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US20060194354A1 (en) * | 2005-02-28 | 2006-08-31 | Nec Lcd Technologies, Ltd. | Laser irradiation method and apparatus for forming a polycrystalline silicon film |
US20090086327A1 (en) * | 2005-02-28 | 2009-04-02 | Hiroshi Okumura | Laser irradiation method and apparatus for forming a polycrystalline silicon film |
US7473657B2 (en) | 2005-02-28 | 2009-01-06 | Nec Lcd Technologies, Ltd. | Laser irradiation method and apparatus for forming a polycrystalline silicon film |
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US20080128704A1 (en) * | 2006-11-30 | 2008-06-05 | Yoshihiro Morimoto | Image display system and manufacturing method of multi-gate thin film transistor |
US20100258808A1 (en) * | 2009-04-09 | 2010-10-14 | Chunghwa Picture Tubes, Ltd. | Thin film transistor and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN1457103A (en) | 2003-11-19 |
CN1319178C (en) | 2007-05-30 |
JP2003332346A (en) | 2003-11-21 |
US20030211666A1 (en) | 2003-11-13 |
TW595003B (en) | 2004-06-21 |
TW200306669A (en) | 2003-11-16 |
KR20030087560A (en) | 2003-11-14 |
JP4190798B2 (en) | 2008-12-03 |
KR100510934B1 (en) | 2005-08-30 |
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