JPH03154383A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03154383A JPH03154383A JP29343389A JP29343389A JPH03154383A JP H03154383 A JPH03154383 A JP H03154383A JP 29343389 A JP29343389 A JP 29343389A JP 29343389 A JP29343389 A JP 29343389A JP H03154383 A JPH03154383 A JP H03154383A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- recrystallized silicon
- type
- source
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 239000000758 substrate Substances 0.000 claims abstract description 93
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 85
- 239000010703 silicon Substances 0.000 claims abstract description 85
- 230000005669 field effect Effects 0.000 claims abstract description 20
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 4
- 108091006146 Channels Proteins 0.000 abstract description 28
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 238000001953 recrystallisation Methods 0.000 description 10
- 239000002253 acid Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- DJHGAFSJWGLOIV-UHFFFAOYSA-N Arsenic acid Chemical compound O[As](O)(O)=O DJHGAFSJWGLOIV-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229940000488 arsenic acid Drugs 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000035558 fertility Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 235000020131 mattha Nutrition 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
「慨 要］
半導体基板上に絶縁膜を介して形成された凹凸を持った
再結晶シリコン基板において、薄い再結晶シリコン基板
部にチャネル領域が形成され、前記薄い再結晶シリコン
基板部上にゲート絶縁膜を介してゲート電極が形成され
、厚い再結晶シリコン基板部にソースドレイン領域が形
成された構造からなるλ’ＩＩＳ電界効果トランジスタ
が形成されているため、チャネル領域を薄い再結晶シリ
コン基板部に形成できることにより、再結晶シリコン基
板を完全に再結晶ｆヒできるため、素子特性の安定ｆヒ
による高性能化及びチャネル電界を小さくできるなめ、
モビリティを大きくすることができることによる高速ｆ
ヒを、ソースドレイン領域を厚い再結晶シリコン基板部
に形成できることによつ。[Detailed Description of the Invention] "Summary" In a recrystallized silicon substrate with irregularities formed on a semiconductor substrate via an insulating film, a channel region is formed in a thin recrystallized silicon substrate portion, and the thin recrystallized Since a λ'IIS field effect transistor is formed with a structure in which a gate electrode is formed on a silicon substrate portion via a gate insulating film and a source/drain region is formed on a thick recrystallized silicon substrate portion, the channel region is Since it can be formed on a thin recrystallized silicon substrate, the recrystallized silicon substrate can be completely recrystallized, resulting in improved performance due to stable device characteristics and a smaller channel electric field.
High speed f due to the ability to increase mobility
This is because the source and drain regions can be formed in a thick recrystallized silicon substrate.
抵抗及び接合容量を低減できることによる高速１ヒを、
凹凸を持った再結晶シリコン基板を使用できるため、熱
容量を大きくできることにより、レーザー再結晶ｆヒに
よる基板ハガレを改善できることによる高信頼性を、又
、一部の変形により各領域をセルファライン形成できる
ことによる高集積１ヒを、メタルを含むソースドレイン
領域を形成できることによるいっそうの高速１ヒも可能
にした半導体装置。High-speed 1-fire by reducing resistance and junction capacitance,
Since a recrystallized silicon substrate with unevenness can be used, the heat capacity can be increased, and substrate peeling due to laser recrystallization can be improved, resulting in high reliability. Also, each area can be formed as a self-line by partially deforming it. A semiconductor device that enables high-integration 1-chip processing due to the high-density semiconductor device, and even higher-speed 1-chip processing by forming a source/drain region containing metal.
［産業上の利用分野］
本発明はＭＩＳ型半導体装置に係り、特に、モビリティ
を大きくし高速ｆヒを計った５ＯＩ（Ｓｉ１ｉｃｏｎ
Ｏｎ、Ｉｎ５ｕｌａｔｏｒ）型のＭＩＳ電界効果トラ
ンジスタに関する。[Industrial Application Field] The present invention relates to MIS type semiconductor devices, and in particular to 5OI (Si1icon
The present invention relates to a MIS field effect transistor (On, In5lator) type.
従来、Ｓｏｌ型のＭＩＳ電界効果トランジスタに関して
は、半導体基板上に絶縁膜を介して形成された概略同じ
膜厚を持った厚い再結晶シリコン基板において、ゲート
絶縁膜を介して形成されたゲート電極にセルファライン
にチャネル領域及びソースドレイン領域が形成された構
造からなるＭＩＳ電界効果トランジスタを使用していた
。通常シリコン基板に形成するＭ Ｉ Ｓ電界効果トラ
ンジスタより、周囲を絶縁膜で分離されているＳＯＩ型
のＭＩＳ電界効果■・ランジスタの場合はソースドレイ
ン領域の接合容量を低；戊することはできるが、厚い再
結晶シリコン基板の完全な再結晶ｆヒが難しく、チャネ
ル領域のモビリティを大きくすることができず、いまひ
とつ高速化が達成できないという問題が顕著になってき
ている。そこで、チャネル領域のモビリティを大きくす
ることができるＳＯＩ型のＭＩＳ電界効果１〜ランジス
タを形成できる手段が要望されている。Conventionally, for Sol-type MIS field effect transistors, a gate electrode formed via a gate insulating film is formed on a thick recrystallized silicon substrate with approximately the same film thickness formed on a semiconductor substrate with an insulating film interposed therebetween. A MIS field effect transistor having a structure in which a channel region and a source/drain region are formed in a self-aligned line was used. Compared to MIS field effect transistors, which are usually formed on silicon substrates, SOI type MIS field effect transistors, whose surroundings are separated by an insulating film, have lower junction capacitance in the source and drain regions; It is becoming increasingly difficult to completely recrystallize a thick recrystallized silicon substrate, making it impossible to increase the mobility of the channel region, making it impossible to achieve even higher speeds. Therefore, there is a need for a means for forming an SOI type MIS field effect transistor that can increase the mobility of the channel region.
［従来の技術］
第５図は従来の半導体装置の模式側断面図である。５１
はｐ−型シリコン（Ｓｉ）基板、５２は絶縁膜（酸化膜
）、５３は再結晶シリコン基板、５４はｐ型チャネル領
域、５５はｎ十型ソースドレイン領域、５Ｇはゲート酸
ｆヒ膜、５７はゲート電極、５８はブロック用酸化膜、
５９は燐珪酸ガラス（ＰＳＧ） ＠、６０はＡ１配線を
示している。[Prior Art] FIG. 5 is a schematic side sectional view of a conventional semiconductor device. 51
is a p-type silicon (Si) substrate, 52 is an insulating film (oxide film), 53 is a recrystallized silicon substrate, 54 is a p-type channel region, 55 is an n+ type source drain region, 5G is a gate oxide film, 57 is a gate electrode, 58 is a block oxide film,
59 indicates phosphosilicate glass (PSG)@, and 60 indicates A1 wiring.
同図においては、ｐ−型シリコン（Ｓｉ）基板５１上に
絶縁膜（酸化膜）５２を介して概略同じ膜厚を持った厚
い再結晶シリコン基板５３が形成されており、前記再結
晶シリコン基板５３上にゲート酸ｆヒ膜５Ｇを介して形
成されたゲート電極５７にセルファラインにｐ型チャネ
ル領域５４及びｎ十型ソースドレイン領域５５が形成さ
れた構造からなるＳＯＩ型のＭＩＳ電界効果トランジス
タが形成されている。周囲を絶縁膜で分離されているソ
ースドレイン領域が形成されているため、通常シリコン
基板に形成されるＭＩＳ電界効果トランジスタに比較し
、接合容量を低減することはできるが、レーザー再結晶
化による再結晶シリコン基板のハガレを防ぐため厚い多
結晶シリコン基板を使用するので、厚い多結晶シリコン
基板の完全な再結晶化が難しく、チャネル領域のモビリ
ティを大きくすることができず、いまひとつ高速化が達
成できない欠点がある。In the figure, a thick recrystallized silicon substrate 53 having approximately the same thickness is formed on a p-type silicon (Si) substrate 51 with an insulating film (oxide film) 52 interposed therebetween. An SOI type MIS field effect transistor has a structure in which a p-type channel region 54 and an n+-type source/drain region 55 are formed on a self-aligned gate electrode 57 formed on the gate electrode 53 via a gate acid film 5G. It is formed. Since the source and drain regions are separated by an insulating film, the junction capacitance can be reduced compared to MIS field effect transistors that are normally formed on silicon substrates, but it is difficult to re-crystallize by laser recrystallization. Since a thick polycrystalline silicon substrate is used to prevent the crystalline silicon substrate from peeling off, it is difficult to completely recrystallize the thick polycrystalline silicon substrate, making it impossible to increase the mobility of the channel region, making it impossible to achieve high speed. There are drawbacks.
［発明が解決しようとする問題点１
本発明か解決しようとする問題点は、従来例に示される
ように、使用する厚い多結晶シリコン基板の完全な再結
晶化が難しく、チャネル領域のモビリティを大きくでき
ないため、Ｓ○■型のＭ ＩＳ電界効効果・ランジスタ
のさらなる高速化ができなかったことである９
［問題点を解決するための手段］
上記問題点は半導体基板上に絶縁膜を介して形成された
再結晶シリコン基板にＭＩＳ電界効果トランジスタを形
成した半導体装置であって、チャネル領域形成部をソー
スドレイン領域形成部より１く形成した凹凸型再結晶シ
リコン基板にＭＩＳ電界効果トランジスタを形成した本
発明の半導体装置によって解決される。[Problem to be Solved by the Invention 1] The problem to be solved by the present invention is that, as shown in the conventional example, it is difficult to completely recrystallize the thick polycrystalline silicon substrate used, and the mobility of the channel region is Because it cannot be made larger, it has not been possible to further increase the speed of the S○■ type MIS field effect transistor9. This is a semiconductor device in which a MIS field effect transistor is formed on a recrystallized silicon substrate formed by a process, and the MIS field effect transistor is formed on a concave-convex recrystallized silicon substrate in which a channel region forming part is formed to be larger than a source/drain region forming part. This problem is solved by the semiconductor device of the present invention.
［ｆヤ 用］
即ち本発明の半導体装置においては、半導体基板上に絶
縁膜を介して形成された凹凸を持った再結晶ンリコン基
板において、薄い再結晶シリコン基板部にチャネル領域
が形成され、前記薄い再結晶シリコン基板部上にゲーＩ
−絶縁膜を介してゲーＩ〜電極が形成され、厚い再結晶
シリコン基板部にソースドレイン領域がｒＦ３成された
Ｉｆ’！造からなるＭＩＳ電界効果トランジスタか形成
されている。しながって、チャネル領域を薄い再結晶シ
リコン基板部に形成できることにより、レーザー再結晶
化により完全に再結晶化されたチャネル領域を形成でき
るなめ、素子特性の安定ｆヒによる高性能化及びゲート
電圧印加により、チャネル領域か完全に空乏化され、チ
ャネル領域電界を小さくできるため、モビリティを大き
くすることができることによる高速化を、ソースドレイ
ン領域を厚い再結晶シリコン基板部に形成できることに
より、ソースドレイン抵抗及び接合容量を低減できるこ
とによる高速ｆヒを、凹凸を持った再結晶シリコン基板
を使用できるため、熱容量を大きくできることにより、
レーザー再結晶化による再結晶シリコン基板のハガレを
改善できることによる高信頼性を、又、一部の変形によ
り、各領域をセルファライン形成できることによる高集
積１ヒを、メタルを含むソースドレイン領域を形成でき
ることによるいっそうの高速１ヒも可能にすることもで
きる。 ！！ｏち、高１謔傾、高性能、高速且つ高集積
な半導体集積回路の形成を可能とした半導体装置を得る
ことかできる。[For fya] That is, in the semiconductor device of the present invention, in a recrystallized silicon substrate having irregularities formed on a semiconductor substrate via an insulating film, a channel region is formed in a thin recrystallized silicon substrate portion, and GaI on a thin recrystallized silicon substrate
-If'! where a gate electrode is formed through an insulating film, and a source/drain region is formed with rF3 on a thick recrystallized silicon substrate portion! A MIS field effect transistor is formed from the structure. Therefore, since the channel region can be formed in a thin recrystallized silicon substrate, a completely recrystallized channel region can be formed by laser recrystallization, resulting in improved performance and stable device characteristics. By applying a gate voltage, the channel region is completely depleted and the electric field in the channel region can be reduced. This increases the mobility, which increases the speed of the source and drain regions. High-speed f-hi is achieved by reducing drain resistance and junction capacitance, and by increasing heat capacity by using a recrystallized silicon substrate with irregularities.
High reliability is achieved by improving peeling of the recrystallized silicon substrate by laser recrystallization, high integration is achieved by forming self-alignment lines in each region through partial deformation, and the formation of source/drain regions containing metal. It is also possible to perform even higher speed hits. ! ! In addition, it is possible to obtain a semiconductor device that enables the formation of a high-performance, high-speed, and highly integrated semiconductor integrated circuit.
「実力＠１列］
以下本発明を、図示実施例により具体的に説明する。第
１図は本発明の半導体装置におけろ第１の実施例の模式
側断面図、第２図は本発明の半導体装置における第２の
実施例の模式１１！す断面図、第３図は本発明の半導体
装置における第３の実施例の模式側断面図、第４図（ａ
）〜（ｅ）は本発明の製造方法の一実施例の工程断面図
である。"Ability @ 1 row" The present invention will be specifically explained below with reference to illustrated embodiments. Fig. 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention, and Fig. 2 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention. FIG. 3 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention, and FIG.
) to (e) are process cross-sectional views of one embodiment of the manufacturing method of the present invention.
全図を通し同一対象物は同一符号で示す９第１図はｐ型
シリコン基板を用いた際の本発明の半導体装置における
第１の実施例の模式側断面図で、１は１０ Ｃｎｌ
程度のｐ−型シリコン（Ｓｉ）基板、２は６００ｎｍ
程度の第１の酸化膜、３は４５０ｎｍ程度の第２の酸１
ヒ膜、４は凹凸型再結晶シリコン基板、５は厚さ５０１
１ｍ程度、濃度１０ （：ｍ 程度のｐ型チャネル
領域、６は厚さ５００ｎｍ程度、濃度１０２０ｃｍ−３
程度のｎ十型ソースドレイン領域、７は２０＋）ｍ程度
のゲーＩ−酸ｆヒ膜、８は３００ｎｍ程度のゲーＩ・電
極、９は５０１１ｍ程度のブロック用酸ｆヒ膜、１０は
ＧＯＯ同図においては、ｐ−型シリコン（Ｓｉ）基板１
に第１の酸化膜２及び第２の酸ｆヒ膜３を介して凹凸型
再結晶シリコン基板４が形成されており、前記再結晶シ
リコン基板４上にゲート酸ｆヒ膜７を介して形成された
グー１〜電極８にセルファラインにｐ型チャネル領域５
及びｎ十型ソースドレイン領域６が形成され、且つチャ
ネル領域５は薄い再結晶シリコン基板部に及びｎ＋型ソ
ースドレイン領域６は概略厚い再結晶シリコン基板部に
形成される（Ｍ密には位置合せずれを考慮し、Ｊい再結
晶シリコン基板部にも少し延在している）構造からなる
８０丁型のＭＩＳ電界効果トランジスタが形成されてい
る。しながって、チャネル領域を薄い再結晶シリコン基
板部に形成できることにより、し−ザー再結晶ｆヒによ
り完全に再結晶１にされたチャネル領域を形成できるた
め、素子特性の安定１ヒによる高性ロヒ化及びゲー１へ
電圧印加により、チャネル領域が完全に空乏（ヒされ、
チャネル領域電界を小さくできるなめ、モビリティを大
きくすることができることによる高速化を、ソースドレ
イン領域を厚い再結晶シリコン基板部に形成できること
により、ソースドレイン抵抗及び接合容量を低減できる
ことによる高速１ヒを、凹凸を持った再結晶シリコン基
板を使用できろため、熱容量を大きくできることにより
、レーザー再結晶Ｃヒによる再結晶シリコン基板のハガ
レを改善できることによる高信頼性を可能にすることも
できる。The same objects are designated by the same reference numerals throughout the drawings.9 Figure 1 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention using a p-type silicon substrate, where 1 is 10 Cnl.
p-type silicon (Si) substrate, 2 is 600 nm
The first oxide film has a thickness of about 450 nm, and the second oxide film has a thickness of about 450 nm.
4 is an uneven recrystallized silicon substrate, 5 is a thickness of 501
p-type channel region with a thickness of about 1 m and a concentration of 10 (:m), 6 has a thickness of about 500 nm, and a concentration of 1020 cm
7 is about 20+)m of GaI-acid f-arsenic film, 8 is about 300 nm of Ga-I electrode, 9 is about 5011 m of block acid f-arsenic film, 10 is the same as GOO. In the figure, a p-type silicon (Si) substrate 1
An uneven recrystallized silicon substrate 4 is formed on the recrystallized silicon substrate 4 via a first oxide film 2 and a second oxide film 3, and a gate oxide film 7 is formed on the recrystallized silicon substrate 4. A p-type channel region 5 is added to the self-aligned goo 1 to electrode 8.
and an n+ type source/drain region 6 are formed, and the channel region 5 is formed in a thin recrystallized silicon substrate portion, and the n+ type source/drain region 6 is formed in a roughly thick recrystallized silicon substrate portion (in the M-density, alignment In consideration of the misalignment, an 80-type MIS field effect transistor is formed, which has a structure that extends slightly to the recrystallized silicon substrate. Therefore, since the channel region can be formed in a thin recrystallized silicon substrate, it is possible to form a channel region that is completely recrystallized by the laser recrystallization process, thereby stabilizing the device characteristics. The channel region is completely depleted (depleted) and
High speeds can be achieved by reducing the electric field in the channel region and increasing mobility; high speeds can be achieved by reducing source-drain resistance and junction capacitance by forming the source-drain region in a thick recrystallized silicon substrate; Since a recrystallized silicon substrate with irregularities can be used, the heat capacity can be increased, and peeling of the recrystallized silicon substrate due to laser recrystallization can be improved, thereby achieving high reliability.
第２図は本発明の半導体装置における第２の実施例の模
式側断面図で、１〜１１は第１図と同じ物を示している
。FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and numerals 1 to 11 indicate the same elements as in FIG. 1.
同図においては、薄い再結晶シリコン基板部上にゲート
酸ｆヒ膜７を介してセルファラインにゲート電極８が埋
め込み形成され、且つゲーＩ・電髄８にセルファライン
に薄い再結晶シリコン基板部にはｐ型チャネル領域５が
及び厚い再結晶シリコン基板部にはｎ生型ソースドレイ
ン領域６が形成されている点を除き、第１の実施例と同
じ構造に形成されている。本実施例においては、第１の
実施例の効果に加え、各領域をセルファラインに形成で
きるため高集積化が期待できる。In the figure, a gate electrode 8 is formed embedded in the self-alignment line through a gate oxide film 7 on a thin recrystallized silicon substrate section, and a thin recrystallized silicon substrate section is formed on the self-alignment line in the gate electrode 8. The second embodiment has the same structure as the first embodiment except that a p-type channel region 5 is formed in the thick recrystallized silicon substrate and an n-type source/drain region 6 is formed in the thick recrystallized silicon substrate. In this embodiment, in addition to the effects of the first embodiment, each region can be formed into a self-line, so high integration can be expected.
第３図は本発明の半導体装置における第３の実施例の模
式側断面図で、１〜１７は第１図と同し物を、１２は埋
め込み導電膜を示している。FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention, in which 1 to 17 are the same as in FIG. 1, and 12 is a buried conductive film.
同図においては、厚い埋め込み導電膜１２を含んで形成
された凹凸を持った再結晶シリコン基板において、ｎ十
型ソースドレイン領域６が埋め込み導電膜１２及び薄い
再結晶シリコン基板部の２層において形成されている点
を除き、第２の実施例と同じ構造に形成されている。本
実施例においては、第２の実施例の効果に加え、ソース
ドレイン抵抗をさらに低減できるため、より高速ｆヒが
期待できる。In the figure, in a recrystallized silicon substrate with unevenness formed including a thick buried conductive film 12, an n0 type source/drain region 6 is formed in two layers: the buried conductive film 12 and the thin recrystallized silicon substrate. The second embodiment has the same structure as the second embodiment except for the following points. In this embodiment, in addition to the effects of the second embodiment, the source-drain resistance can be further reduced, so that higher speed f-hi can be expected.
又、第３図において、埋め込み導電膜の替わりに薄Ｊｆ
ｌ、％の再結晶シリコン層を設け、その上に選択化学気
相成長導電膜を形成し、その上に薄い再結晶シリコン基
板を設けたものにソース１くレイン頭載を形成してもよ
い９
次いで本発明にｆ系る半導体装置の製造方法の一実施例
について第４図（ａ）〜（ｅ）及び第１図を参照して説
明する。In addition, in FIG. 3, a thin Jf film is used instead of the buried conductive film.
1% recrystallized silicon layer, a selective chemical vapor deposition conductive film is formed thereon, and a thin recrystallized silicon substrate is provided on top of this, and a source 1 layer may be formed on top of the recrystallized silicon layer. 9 Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 4(a) to 4(e) and FIG. 1.
第４図（ａ）
ｐ−型シリコン（Ｓｉ ）基［１に６００ｎｎ＋程度）
Ｒｆヒ膜２を熱酸「ヒにより形成する０次いで（ヒ学気
相成長法により４５０ｎｍ稈度の＠ｆヒ膜３を成長させ
る９次いで通常のフォＩ・リソグラフィー技術を利用し
、レジスト（図示せず）をマスク層として、酸ｆヒ膜３
をドライエツチングする。（その際多少下地の熱酸化膜
２が工・ソチングされてもさしつかえない。）次いでレ
ジストを除去する〜
第４図（１））
次いで化学気相成長法により第１の多結晶シリコン膜１
３を成長させる。次いで異方性ドライエ・ソチングによ
り酸化膜３の開孔部に第１の多結晶シリコン膜１３を埋
め込む、 （４５０ｎｍ程度の膜厚）第４図（Ｃ）
次いてゴヒ学気相成長法により５０ｎｍ程度の第２の多
結晶シリコン膜１４を成長させる。Figure 4 (a) p-type silicon (Si) group [approximately 600 nn+ in 1]
The Rf film 2 is formed by thermal acid deposition. Next, the @f film 3 with a 450 nm fertility is grown by the chemical vapor phase epitaxy method. Next, a resist (Fig. (not shown) was used as a mask layer, the acid f arsenic film 3
Dry etching. (At this time, there is no problem even if the underlying thermal oxide film 2 is etched/soched to some extent.) Next, the resist is removed (Figure 4 (1)) Next, the first polycrystalline silicon film 1 is formed by chemical vapor deposition.
Grow 3. Next, the first polycrystalline silicon film 13 is buried in the opening of the oxide film 3 by anisotropic dry etching (film thickness of about 450 nm) as shown in FIG. 4(C). A second polycrystalline silicon film 14 of about 50 nm is grown.
第４図（（１）
次いでレーザーアニールをおこない、第２の多結晶シリ
コン膜１４及び第１の多結晶シリコン膜１３を再結晶化
させる１次いで通常のフォトリソグラフィー技術を利用
し、レジスＩ−（図示せず）をマスク層として、再結晶
シリコン膜を工・・ノチングし、凹凸型再結晶シリコン
基板４を形成する。次いでレジストを除去する。次いで
ゲート酸１ヒ膜７を成長させる。次いでｆヒ学気相成長
法により不純物を含んだ多結晶シリコン膜を成長させる
９次いで通常のフォトリソグラフィー技術を利用し、レ
ジスト（図示せず）をマスク層として、多結晶シリコン
膜をエツチングし、グー１−電極８を形成する。次いで
レジスＩ・を除去する。FIG. 4 ((1) Next, laser annealing is performed to recrystallize the second polycrystalline silicon film 14 and the first polycrystalline silicon film 13. Next, a resist I-( (not shown) is used as a mask layer, the recrystallized silicon film is etched to form an uneven recrystallized silicon substrate 4.Then, the resist is removed.Then, a gate acid film 7 is grown.Next, f A polycrystalline silicon film containing impurities is grown using a chemical vapor phase epitaxy method.9 Next, using a conventional photolithography technique, the polycrystalline silicon film is etched using a resist (not shown) as a mask layer. - Form electrode 8. Then remove resist I.
第４図（ｅ）
次いで通常のフォトリソグラフィー技術を利用し、レジ
スト（図示せず）及びゲート電極８をマスク層として、
砒素をイオン注入してｎ生型ソースドレイン領域６を、
同じレジスト〈図示せず）をマスク層として、硼素をイ
オン注入してｐ型チャネル領域５を、凹凸型再結晶シリ
コン基板４にそれぞれ選択的に順次画定する６次いでレ
ジストを除去する。FIG. 4(e) Next, using a normal photolithography technique, using a resist (not shown) and the gate electrode 8 as a mask layer,
Arsenic is ion-implanted to form n-type source/drain regions 6.
Using the same resist (not shown) as a mask layer, p-type channel regions 5 are selectively and sequentially defined in the uneven recrystallized silicon substrate 4 by ion implantation of boron.6 Then, the resist is removed.
第１図 次いで不要のゲート酸化膜７を工・ソチング除去する。Figure 1 Next, unnecessary gate oxide film 7 is removed by etching and soching.
次いで通常の技法を適用することによりブロック用酸化
膜９及び燐珪酸ガラス（ＰＳＧ）膜１０の成長、高温熱
処理によるｎ生型ソースドレイン領域６及びｐ型チャネ
ル領域５の形成、電極コンタクト窓の形成、Ａ１配線１
１の形成等をおこない半導体装置を完成する９
以上実施例に示したように、本発明の半導体装置によれ
ば、チャオ・ル領域を薄い再結晶シリコン基板部に形成
できることにより、レーザー再結晶１ヒにより完全に再
結晶１とされたチャネル領域を形成できるなめ、素子特
性の安定化による高性１ｊ旧ヒ及びゲーＩ−電圧印加に
より、チャネル領域が完全に空乏１ヒされ、チャネル領
域電界を小さくできるため、モビリティを大きくするこ
とかできることによる高速化を、ソースドレイン領域を
厚い再結晶シリコン基板部に形成できることにより、ソ
ースドレイン抵抗及び接合容量を低減できることによる
高速化を、凹凸を持った再結晶シリコン基板を使用でき
るため、熱容量を大きくできることにより、レーザー再
結晶１ヒによる再結晶シリコン基板のハガレを改善でき
ることによる高ｆｓ顆性を可能にすることができる。又
、各領域をセルファラインに形成することもできるため
、高集積（ヒを可能にすることもできる。さらに、ソー
スドレイン領域を埋め込み導電膜及び薄い再結晶シリコ
ン基板部の２層により形成することもできるなめ、ソー
スドレイン抵抗をさらに低減できるので、より高速（ヒ
を可能にすることもできる。Next, by applying conventional techniques, a blocking oxide film 9 and a phosphosilicate glass (PSG) film 10 are grown, an n-type source/drain region 6 and a p-type channel region 5 are formed by high-temperature heat treatment, and an electrode contact window is formed. , A1 wiring 1
9. As shown in the embodiments above, according to the semiconductor device of the present invention, the chao-lu region can be formed in the thin recrystallized silicon substrate portion, so that the laser recrystallization step 1 can be completed. Since it is possible to form a channel region completely recrystallized as 1 by H, the channel region is completely depleted by applying a voltage of 1j old and 1, which stabilizes the device characteristics, and the channel region electric field is reduced. By forming the source-drain region in a thick recrystallized silicon substrate, the source-drain region can be formed in a thick recrystallized silicon substrate, which can reduce the source-drain resistance and junction capacitance. Since a crystalline silicon substrate can be used, the heat capacity can be increased, and peeling of the recrystallized silicon substrate due to laser recrystallization can be improved, thereby making it possible to achieve high fs curvature. In addition, since each region can be formed as a self-alignment line, it is possible to achieve high integration.Furthermore, the source/drain region can be formed with two layers: a buried conductive film and a thin recrystallized silicon substrate. Since the source-drain resistance can be further reduced, higher speeds can be achieved.
［発明の効果］
以上説明のように本発明によれば、Ｍ Ｉ Ｓ型半導体
装置において、凹凸を持った再結晶シリコン基板の薄い
再結晶シリコン基板部にチャオ・小領域を形成し、厚い
再結晶シリコン基板部にソーストしイン領域を形成する
構造を有するＳ○■型のＭＩＳ電界効果Ｉ・ランジスク
を形成できるためチャネル領域を薄い再結晶シリコン基
板部に形成できることにより、再結晶シリコン基板を完
全に再結晶ｆヒできるため、素子特性の安定ｆヒによる
高性能１ヒ及びチャネル電界を小さくできるため、モヒ
刃ティを大きくすることかできることによる高速１′ヒ
を、ソースドレイン領域を厚い再結晶シリコン基板部に
形成できることにより、抵抗及び接合容量を低減できる
ことによる高速ｆヒを、凹凸を持った再結晶シリコン基
板を使用できるため、熱容量を大きくできることにより
、レーザー再結晶１ヒによる基板ハガレを改善できるこ
とによる高信頼性を、各領域をセルファラインに形成で
きることによる高集積１ヒを、メタル層を含むソースド
レイン領域を形成できることによるいっそうの高速１ヒ
も可能にすることができろ。即ち、高信頼、高性能、高
速且つ高集積な半導体集積回路の形成を可能とした半導
体装置を得ることができる。[Effects of the Invention] As described above, according to the present invention, in an MIS type semiconductor device, a chao small region is formed in a thin recrystallized silicon substrate portion of a recrystallized silicon substrate having irregularities, and a thick recrystallized silicon substrate is formed. Since it is possible to form an S○■ type MIS field effect I-range disk with a structure in which the source is sourced in the crystalline silicon substrate part and an in region is formed, the channel region can be formed in the thin recrystallized silicon substrate part, so that the recrystallized silicon substrate can be completely removed. Since recrystallization can be performed quickly, the device characteristics can be stabilized.High performance due to f can be made small, and the channel electric field can be made small, resulting in high-speed 1' due to the ability to increase the Mohi edge. Since it can be formed on the silicon substrate, resistance and junction capacitance can be reduced, resulting in high-speed f-f, and since a recrystallized silicon substrate with unevenness can be used, heat capacity can be increased, which improves substrate peeling caused by laser recrystallization. It is possible to achieve high reliability by forming a self-contained semiconductor device, high integration by forming each region as a self-line, and even higher speed by forming a source/drain region including a metal layer. That is, it is possible to obtain a semiconductor device that enables formation of a highly reliable, high-performance, high-speed, and highly integrated semiconductor integrated circuit.
第１図は本発明の半導体装置における第１の実施例の模
式側断面図、
第２図は本発明の半導体装置における第２の実施例の模
式側断面図、
第３図は本発明の半導体装置における第３の実施例の模
式側断面図、
第４図（ａ）〜（ｅ）は本発明の半導体装置における製
造方法の一実施例の工程断面図、
第５図は従来の半導体装置の模式側断面図である。
図において、
１はｐ−型シリコン（Ｓｉ）基板、
２は第１の酸化膜、
３は第２の酸１ヒ膜、
Ｌｌは凹凸型再結晶シリコン基板、
５はｐ型チャネル領域、
６はｎ十型ソースドレイン＠域、
７はゲート酸ｊヒ膜、
８はゲート電極、
９はブロック用酸化膜、
１０は燐珪酸ガラス（ＰＳＧ）膜、
１っけＡ１配線、
１２は埋め込み導電膜
を示す。
特許用願人 白土猛英
本発明の半導体装置における
第１の実施例の模式側断面図
１はｐ−型シリコン（Ｓｉ）基板
２は第１の酸化膜
３は第２の酸化膜
４は凹凸型再結晶シリコン基板
５はｐ型チャネル領域
６はｎ十型ソースドレイン領域
７はゲート酸化膜
８はゲート電極
９はブロック用酸化膜
１０は燐珪酸ガラス＜ｐｓａ＞膜
１１は＾ｌ配線
本発明の半導体装置における
第３の実施例の模式側断面図
第３図
１はｐ−型シリコン（Ｓｉｌ基板
２は第１の酸化膜
３は第２の酸化膜
４は凹凸型再結晶シリコン基板
５はρ型チャネル領域
６はｎ十型ソースドレイン領域
７はゲート酸化膜
８はゲートを極
９はブロック用酸化膜
１０は燐珪酸ガラス（ＰＳＧ）膜
１１はＡ１配線
１２は埋め込み導電膜
本発明の半導体装置における
第２の実施例の模式側断面図
１はｐ−型シリコン（Ｓｉ）基板
２は第１の酸化膜
３は第２の酸化膜
４は凹凸型再結晶シリコン基板
５はｐ型チャネル領域
６はｎ十型ソースドレイン領域
７はゲート酸化膜
８はゲート電極
９はブロック用酸化膜
１０は燐珪酸ガラス（ＰＳＧ）膜
１１はＡ１配線
本発明の半導体装置における
製造方法の一実施例の工程断面図
第４図
本発明の半導体装置における
製造方法の一実施例の工程断面図
第４図
従来の半導体装置の
模式側断面図
第
図FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of a semiconductor device of the present invention, and FIG. 3 is a semiconductor device of the present invention. A schematic side sectional view of a third embodiment of the device; FIGS. 4(a) to (e) are process sectional views of an embodiment of the manufacturing method for the semiconductor device of the present invention; FIG. 5 is a schematic side sectional view of a conventional semiconductor device. It is a schematic side sectional view. In the figure, 1 is a p-type silicon (Si) substrate, 2 is a first oxide film, 3 is a second arsenic acid film, Ll is an uneven recrystallized silicon substrate, 5 is a p-type channel region, and 6 is a n-type source/drain region, 7 is a gate oxide film, 8 is a gate electrode, 9 is a block oxide film, 10 is a phosphosilicate glass (PSG) film, 1 is an A1 wiring, 12 is a buried conductive film show. Patent applicant: Takehide Shirato A schematic side cross-sectional view 1 of a first embodiment of a semiconductor device of the present invention shows a p-type silicon (Si) substrate 2, a first oxide film 3, a second oxide film 4, and an uneven structure. The type recrystallized silicon substrate 5 is the p-type channel region 6, the n-type source/drain region 7, the gate oxide film 8, the gate electrode 9, the blocking oxide film 10, the phosphosilicate glass <PSA> film 11, the ^l wiring of the present invention A schematic side cross-sectional view of a third embodiment of a semiconductor device in FIG. The ρ type channel region 6 is the n+ type source drain region 7 is the gate oxide film 8 is the gate electrode 9 is the blocking oxide film 10 is the phosphosilicate glass (PSG) film 11 is the A1 wiring 12 is the buried conductive film the semiconductor of the present invention A schematic side cross-sectional view 1 of a second embodiment of the device shows a p-type silicon (Si) substrate 2, a first oxide film 3, a second oxide film 4, a concavo-convex recrystallized silicon substrate 5, and a p-type channel region. 6 is an n-type source/drain region 7 is a gate oxide film 8 is a gate electrode 9 is a blocking oxide film 10 is a phosphosilicate glass (PSG) film 11 is an A1 wiring process of an embodiment of the manufacturing method for a semiconductor device of the present invention 4. Cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a schematic side sectional view of a conventional semiconductor device.
Claims (3)
シリコン基板にＭＩＳ電界効果トランジスタを形成した
半導体装置であつて、チャネル領域形成部をソースドレ
イン領域形成部より薄く形成した凹凸型再結晶シリコン
基板にＭＩＳ電界効果トランジスタを形成したことを特
徴とする半導体装置。(1) A semiconductor device in which a MIS field effect transistor is formed on a recrystallized silicon substrate formed on a semiconductor substrate with an insulating film interposed therebetween, in which the channel region forming part is formed thinner than the source drain region forming part. A semiconductor device characterized in that a MIS field effect transistor is formed on a crystalline silicon substrate.
され、前記薄い再結晶シリコン基板部上にゲート絶縁膜
を介してゲート電極が形成され、且つ厚い再結晶シリコ
ン基板部にソースドレイン領域が形成されていることを
特徴とする特許請求の範囲第１項記載の半導体装置。(2) A channel region is formed in a thin recrystallized silicon substrate portion, a gate electrode is formed on the thin recrystallized silicon substrate portion via a gate insulating film, and a source/drain region is formed in the thick recrystallized silicon substrate portion. A semiconductor device according to claim 1, characterized in that:
、且つソースドレイン領域が導電膜を含む再結晶シリコ
ン基板部に形成されていることを特徴とする特許請求の
範囲第１項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the channel region is formed in a recrystallized silicon substrate portion, and the source/drain region is formed in a recrystallized silicon substrate portion including a conductive film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1293433A JP2543416B2 (en) | 1989-11-11 | 1989-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1293433A JP2543416B2 (en) | 1989-11-11 | 1989-11-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03154383A true JPH03154383A (en) | 1991-07-02 |
| JP2543416B2 JP2543416B2 (en) | 1996-10-16 |
Family
ID=17794697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1293433A Expired - Fee Related JP2543416B2 (en) | 1989-11-11 | 1989-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2543416B2 (en) |
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| JPH03155166A (en) * | 1989-11-14 | 1991-07-03 | Fuji Electric Co Ltd | Thin film semiconductor element |
| US5281828A (en) * | 1991-09-20 | 1994-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor with reduced leakage current |
| US5821559A (en) * | 1991-02-16 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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| JPS63200572A (en) * | 1987-02-17 | 1988-08-18 | Seiko Instr & Electronics Ltd | Manufacture of thin film semiconductor device |
| JPH0284772A (en) * | 1988-09-21 | 1990-03-26 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH0298969A (en) * | 1988-10-06 | 1990-04-11 | Agency Of Ind Science & Technol | Mos transistor and manufacture thereof |
| JPH02257672A (en) * | 1989-03-30 | 1990-10-18 | Seiko Epson Corp | Manufacture of soi structure mis-fet |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03155166A (en) * | 1989-11-14 | 1991-07-03 | Fuji Electric Co Ltd | Thin film semiconductor element |
| US5821559A (en) * | 1991-02-16 | 1998-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5281828A (en) * | 1991-09-20 | 1994-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor with reduced leakage current |
| US5436184A (en) * | 1991-09-20 | 1995-07-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| US7148542B2 (en) | 1992-02-25 | 2006-12-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
| US7649227B2 (en) | 1992-02-25 | 2010-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2543416B2 (en) | 1996-10-16 |
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