JPS6351677A - Semiconductor device provided with junction-type effect transistor - Google Patents

Abstract

PURPOSE:To stabilize a device in its electrical characteristics and enlarge the diameter of a wafer through decreasing variations in thickness and resistance of a semiconductor region to serve as a channel region by a method wherein a semiconductor region lower in concentration than and same in conductivity type as a semiconductor substrate is formed on said semiconductor substrate, ions are implanted into said region for the construction of a semiconductor region of the reverse conductivity type, and this semiconductor region is used as a channel region. CONSTITUTION:On a substrate, a P-type region 2 of an impurity concentration N2 which is lower than an impurity concentration N3 is formed by ion implantation. On the P<+>-type region 2, an N-type region 3 is formed of an impurity concentration N3, by ion implantation. An insulating film 7 is next formed selectively on the substrate by photolithography. The planar diffusion method is then used for the formation of a P-type gate region 5 within the N-type region 3. There is connection between the region 5 and region 1. A process follow wherein an N<+>-type substrate 6 is formed and the insulating film 7 is then subjected to selective removal for the creation of contact windows. A metal wiring 8 is selectively formed through the contact windows for the construction of a junction-type field effect transistor. The ion-implanted N-type semiconductor region 3 serves as a channel layer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a junction field effect transistor (hereinafter referred to as J-FET).
The present invention relates to a semiconductor device having a semiconductor AM (hereinafter referred to as "AM"), and particularly to a semiconductor device having a junction field effect transistor whose channel region is formed by ion implantation technology to reduce characteristic fluctuations.

[Conventional technology]

An example of a semiconductor substrate used in a conventional N-channel type J-FET is shown in FIG. 5(a). Is this semiconductor substrate designed to make ohmic contact with the gate electrode and to reduce electrical resistance? A P' type substrate 1 of high yield is used, and an N type semiconductor region 9 is formed on this substrate 1 by epitaxially growing an N type impurity. FIG. 5(B) shows the impurity concentration at the depth X of the semiconductor substrate in FIG. 5(A).

Figure 6 shows an N-channel J-type using the substrate shown in Figure 5 (a).
This shows an example of an FET.

An insulating film is selectively formed on a silicon substrate consisting of a type semiconductor region 1 and an N-type semiconductor region 9 using a photolithography technique, and a P-type head region 4 is formed using a Brenna diffusion technique. A P-type gate region 5 is formed in an N-type region 9 surrounded by , and the region 5 is electrically connected to the region 1 . Further, an N9 type region 6 (source/drain region) is formed in the region 9 to make ohmic contact with the electrode across the gate region 5, and a contact window is formed by selectively forming an insulating film 7. Open. A junction field effect transistor is formed by selectively forming metal wiring 8 through the contact window.

[Problem that the invention seeks to solve]

However, in a semiconductor device including a conventional junction field effect transistor, it is difficult to avoid variations of about ±10% in the thickness and resistance of the N-type semiconductor region 9 formed by epitaxial growth. Variations in the thickness result in variations in channel width, and variations in resistance are caused by variations in impurity concentration, and this variation causes the disadvantage that electrical characteristics become unstable. This tendency becomes stronger as the wafer becomes larger, making it difficult to increase the diameter of the J-FET.

[Means for solving problems]

The present invention has been made in view of the above, and aims to stabilize the electrical characteristics by suppressing variations in the thickness and resistance of the semiconductor region that becomes the channel region, and thereby reduce costs by increasing the diameter of the wafer. In order to achieve this, a semiconductor region of the same conductivity type but with a lower concentration is formed on the semiconductor substrate, and a semiconductor region of the opposite conductivity type is formed by ion implantation into this semiconductor region, and this becomes a channel region. The present invention provides a semiconductor device having a junction field effect transistor.

Hereinafter, a semiconductor device having a junction field effect transistor of the present invention will be explained in detail.

〔Example〕

FIG. 1 (a), (o), and (71) show the cross-sectional structure of the semiconductor substrate of the present invention, and (d), (ne), and (f) are sequentially (a), (u), and (/l). ) shows the impurity concentration corresponding to

As shown in FIG. 1(0), a P wall region 2 having a lower concentration N2 than the ion implantation impurity concentration N2 described later is formed, and as shown in FIG. 1(c), a P wall region 2 is formed.

The impurity concentration N3 is deposited on the mold region 2 by ion implantation technology.
A mold region 3 is formed.

Figure 2 shows an N-channel type J using this substrate according to the present invention.
- indicates a FET. An insulating film 7 is selectively formed using a photolithography technique on a silicon substrate consisting of a P type semiconductor region 101, a P type semiconductor region 2, and an N type semiconductor region 3 ion-implanted to have an impurity concentration of N3,
A P-type gate region 5 is formed in an N-type region 3 surrounded by a P-wall region 2 by a planar diffusion technique, and the region 5 is connected to the region 1. Furthermore, in order to make ohmic contact with the electrode by sandwiching the gate region 5 within the region 3,
A contact window is opened by forming an N''' type region 6 (source/drain region) and selectively forming an insulating film 7. A contact window is opened by selectively forming a metal wiring 8 through this contact window. A type field effect transistor is formed. Here, the N type semiconductor region 3 formed by ion implantation becomes a channel layer.

As mentioned above, the variation in the thickness and resistance of the semiconductor region due to epitaxial growth is about ±10%, whereas when using ion implantation technology as in the present invention, the variation is ±5%.
It can be reduced within

The ion concentration due to ion implantation is given by the following equation.

Here, N (Z) is the ion concentration N1 is the implantation amount per unit area Z is the substrate depth R1)> is the projected range of ions ΔRp> is the standard deviation According to the above formula, the ion concentration is compared to conventional epitaxial growth. can be controlled with much higher precision and the aforementioned variations can be reduced.

More specifically, it is as follows.

As shown in FIGS. 1(a) to (f), a low concentration impurity concentration N2 (for example, -5X
A semiconductor region 2 with a thickness of 1.5 cm is formed, and ions of an opposite conductivity type impurity N are implanted into the semiconductor region 2, so that the formed surface impurity concentration is N.

(For example, l×l Q I S cIo-3), the impurity concentration N of ion implantation at the time of conversion is given by the following equation.

N"'Nz N3 = I XIO" + 5 XIO" = 6 Controlling the depth is very difficult due to large concentration differences.

For example, if the impurity concentration of one conductivity type base with a high impurity concentration is N (for example, I The impurity concentration is Nl (for example,
−5×10”cm−′), the impurity concentration N° of ion implantation is given by the following equation.

N' = N, -N.

= I For example, N' = 1.00
5 xlQIIl (cm-3), then this is 1
% deviation N' = 1.015xlQ18 (cm-3
), the surface impurity concentration is N, = 1.5
IO"(cm-'), and the required value is 5 ×
There is a difference of three times compared to 1QI5 (cm-').

On the other hand, for example, N= 6 XIO"(cm-'
), this shifts by 1% and becomes N=6.06xlOI
5(am -'), the required value 5X1
The deviation from 0''(cm-'') is small, and there is little variation due to the precision of ion implantation.

From the above, forming a low concentration semiconductor region of the same conductivity type on a high concentration substrate as in the present invention is extremely effective in controlling the concentration and depth by ion implantation.

FIG. 3(a), (t+), (11) shows the cross-sectional structure of the second embodiment of the present invention, (=), (+)
, (f) indicates impurity concentrations corresponding to (a), ([1), and (c) in sequence.

As shown in FIG. 3(0), an N-type impurity region 12 with a concentration N2 lower than the ion-implanted impurity concentration is formed on an N-type substrate 11 with a concentration N1 shown in FIG. 3(a). As shown in FIG. 3C, a P-type channel layer 13 is formed by ion-implanting a P-type impurity onto the region 12 and diffusing it.

FIG. 4 shows a P-channel type J-FET manufactured by planar diffusion technology using this substrate according to the present invention. Here, 15 is an N-type gate region, and 16 is a P-type gate region.
''-type ohmic contact region, 17 is an insulating film having a contact window, 1 is a metal wiring, and a P-type semiconductor region 13 formed by ion implantation becomes a channel region.

(Effects of the Invention) As explained above, according to the semiconductor device having the junction field effect transistor of the present invention, a semiconductor region of the same conductivity type and lower concentration than that of the semiconductor substrate is formed on the semiconductor substrate,
By forming a semiconductor region of the opposite conductivity type in this semiconductor region by ion implantation and using this as a channel region, variations in the thickness and abrasive resistance of the semiconductor θ■ region that will become the channel region are suppressed, and the electrical characteristics are improved. Stabilize, and
This makes it possible to reduce costs by increasing the diameter of the wafer.

[Brief explanation of drawings]

Figure 1 (A), (Tl), and (C) are J-FETs of the present invention.
FIG.
, 1, ), (*), (f) are explanatory diagrams showing impurity concentrations, FIG. 2 is an explanatory diagram showing one embodiment of the present invention, and FIG.
Figures (A), (Ill), and (C) are other J-FEs of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a T wafer; FIGS. 3(d), (*), and (f) are explanatory views showing impurity concentrations; FIG. , Fig. 5(A) and (El) are explanatory diagrams showing the cross-sectional structure and impurities of a conventional J-FET wafer, and Fig. 6 is an explanatory diagram showing a conventional J-FET wafer.
A sectional view showing an FET. Explanation of symbols 1-----P" type semiconductor region 2--P-type semiconductor region 3--N-type semiconductor region 4 by ion implantation
P-type semiconductor region 5--Gate (P-type) region 6--N'' type ohmic contact region 7--
-Insulating film 8--Metal wiring 9--N-type semiconductor region 11 by evixaxial growth N-type semiconductor region 12--N-type semiconductor region 13-...P-type semiconductor region 14 by ion implantation
−・−・N type semiconductor region

Claims (1)

Claims: A first semiconductor region of one conductivity type formed on a semiconductor substrate of one conductivity type and having an impurity concentration lower than that of the substrate; a junction field effect transistor including a second semiconductor region of a conductivity type opposite to the one conductivity type and having an impurity concentration higher than that of the semiconductor region; and a gate, a source, and a drain provided in the second semiconductor region. . A semiconductor device having a junction field effect transistor, wherein the second semiconductor region is a channel region.