JPS63261748A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To have a constitution of an activated element part excellent in high degree of speed and integration and to improve the manufactural controllability of the activated element part by connecting a second semiconductor region as an outer base with a third semiconductor region as an inner base at an intermediate base directly under the edge sections of an opening of an oxide film as an insulating film in case of a bipolar transistor. CONSTITUTION:A thermal oxide film 122 having the beak-shaped edge sections is formed at an N-type epitaxial semiconductor layer 104 with an N-type buried layer 102 formed onto a P-type silicon semiconductor substrate 100, and a P-type semiconductor region 116 as an outer base and a trench section 142 formed within an opening by the film are formed under the main section of the oxide film. And, a P-type semiconductor region 126 as an inner base is formed at a low section of the trench section. The outer base 116 is connected with the inner base 126 through a P-type semiconductor region 118 as an intermediate base formed directly under the beak-shaped edge sections of the oxide film. Thus, a poly-silicon electrode 124 is formed onto an N-type semiconductor region 128 serving as an emitter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to the structure of a transistor element suitable for increasing the speed and integration of bipolar type integrated circuits and the like, and a method for manufacturing the same.

BACKGROUND OF THE INVENTION In recent years in the field of bipolar integrated circuits, various new techniques have been proposed for improving the switching speed of transistors. The main improvements based on these technologies are to shorten the transit time of electrons in the base by making the internal base of the vertical NPN transistor shallower and narrowing the width of the base in the depth direction; To reduce the delay time caused by the coupling between the parasitic base resistance and the base human capacitance that are connected in series with the The so-called graft-based method is known, in which a parasitic base region for electrode extraction is formed by diffusion with impurities at a higher concentration than the internal base, and this is used as the external base.For example, in 1984 International Electron Device Meeting Digest of Technical Papers (INTE
RNATIONAL ELECTRON DEVI
CE MEETING 0IGESTOF TE
CHNICAL PAPER5PP, 753-756
), in the formation of a vertical NPN transistor, an external base formed under a thermal oxide film and an internal base formed from an opening in the thermal oxide film are connected near the edge of the thermal oxide film. is disclosed.

Problems to be Solved by the Invention In order to increase the speed of bipolar transistors, it is necessary to simultaneously form a shallow internal base and a low resistance external base. As the internal base becomes shallower, the layered resistance of the internal base tends to increase.To reduce this effect, a method is usually taken to reduce the width of the emitter.However, in this case, the height of the external base If the impurity concentration is increased (this will cause impurity atoms to enter the internal base, changing the impurity profile of the internal base, decreasing the current amplification factor for DC, increasing the base transit time of electrons for AC, etc.) The only way to suppress this phenomenon is to lower the impurity concentration of the external base and reduce the lateral diffusion of the base.

This method reduces the infiltration of external bases, but
If the internal base is formed to a very shallow depth of 150 nanometers, the following structural or manufacturing problems will occur: The opening end formed by the beak-shaped end of the oxide film The connectivity between the internal base and the external base itself becomes unstable due to unstable fluctuations due to the etching inside.Furthermore, if the connection is poor, the lateral diffusion of the internal base under this peak is small. , because the effective base width is narrow, punch-through leakage current between the collector and emitter is likely to occur.For example, as shown in Figure 3(a), the P-type An N-type buried layer 102 is formed on a silicon semiconductor substrate 100, and an N-type epitaxial semiconductor layer 10 is formed.
After forming 4, a thin thermal oxide film 1 of about 20 nanometers is formed.
Using the silicon nitride film pattern 110 with a thickness of about 100 nanometers formed on 08 as a mask, the dose was 2X.
Boron ions of IO15/c+J were ion-implanted to form a P-type semiconductor region 116 serving as an external base. moreover,
As shown in FIG. 3(b), thermal oxidation is performed using the oxidation-resistant silicon nitride film pattern 110 as a mask, and the thickness is approximately 2.
After forming an oxide film 122 of 50 nanometers, the silicon nitride film pattern 110 and oxide film 108 are removed to form an opening for an emitter, and a polycrystalline silicon film is deposited on the entire surface, which is then patterned. A polycrystalline silicon film pattern 124 is formed, and the dose m 2
/cd boron to this polycrystalline silicon film pattern 1
After ion implantation into the polycrystalline silicon film pattern 124 and heat treatment to form a P-type semiconductor region 126 which becomes an active base with a depth of about 150 nanometers, arsenic is similarly ion-implanted into the polycrystalline silicon film pattern 124. After heat treatment, the depth is reduced to approximately 5.
N-type semiconductor region 12 serving as a 0 nanometer emitter
8 was formed.

According to such a manufacturing method, as shown in FIG. 3(b), depending on the shape of the beak-shaped end of the oxide film pattern 122, the outer base 116 and the inner base 12
Connectivity with 6 becomes difficult. Therefore, there is a need for a new transistor structure and a method for manufacturing the same that solves the structural and manufacturing problems caused by the unstable connection between the external base and the internal base.

Means for Solving the Problems The present invention aims to solve these problems (by providing an opening in an insulating film having a beak-shaped edge at the periphery formed on a semiconductor layer of a first conductivity type; A first semiconductor region of the second conductivity type formed immediately below the beak-shaped end of the insulating film, and a second conductive region formed below the beak-like end of the insulating film. a second conductivity type semiconductor region, a groove formed in the opening of the insulating film having the beak-shaped end, and a second conductivity type third semiconductor region formed in the groove; A structure including a fourth semiconductor region of the first conductivity type formed in the third semiconductor region of the second conductivity type,
A structure of a semiconductor device characterized in that the second semiconductor region and the third semiconductor region are connected via the first semiconductor region, and an oxidation-resistant layer is provided on the semiconductor layer of the first conductivity type. forming a first semiconductor region of a second conductivity type on the surface of the semiconductor layer immediately below the oxidation-resistant mask material pattern; A second layer of the second conductivity type is placed around the material pattern.
forming an oxide film having beak-shaped edges around the oxidation-resistant mask material pattern by an oxidation method using the oxidation-resistant mask material pattern as a mask; forming an opening in the oxide film pattern having the beak-shaped end by removing the mask material pattern; forming a groove in the opening of the oxide film pattern having the beak-shaped end; The step of forming a third semiconductor region of the second conductivity type in the trench, and the step of forming a fourth semiconductor region of the first conductivity type in the third semiconductor region, The present invention provides a method of manufacturing a semiconductor device, characterized in that a second semiconductor region and the third semiconductor region are connected via the first semiconductor region.

Effects When the measures according to the invention were applied, by way of example, to the emitter-base junction of a bipolar transistor, the following effects occurred.

A first semiconductor region of a second conductivity type that serves as an intermediate base that connects a second semiconductor region that serves as an external base and a third semiconductor region that serves as an internal base directly below the edge of the opening of an oxide film that is an insulating film.
The impurity concentration of the semiconductor region or the total number of impurity atoms per unit area can be made smaller than that of the internal base, thereby preventing impurity atoms of the external base from directly penetrating into the internal base. did it. Gah,
The groove formed in the opening of this oxide film allows the internal base to be as deep as the external base, making it possible to thin the N-type epitaxial layer left between the internal base and the N-type buried layer directly below it. This made it possible to reduce the collector resistance. As a result of the above, it was possible to prevent the occurrence of negative phenomena such as a decrease in the current amplification factor in the case of direct current, and an increase in the base transit time of electrons in the case of alternating current. Furthermore, since the collector resistance could be reduced, the switching time of the transistor could be improved.

Furthermore, since the external base and internal base are not directly connected, each impurity profile can be optimized independently, making it easier to control impurity diffusion and improving manufacturing yield.

Furthermore, inside the opening of the oxide film having a beak-shaped end,
If the first semiconductor region of the second conductivity type is formed in advance, by forming a groove in this opening, unnecessary first semiconductor regions other than directly under the beak-shaped end can be removed. Therefore, the influence of impurity atoms by ion implantation during the formation of the intermediate base on the impurity profile of the third semiconductor region of the second conductivity type, which will be formed on the lower surface of the trench and will become the internal base, will be almost eliminated ( As a result, good device characteristics with little variation in current amplification factor were obtained.

Embodiment A first embodiment in which the structure method according to the present invention is applied to the emitter-base junction of a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 1, a thermal oxide film 122 having beak-shaped edges is formed in an N-type epitaxial semiconductor layer 104 having an N-type buried layer 102 formed on a P-type silicon semiconductor substrate 100. Then, under the main part of this oxide film, there is a P-type semiconductor region 116 which becomes an external base.
A trench 142 is formed in the opening formed by this oxide film, and a P-type semiconductor region 126 serving as an internal base is formed at the bottom of the trench. The external base 116 and the internal base 126 are connected via a P-type semiconductor region 118 that serves as an intermediate base and is formed directly under the beak-shaped end of the oxide film, and an N-type semiconductor region that serves as an emitter. A polysilicon electrode 124 is formed at 128 .

As an example of a method for forming such an emitter-base junction, if polysilicon electrode 124 is used as a diffusion source for internal base 126 and emitter 128, the internal base depth 15
0 nanometer and emitter depth of 50 nanometers, allowing for a structure with excellent high-speed performance.Moreover, since the internal base and external base can be connected via an intermediate base with a relatively low impurity concentration, the external It was possible to prevent highly concentrated impurities in the base from penetrating into the internal base and change the impurity profile of the internal base, and to stabilize the connectivity of the base. Further, in the structure shown in FIG. 1, the shape of the side surface of the groove is vertical, but it may be formed into any shape as required. For example, the beak-shaped end of the oxide film and the P-type semiconductor region 11 that becomes the external base
6, if the groove is formed using an isotropic etching method so that the sides of the groove go under the beak-shaped end, the inner and outer bases can be separated. In other words, the width of the intermediate base can be reduced, and parasitic base resistance can be reduced.

Next, a second embodiment in which the method of the present invention is applied to a method for manufacturing a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 2(a) (P-type silicon semiconductor substrate 10
After forming an N-type buried layer 102 on 0, an N-type epitaxial semiconductor layer 104 was formed.

After forming the P-type element isolation region 106, approximately 20 nm
Using the silicon nitride films 110A and 110B with a thickness of about 100 nanometers formed on the thin thermal oxide films 108A and 108B of the meters as masks, thermal oxidation is performed to form a thick oxide film 112 with a thickness of about 600 nanometers. did.

As shown in FIG. 2(b), a resist pattern 114 is formed by a photomask process, and using this as a mask, a silicon nitride film pattern 114 with a width of approximately 1 micron is left on the area where the emitter is to be formed.
Dose amount 2XIO”/c using pattern 114 as a mask
A P-type semiconductor region 116, which will become an external base, was formed by ion-implanting boron of j.

As shown in FIG. 2(C), after removing the resist pattern 114, an N-type semiconductor region 120 is selectively formed by ion implantation of phosphorus, and then a
012/cJ boron silicon nitride film pattern 110
Ions are implanted to have a peak concentration at the silicon interface through C to form a P-type shallow semiconductor region 1 that will serve as an intermediate base.
18 was formed.

As shown in FIG. 2(d), thermal oxidation was performed using the oxidation-resistant silicon nitride film pattern 110C as a mask to form an oxide film 122 with a thickness of about 200 nanometers.

As shown in FIG. 2(e), silicon nitride film pattern ll0
After removing the C1 oxide film 108A and forming an opening for the emitter, a resist pattern 140 was formed, and using this as a mask, a groove 142 was formed in the opening for the emitter. By forming this groove, a P-type shallow semiconductor region 11 which is to be an intermediate base formed in the emitter opening is formed.
Most of the 8 were removed.

As shown in FIG. 2(f), a polycrystalline silicon film is deposited on the entire surface, patterned to form polycrystalline silicon film patterns 124A and 124B, and
Boron ions of x 10"/cd were ion-implanted into this polycrystalline silicon film pattern 124A, and then heated to about 15"/cd.
After forming a P-type semiconductor region 126 as an active base with a depth of 0 nanometers, arsenic ions are similarly implanted into this polycrystalline silicon film pattern 124A, and heat treatment is performed to reduce the depth to approximately An N-type semiconductor region 128 was formed to serve as a 50 nanometer emitter.

FIG. 2(g) Throat (with silicon oxide film 130 on the entire surface)
After depositing, aluminum electrodes 132A, 132B, 132c, etc. were formed according to a normal manufacturing method.

As described above, by the method of the present invention, a vertical NPN transistor is formed, and an active element part (internal base) structure with a base width of approximately 100 nanometers and excellent high speed performance is obtained. , the external base and internal base are thin (
Since the connection was made well through the shallow intermediate base, it was possible to prevent leakage current between the collector and emitter under the peak-shaped oxide film. Furthermore, since the collector resistance was reduced by forming the groove, the switching characteristics were improved, and the unnecessary intermediate base formed in the area where the internal base was to be formed was also removed, so the current amplification factor was improved. Good characteristics with little variation were obtained.

According to the method of the present invention, the emitter of the bipolar element is the gate, the external bases on both sides of the gate are the source,
When considered as a drain, it can function as a junction field effect transistor with the internal base as a channel portion. In this manner, the method of the present invention can be applied not only to bipolar devices but also to various semiconductor devices.

Effects of the Invention The structure of the present invention and its manufacturing method provide a semiconductor device having an active element structure that is excellent in high speed and high integration, and with good controllability in manufacturing the active element part. We were able to.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a bipolar NPN transistor according to the present invention, FIG. 2 is a series of cross-sectional views showing a method for manufacturing a bipolar NPN transistor according to the method of the present invention, and FIG. NPN
FIG. 2 is a cross-sectional view illustrating the structure of a transistor and problems in its manufacture. 100...P type semiconductor substrate, 102...N type buried layer, 104...N type semiconductor layer, 106.116.1
18.126...P semiconductor region, 120,128...
・N-type semiconductor region, 108.112.122.130・
...Silicon oxide film, 110...Silicon nitride film, 1
24...Polycrystalline silicon membrane, 114.140...Resist, 132...Aluminum electrode, 142...
Groove. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 2 Figure 3 nf

Claims (7)

[Claims] (1) An opening in an insulating film having a peripheral beak-shaped end formed on a first conductivity type semiconductor layer, and an opening formed at least directly under the beak-shaped end of the insulating film a first semiconductor region of two conductivity type; a second semiconductor region of second conductivity formed under a portion other than the beak-shaped end of the insulating film; and an insulator having the beak-shaped end. a groove formed in the opening of the film; a third semiconductor region of the second conductivity type formed in the groove; and a first semiconductor region formed in the third semiconductor region of the second conductivity type. A semiconductor device having a structure including a conductive type fourth semiconductor region, wherein the second semiconductor region and the third semiconductor region are connected via the first semiconductor region. (2) The first semiconductor region is an intermediate base, the second semiconductor region is an external base, the third semiconductor region is an internal base, and the fourth semiconductor region is an internal base.
2. The semiconductor device according to claim 1, wherein a semiconductor region of is used as an emitter. (3) Claim 1 or 2 characterized in that the total number of impurity atoms per unit area of the first semiconductor region is smaller than that of the third semiconductor region of the second conductivity type. 1. Semiconductor device described in Section 1. (4) forming an oxidation-resistant mask material pattern on the semiconductor layer of the first conductivity type; forming a second semiconductor region of a second conductivity type around the oxidation-resistant mask material pattern; and performing an oxidation method using the oxidation-resistant mask material pattern as a mask. A step of forming an oxide film having beak-shaped edges around the mask material pattern, and removing the oxidation-resistant mask material pattern to form an opening in the oxide film pattern having the beak-shaped edges. forming a groove in the opening of the oxide film pattern having the beak-shaped end; forming a third semiconductor region of the second conductivity type in the groove; forming a fourth semiconductor region of the first conductivity type in the third semiconductor region, and connecting the second semiconductor region and the third semiconductor region via the first semiconductor region. A method for manufacturing a semiconductor device characterized by connecting. (5) The first semiconductor region is an intermediate base, the second semiconductor region is an external base, the third semiconductor region is an internal base, and the fourth semiconductor region is an internal base.
5. The method of manufacturing a semiconductor device according to claim 4, wherein a semiconductor region of 1 is used as an emitter. (6) Claim 4 or 5, characterized in that the total number of impurity atoms per unit area of the first semiconductor region is smaller than that of the third semiconductor region of the second conductivity type. A method for manufacturing a semiconductor device according to section 1. (7) Claim 4, characterized in that the third semiconductor region of the second conductivity type and the fourth semiconductor region of the first conductivity type are formed using the same polycrystalline semiconductor as a diffusion source. 7. The method for manufacturing a semiconductor device according to any one of items 6 to 6.