KR920000632B1 - High quality bipolay transistor and its manufacturing method - Google Patents

Abstract

High performance bipolar transistor is manufactured by (a) forming link area for p layer (18) between intrinsic base p- layer (17) and extrinsic base p+ layer (19) under high conc. emitter area, and (b) forming a single inside connection part (24) between emitter N+ layer (22) and metal layer (29). This method can prevent current leakage by minimizing collision between high conc. layers, increase junction breakdown voltage and improve current amplification. And also it can simplify the manufacturing process and so reduce the cost.

Description

High Performance Bipolar Transistors and Manufacturing Method Thereof

1 is a vertical structure diagram of a conventional bipolar transistor.

2 is a vertical structure diagram of a bipolar transistor of the present invention.

3A to 3K are vertical structure diagrams for respective processes for explaining a method of manufacturing a bipolar transistor of the present invention.

* Explanation of symbols for the main parts of the drawings

1 silicon substrate 2 buried layer

3: epi layer 4: N + layer

5: field oxide film 6: pad oxide film

7: photoresist 8: p-ion implantation layer

9 nitride film 10 oxide film

11: photoresist 12: BSG film

14 BSG side wall 16 oxide film

17: p-layer 13,18: p layer

19: p + layer 20: polysilicon

21: oxide film 22: N + layer

24: internal connection poly 25: oxide film

26: photoresist 28: barrier metal layer

29: metal layer

The present invention relates to a structure of a high performance bipolar transistor that self-aligns an emitter using BSG and a single polysilicon, and a method of manufacturing the same.

The vertical structure diagram of a conventional bipolar transistor is as shown in FIG. As can be seen here, the buried layer 32, the epi layer 33, the N + layer 34 and the field oxide film 35 are formed on the silicon substrate 31, and the high concentration p + layer 36 is formed of the primary poly. The high concentration n + layer 39 on the P-layer 40 is connected to the secondary polysilicon 38 and is connected to the silicon 37 and the primary and secondary polysilicon 37 of each region of the transistor. And 38 are each made of metal 41.

In the conventional bipolar transistor, since the double polysilicon is used, a mask layer is further added, resulting in process complexity and device performance, and the p + layer 3 is connected to the primary polysilicon 37. Therefore, since there is a limit to reducing Rb, there is a limit to improving operation speed and noise immunity. In addition, since the overlapping by the lateral diffusion of the emitter region and the extrinsic base region causes leakage current of the high concentration layer, the internal pressure is lowered and the current amplification degree is lowered. In particular, the high field formed by the high concentration p + layer There is a problem that causes a surface leakage current by causing a collision of the carrier.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to minimize collisions between high concentration layers, thereby improving device characteristics such as prevention of leakage current, line breakdown and h _FE , and also reducing Rb. It is to provide a high-performance bipolar transistor and a method of manufacturing the same, which improves the operating speed and improves the noise characteristics, and in particular, expects cost reduction and yield improvement due to the simplification of the process. A feature of the present invention is the structure of a high performance bipolar transistor in which the bipolar transistor is composed of a single polysilicon layer and the p- and p + layers, which are respective regions of the transistor, are connected to the p-layer. A process of forming a normal intrinsic base, a process of defining an emitter region in a laminated structure of a nitride film and an oxide film after the process, depositing an BSG, and performing annealing, and a nitride film defining an emitter region after the process And forming an BSG sidewall by anisotropic etching on the side of the oxide film, implanting ions and annealing to form a p + layer, a p layer, and a p- layer, and removing the nitride film and the pad oxide film after the process. Depositing ions after depositing polysilicon and annealing after the step to form an emitter region of the N + layer Forming a barrier metal layer and a metal layer at an opening formed by the process, forming an interconnect poly after the process, and forming a photolithography and an etching process; and producing a bipolar transistor by a general photolithography process and a heat treatment process for the metal layer. It is to be.

Hereinafter, the present invention will be described in detail with reference to one embodiment of the present invention.

2 is a vertical structure diagram of the bipolar transistor of the present invention, in which the p-layer 17 under the emitter region and the p + layer 19 in the base region are connected to the p layer 18, and the N + layer 22 in the emitter region. And a single interconnecting poly 24 is formed between the metal layer 29 and the barrier layer of metal between the metal layer 29 and the p + layer 19 of the base region and between the metal layer 29 and the interconnecting poly 24. 28 is formed.

Using a silicon substrate (1) on a <100> crystal plane doped with boron with a resistivity of 15-200Ωcm as a starting material, an initial oxide layer of about 4000-6000Å was grown, followed by photographic and etching processes, and high concentration of arsenic ions. The buried layer 2 is formed. Afterwards, an epitaxial layer 3 doped with phosphorus is formed at about 2.0-2.5 μm, and an N-layer 4 is formed thereon, and then about 6000-8000 μs for defining an active region by a conventional method. A field oxide film 5 is formed (FIG. 3A). After the above process, a pad oxide film 6 of about 400-600 에 was formed on the entire upper surface of the substrate, and the intrinsic base region was defined using the photoresist 7, and then dose 3-7 E13 and energy 30-. 50-KeV impurity source boron is implanted to form the p-ion implantation layer 8 (FIG. 3B). The photoresist 7 is removed, the nitride film 9 of about 1200-1500 mV and the oxide film 10 of about 2500-3000 mV are deposited, and the photoresist 11 is defined to emitter region and collector region. (Figure 3c). The emitter and collector regions are defined by etching the nitride film 9 and the oxide film 10 using the photoresist 11 as a mask, and then the photoresist 11 is removed and 3-7% of the photoresist 11 is removed. P-layer 13 having a BSG film 12 containing boron (B) source deposited at a thickness of about 3000-5000 kPa, and then annealing at 900-1000 ° C. to make the BSG film 12 a diffusion source. ) (Fig. 3d). After the process, the silicon substrate is exposed through anisotropic etching to leave the BSG film 12 on only the sidewalls and the upper side of the emitter region defined by the stacked structure of the nitride film 9 and the oxide film 10. Will be formed. The p + ion implantation layer 15, which is an extransic base region, is implanted by dosing 1-3E15 and energy 30-50 KeV impurity source boron using the emitter region where the BSG side wall 14 is formed as a mask layer. Form. At this time, since the implanted ions are blocked by the BSG sidewall 14, the silicon substrate under the BSG sidewall 14 continues to maintain the p layer (Fig. 3e). After the process, the BSG film 12 is etched only on the sidewall and the top of the emitter region to remove the BSG sidewall 14. The p + layer 15, the p layer 13 under the BSG side wall 14, and the p- layer under the emitter region are grown while the silicon substrate in the exposed base region is oxidized to grow an oxide film 16 of about 2000-2500Å. The impurities in (8) diffuse to form the diffusion regions of the p + layer 19 of the Xtrin base, the p layer 18, and the p- layer 17 of the intrinsic base, respectively. At this time, the p-layer 18 formed by the sidewall oxide layer 14 connects the p-layer 17 of the intrinsic base region and the p + layer 19 of the Xtrin base region (FIG. 3f). After the above process, the nitride oxide film 9 and the pad oxide film 6 under the nitride film 9 were removed, and the polysilicon 20 was deposited at 2500-5000 Pa, and then ionized with a Dose 4-7 E15 energy 100-140 KeV impurity source arsenic. And then annealing is performed for 20-30 minutes at a temperature of 1000 ° C. in order to deposit an oxide film 21 of about 4000-5000 kPa and form an emitter region (n + layer 22 in the emitter region). 3g degrees). After the process, the photoresist is used to define the portion where the internal connection poly will be formed (FIG. 3h). Using the oxide film 21 as a mask, an internal connection poly 24 is formed on the N + layer 22 in the emitter region, and the oxide film 25 of about 5000 kV is deposited (FIG. 3i). After the above process, the opening formation site is defined using the photoresist 26 (FIG. 3j). After opening the oxide layer 25 using the photoresist 26 as a mask, the barrier metal layer 28 and the metal layer 29 of TiN are sequentially deposited, and a bipolar transistor is formed through a general photograph, an etching process, and a heat treatment process. Complete the final structure.

As described above, the intrinsic and extrinsic base regions of the present invention are connected to the p layer formed by using the BSG film containing boron as a source, thereby improving noise immunity and operating speed of the device, and also increasing the concentration of n + and p + layers. The collision of is suppressed so that the leakage current, the rise of the junction breakdown voltage and the current amplification degree can be improved, and in particular, the prevention of spike by the barrier metal, the reduction of contact resistance and the elimination of the mask layer It has a unique effect that can be simplified.

Claims (2)

In the structure of the bipolar transistor, a link region of the p layer 18 is formed between the intrinsic base p-layer 17 and the Xtrin base p + layer 19 below the high concentration emitter region and the emitter N + layer. A high performance bipolar transistor, characterized in that a single internal interconnect poly is formed between the 22 and the metal layer 29. In the method of manufacturing a bipolar transistor, an intrinsic base forming step and a stacked structure of the nitride film 9 and the oxide film 10 are used to define an emitter region, deposit the BSG film 12, and then perform annealing. And forming an BSG sidewall 14 on the side of the nitride film 9 by an anisotropic etching method and injecting impurities, and annealing to form the p + layer 19, the p layer 18, and the p- layer ( 17), an annealing process for removing the nitride film (9) and the pad oxide film (6), depositing polysilicon (20), implanting ions, and then forming an N + layer (22); And forming a barrier metal layer (28) and a metal layer (29) on the interconnect poly (24) in the emitter region.

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