JPH01169964A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a vertical type transistor of high speed and high density integration, by connecting an external base region and an internal base region, just under an aperture end of an oxide film being a first insulating film, via the lower part of a second insulating film formed on the side surface of a trench part. CONSTITUTION:An epitaxial layer 104 having a buried layer 102, is formed on a P-type substrate 100. A P-type semiconductor region 116 turning to an external base, and a thermal oxide film 122 are formed on the epitaxial layer. In an aperture formed in the thermal oxide film 122, a trench 142 is formed. A thermal silicon oxide film 150 left in the bottom side surface of the above trench, and a silicon nitride film 152 being a mask material are provided, and a P-type semiconductor region 126 turning to an internal base is formed under the trench 142. The external base 116 and an internal base 126 are connected via the lower parts of the oxide film 150 and the silicon nitride film 152, and a polysilicon electrode 124 is formed in a semiconductor region 128 turning to an emitter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to the structure of a transistor element suitable for increasing the speed and integration of bipolar type integrated circuits and the like, and a method for manufacturing the same.

BACKGROUND OF THE INVENTION In recent years in the field of bipolar integrated circuits, various new techniques have been proposed for improving the switching speed of transistors. The main improvement methods using these technologies are to make the internal base of a vertical NPN transistor shallower and narrow the width in the depth direction of the base, thereby shortening the transit time of electrons in the base; In order to reduce the delay time caused by the coupling between the parasitic base resistance and the base input capacitance that are connected in series with the parasitic base, there is a method of lowering the resistance of the parasitic base. As a method of reducing the resistance of the parasitic base, the so-called graft base method is known, in which a parasitic base region for electrode extraction is formed by diffusion with impurities at a higher concentration than the internal base, and this is used as the external base. It is being An example is the 1984 International Electron Devices Meeting Digest of Technical Papers (INTER
-NATIONAL ELECTRON DEVI
CE MEETING 0IGESTOF TE
CHNICAL PAPER5PP, 753-756
), in forming a vertical NPN transistor, the external base formed under the thermal oxide film and the internal base formed from the opening of the thermal oxide film were connected near the edge of the thermal oxide film. structure is disclosed.

Problems to be Solved by the Invention In order to increase the speed of bipolar transistors, it is necessary to simultaneously form a shallow internal base, reduce the resistance of the external base, and reduce the resistance of the collector directly below the emitter. It must be realized. As the internal base becomes shallower, the layered resistance of the internal base tends to increase;
In order to reduce this effect, a method is usually taken to narrow the width of the emitter. However, in this case, when the impurity concentration of the external base is increased, impurity atoms invade the internal base and change the impurity profile of the internal base, resulting in a decrease in the current amplification factor for DC and a decrease in the electron base for AC. Bad phenomena such as increased running time occur.

The only way to simply suppress this phenomenon is to lower the impurity concentration of the external base and reduce the lateral diffusion of the base. According to this method, penetration of the external base can be suppressed, but if the internal base is formed to a very shallow depth of 150 nanometers, various structural or manufacturing problems arise. For example, as shown in FIG. 3(a), P
An N type buried layer 1 is formed on a type silicon semiconductor substrate 100.
After forming N-type epitaxial semiconductor N104, a thin thermal oxide film 10B of about 20 nanometers is formed.
Using the silicon nitride film pattern 110 with a thickness of about 100 nanometers formed above as a mask, a dose of ff12X is applied.
Boron ions of 10" Cm-2 were ion-implanted to form a deep P-type semiconductor region 116 that would serve as an external base. Furthermore, as shown in FIG. 3(b), an oxidation-resistant silicon nitride film pattern 110 was masked. After performing thermal oxidation to form an oxide film 122 with a thickness of about 250 nanometers,
The silicon nitride film pattern 110 and the oxide film 108 are removed to form openings for emitters and ivy, a polycrystalline silicon film is deposited on the entire surface, and this is patterned to form a polycrystalline silicon film pattern 124. , Dose ff12X
After ion-implanting 10" cm of boron into the polycrystalline silicon film pattern 124 and forming a shallow P-type semiconductor region 126 serving as an active base with a depth of about 150 nanometers through heat treatment, Similarly, arsenic was ion-implanted into this polycrystalline silicon film pattern 124, and an N-type semiconductor region 128 serving as an emitter with a depth of about 50 nanometers was formed by heat treatment. Therefore, as shown in FIG. 3(b), depending on the shape of the peaked end of the oxide film pattern 122, it becomes difficult to connect the external base 116 and the internal base 126. In other words, since the open end formed at the peak-shaped end of the oxide film fluctuates unstably due to etching during the process, the connectivity itself between the internal base and the external base becomes unstable, and the rough edges become unstable. If the connection is confusing, the small lateral diffusion of the internal base below this peak
Because the effective base width is narrow, there is a drawback when punch-through leakage current occurs between the collector and emitter. Furthermore, the P-type semiconductor region 126 serving as an active base is different from the P-type semiconductor region 116 serving as an external base.
Since the N-type epitaxial semiconductor layer 04, which is formed to be shallower than the internal base, becomes the collector region directly under the internal base, the resistance becomes unnecessarily large. Therefore, there is a need for a new transistor structure and a method for manufacturing the same that solves these problems in structure, manufacturing, etc.

Means for Solving the Problems In order to solve these problems, the present invention provides an opening formed by a first insulating film formed on a semiconductor layer of a first conductivity type;
A first insulating film of a second conductivity type formed under the first insulating film.
a semiconductor region, a trench formed from the opening in the first insulating film, a second insulating film formed in the trench, and a semiconductor region left on the side surface of the trench in which the second insulating film is formed. a second insulating film opening formed at the bottom of the groove using the mask material as a mask; a second semiconductor region of a second conductivity type formed in the groove; a third semiconductor region of a first conductivity type formed in a second semiconductor region of a second conductivity type from an opening in an insulating film, wherein the first semiconductor region and the second semiconductor region A semiconductor device characterized by connecting a semiconductor region, a step of forming an opening with a first insulating film on a semiconductor layer of a first conductivity type;
forming a first semiconductor region of a second conductivity type under the first insulating film; forming a trench from an opening in the first insulating film; and forming a second insulating region in the trench. a step of forming a film, a step of leaving a mask material on the side surface of the trench where the second insulating film is formed, and a step of forming an opening in the second insulating film at the bottom of the trench using the mask material as a mask. forming a second conductivity type second semiconductor region in the trench; and forming a first conductivity type second semiconductor region from the opening of the second insulating film into the second conductivity type second semiconductor region. and a step of forming a third semiconductor region, wherein the first semiconductor region and the second semiconductor region are connected.

Effects When the measures according to the invention are applied, by way of example, to bipolar transistors, the following effects occur.

A first semiconductor region serving as an external base and a second semiconductor region serving as an internal base are separated by a second insulating film formed on the side surface of the trench directly under the edge of the opening of the oxide film serving as the first insulating film. Since the connection was made through the bottom of the base, it was possible to prevent highly concentrated impurity atoms from the external base from directly penetrating into the internal base. For this reason, it was possible to prevent the occurrence of negative phenomena such as a decrease in current amplification factor in the case of direct current, and an increase in the base transit time of electrons in case of alternating current. Furthermore, when forming an opening in the second insulating film that will become an emitter diffusion window at the bottom of the trench,
Since the mask material left on the sides of the groove was used, an isotropic wet etching method with less etching damage could be used, and the crystallinity of the emitter diffusion front surface could be maintained well.

Furthermore, since it is possible to leave the mask material with a desired thickness on the side surface of the groove, the controllability of the distance between the external base and the internal base is improved. At this time, since there is a mask material on the sides of the groove, the high concentration area of the external base and the low concentration area of the internal base are no longer directly connected, preventing deterioration of the uniformity of the internal base. did it. On the other hand, because the internal base was made to be as deep as the external base due to the groove formed in the opening of the oxide film, which is the first insulating film, N The mold epitaxial layer could be made thinner, which made it possible to reduce the collector resistance.

As a result of the above, it was possible to prevent the occurrence of bad phenomena such as a decrease in current amplification factor in the case of direct current, and an increase in the base transit time of electrons in case of alternating current, and it was possible to improve the switching time of the transistor.

Furthermore, even if the first semiconductor region of the second conductivity type is formed in advance in the planned opening of the oxide film, when forming the groove in this opening, Since the unnecessary first semiconductor region can be removed, it is possible to substantially eliminate the influence on the impurity profile of the second conductivity type second semiconductor region that will be formed later on the lower surface of the trench and will become the internal base. did it.

As a result, good device characteristics with little variation in current amplification factor were obtained.

Embodiment A first embodiment in which the structure method according to the present invention is applied to the emitter-base junction of a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 1, in an N-type epitaxial semiconductor layer 104 having an N-type buried layer 102 formed on a P-type silicon semiconductor substrate 100, an opening for a thermal oxide film 122 is formed, and this oxide film A P-type semiconductor region 116 that serves as an external base under the main part of the oxide film, a trench 142 formed within the opening of this oxide film, and a thermal silicon oxide film that is a second insulating film left on the sides of the trench. +50, the silicon nitride film 152 which is the mask material, and further,
A P-type semiconductor region 126 serving as an internal base is formed at the bottom of this groove.

The external base 110 and the internal base 126 are connected to the oxide film 15.
A polysilicon electrode 124 is formed in an N-type semiconductor region 128 that is connected to the silicon nitride film 152 through the lower part of the silicon nitride film 152 and serves as an emitter.

As an example of a method for forming such an emitter-base junction, if the polysilicon electrode 124 is used as a diffusion source for the internal base 126 and the emitter 12H, the depth of the internal base 15
It is possible to realize a structure excellent in high speed with a depth of 0 nanometers and an emitter depth of 50 nanometers, and commonly used methods such as ion implantation can also be employed. In addition, it was possible to prevent highly concentrated impurities from the external base from directly penetrating into the internal base and change the impurity profile of the internal base, thereby stabilizing the connectivity of the base. Further, in the structure shown in FIG. 1, the side surfaces of the grooves have a tapered shape, but may have any shape as required. If a mixed solution of hydrofluoric acid and nitric acid was used to form the tapered groove, etching damage to the surface of the groove could be prevented. Furthermore, the oxide film 1 which is the second insulating film is
50 was opened by wet etching using ammonium fluoride or the like, which causes little etching damage, using the nitride film 152 as a mask material, so that a very good emitter-base junction could be formed. Oxide film 122 which is the first insulating film
A groove 142 formed in the opening of the inner base 126
Since the depth of the N-type epitaxial layer can be made as deep as that of the external base 116, the N-type epitaxial layer left between the internal base and the N-type buried layer immediately below it can be made thinner without deteriorating (reducing) the collector breakdown voltage. It was possible to reduce the collector resistance.

Next, a second example in which the method of the present invention is applied to a method for manufacturing the main part of a bipolar NPN transistor will be described.
This will be explained using a) to (e).

As shown in FIG. 2(a), a P-type silicon semiconductor substrate 10
After forming an N-type buried layer 102 on 0, an N-type epitaxial semiconductor layer 104 was formed. A thin polysilicon layer 160 of about 300 nanometers is formed on this semiconductor layer +04, and the polysilicon layer 160 is formed by ion implantation.
Boron is implanted at a dose of 0, tlX 1016 cm-2, and a silicon oxide film 122 with a thickness of about 300 nanometers is deposited. After that, a P-type film, which will become an external base, is heat-treated at about 900 degrees. A semiconductor region 116 was formed. Here, as shown in the figure, a resist pattern 158 was formed by a photomask process on the area where the emitter was to be formed.

As shown in FIG. 2(b), the area where the emitter is to be formed is etched using the resist pattern 158 as a mask.
．． A groove 142 with a width of 5 microns is formed, and the surface of this groove is roughly thermally oxidized to form an oxide film 1 of about 100 nanometers.
After that, a silicon nitride film 152 of about 50 nanometers and a silicon oxide film 162 of about 100 nanometers were sequentially deposited.

As shown in FIG. 2(c), an oxide film 162 and a nitride film 1, which serve as mask materials, are etched on the sides of the trench by anisotropic reactive etching.
52 remained.

As shown in FIG. 2(d), the thermal oxide film 164 at the bottom of the trench is removed using ammonium fluoride using the oxide film 162 and nitride film 152 on the side surfaces of the trench as a mask to form an opening.
A polysilicon film 124 approximately 250 nanometers thick was deposited. This polysilicon 124 is implanted with boron at a dose of j12 x 10" cm-2, and is heat-treated at about 950 degrees to form an internal base of about 15
A P-type semiconductor region 126 with a depth of 0 nanometers was formed.

As shown in FIG. 2(e), after arsenic is ion-implanted into polysilicon 124, an N-type semiconductor region 128 which becomes an emitter with a depth of about 50 nanometers is formed by heat treatment at about 900 degrees. Formed. After forming a polysilicon film pattern 124 by a photo mask process, aluminum electrodes 166A, 166B, etc. were formed according to a normal manufacturing method.

As described above, by the method of the present invention, a vertical NPN transistor is formed, and an active element part (internal base) structure with a base width of approximately 100 nanometers and excellent high speed performance is obtained. Since the external base and the internal base were well connected, generation of punch-through current between the collector and emitter at the emitter end could be prevented. In general, the collector resistance was reduced by forming the groove, so the switching characteristics were improved.
Furthermore, since the external base was prevented from penetrating into the internal base, a good element with little variation in characteristics was obtained.

According to the method of the present invention, the emitter of the bipolar element is the gate, the external bases on both sides of the gate are the source,
When considered as a drain, it can function as a junction field effect transistor with the internal base as a channel portion. In this way, the method of the present invention can be applied not only to bipolar devices but also to various semiconductor devices.

Effects of the Invention The structure of the present invention and its manufacturing method provide an active element structure that is excellent in high speed and high integration, and a manufacturing method with good controllability for realizing this active element part. I was able to do that.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of a bipolar NPN) transistor according to the present invention, FIG. 2 is a series of cross-sectional views showing a method for manufacturing a bipolar NPN) transistor according to the method of the present invention, and FIG. 3 is a conventional method. 1 is a cross-sectional view illustrating the structure of a bipolar NPN transistor and problems in manufacturing it; FIG. 100...P type semiconductor substrate, 102...N type buried layer, 104...N type semiconductor layer, 106.116, U
S, +26...P semiconductor region, 128...N type semiconductor region, 108.122.162·ψ·silicon oxide film, 110.152...silicon nitride film, 124.16
0... Polycrystalline silicon film, 158... Resist, 1
66A, 166B... Aluminum electrode, 142
◆・φ groove. Name of agent: Patent attorney Toshio Nakao

Claims (2)

[Claims] (1) an opening formed by a first insulating film formed on a semiconductor layer of a first conductivity type; and a first semiconductor region of a second conductivity type formed under the first insulating film; a groove formed from an opening in the first insulating film, a second insulating film formed in the groove, and a mask material left on a side surface of the groove in which the second insulating film was formed; an opening in a second insulating film formed at the bottom of the trench using the mask material as a mask; a second semiconductor region of a second conductivity type formed in the trench;
A structure including a third semiconductor region of the first conductivity type formed in the second semiconductor region of the second conductivity type from the opening of the second insulating film, wherein the first semiconductor region and the Second
A semiconductor device characterized in that it connects a semiconductor region. (2) A step of forming an opening with a first insulating film on a semiconductor layer of a first conductivity type, and a step of forming a first semiconductor region of a second conductivity type under the first insulating film. forming a groove from an opening in the first insulating film; forming a second insulating film in the groove; and applying a mask material to the side surface of the groove in which the second insulating film is formed. a step of forming a second insulating film at the bottom of the groove using the mask material as a mask; and a step of forming a second insulating film of a second conductivity type in the groove.
and forming a third semiconductor region of the first conductivity type in the second semiconductor region of the second conductivity type from the opening of the second insulating film, Said first
A method of manufacturing a semiconductor device, characterized in that the semiconductor region of the second semiconductor region is connected to the second semiconductor region.