JPH081907B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a transistor element suitable for high speed and high integration of a bipolar type integrated circuit and a method for manufacturing the same. Involve

2. Description of the Related Art Recently, in the field of bipolar integrated circuits, various new technologies have been proposed for improving the switching speed of transistors. The major improvements made by these technologies are to make the internal base of a vertical NPN transistor shallow to form a narrow width in the depth direction of the base to shorten the transit time of electrons in the base. On the other hand, there is a method of lowering the resistance of this parasitic base in order to reduce the delay time due to the coupling between the parasitic base resistance and the base input capacitance that enter in series. As a method of reducing the resistance of the parasitic base, a so-called graft base method is known, in which a parasitic base region for extracting an electrode is formed by diffusion with impurities having a higher concentration than the internal base, and this is used as an external base. Has been. For example, the 1984 International Electron Device Meeting Digest of Technical Papers (INTERNATIONAL E
LECTRON DEVICE MEETING DIGEST OF TECHNICAL PAPERS
PP.753-756), in the formation of a vertical NPN transistor, the external base formed under the thermal oxide film and the internal base formed from the opening of the thermal oxide film are close to the edge of the thermal oxide film. A connected structure is disclosed.

Problems to be Solved by the Invention In order to increase the speed of a bipolar transistor, it is necessary to simultaneously form a shallow internal base and a low resistance external base. As the inner base is made shallower, the layered resistance of the inner base is likely to increase, and in order to reduce this effect, a method of narrowing the width of the emitter is usually adopted. However, in this case, if the high-concentration impurity concentration of the external base is increased, the impurity atoms invade the internal base and change the impurity profile of the internal base. A bad phenomenon such as an increase in the base transit time of the electron occurs. The only way to suppress this phenomenon is to reduce the impurity concentration of the external base and reduce the lateral diffusion of the base. According to this method, the penetration of the external base is suppressed, but when the internal base is formed to have a very shallow depth of 150 nanometers, the following structural or manufacturing problems occur. That is, since the opening end formed by the beak-shaped end portion of the oxide film fluctuates unstable due to etching during the process, the connectivity itself between the internal base and the external base becomes unstable, and further, the connection is In the worst case, since the lateral diffusion of the internal base under this beak is small, the effective base width is narrowed, and there is a drawback that punch-through leakage current between the collector and the emitter is likely to occur. It was For example, as shown in FIG. 3A, after forming an N type buried layer 102 on a P type silicon semiconductor substrate 100 and forming an N type epitaxial semiconductor layer 104, about 20 nanometers A dose of 2 × 1 is used by using a silicon nitride film pattern 110 having a thickness of about 100 nanometers formed on a thin thermal oxide film 108 of a meter as a mask.
Ion implantation of boron of ¹⁵ / cm ² was performed to form a P-type semiconductor region 116 to be an external base. Further, as shown in FIG. 3 (b), an oxidation resistant silicon nitride film pattern 11 is formed.
Thermal oxidation is performed using 0 as a mask to form an oxide film 122 having a thickness of about 250 nanometers, the silicon nitride film pattern 110 and the oxide film 108 are removed, and an opening for an emitter is formed.
A polycrystalline silicon film is deposited on the entire surface and patterned to form a polycrystalline silicon film pattern 124. Further, boron having a dose amount of 2 × 10 ¹⁴ / cm ² is ion-deposited in the polycrystalline silicon film pattern 124. About 150 after injection and heat treatment
After forming the P-type semiconductor region 126 to be the active base having a depth of nanometer, arsenic is similarly ion-implanted into the polycrystalline silicon film pattern 124, and the heat treatment is performed to a depth of about 50 nanometers. An N-type semiconductor region 128 that will be the emitter of the meter was formed. According to such a manufacturing method,
The oxide film pattern 12 as shown in FIG.
Depending on the shape of the beak-shaped end portion of 2, the connectivity between the external base 116 and the internal base 126 becomes difficult. Therefore, there is a need for a novel transistor structure and a method for manufacturing a som that solves the problems in the structure and manufacturing due to the unstable connection between the external base and the internal base.

Means for Solving the Problems In order to solve such problems, the present invention provides an insulating film having a beak-shaped end portion in the periphery formed on a semiconductor layer of the first conductivity type, an opening, and A first semiconductor region of the second conductivity type formed immediately below the beak-shaped end portion of the insulating film, and a second conductivity type first semiconductor region formed below the beak-shaped end portion of the insulating film. A second semiconductor region and a groove formed in the opening of the insulating film having the beak-shaped end,
A structure having a third semiconductor region of the second conductivity type formed in the groove and a fourth semiconductor region of the first conductivity type formed in the third semiconductor region of the second conductivity type A structure of a semiconductor device, characterized in that the second semiconductor region and the third semiconductor region are connected via the first semiconductor region, and an oxidation-resistant structure on the first conductivity type semiconductor layer. Forming a mask material pattern; forming a second semiconductor type first semiconductor region on the surface of the semiconductor layer at least immediately below the oxidation resistant mask material pattern and immediately below an end portion thereof; Forming a second semiconductor region of the second conductivity type around the mask material pattern, and an end portion of the beak material around the mask material pattern by an oxidation method using the oxidation resistant mask material pattern as a mask. Forming an oxide film having A step of removing the oxidation-resistant mask material pattern to form an opening of the oxide film pattern having the beak-shaped end portion, and a step of forming an opening of the oxide film pattern having the beak-shaped end portion. Forming a groove in the groove, forming a third semiconductor region of the second conductivity type in the groove, and forming a fourth semiconductor region of the first conductivity type in the third semiconductor region. And the second
And a third semiconductor region are connected to each other through the first semiconductor region, and a method for manufacturing a semiconductor device is provided.

Operation When the means according to the present invention is applied to the emitter-base junction of a bipolar transistor as an example, the following operation occurs.

A first semiconductor of a second conductivity type serving as an intermediate base that connects a second semiconductor region serving as an external base and a third semiconductor region serving as an internal base immediately below an end of an opening of an oxide film that is an insulating film. Since the impurity concentration of the semiconductor region or the total number of impurity atoms per unit area can be made smaller than that of the internal base, it is possible to prevent the impurity atoms of the external base from directly entering the internal base. did it. Moreover, since the inner base can be made as deep as the outer base by the groove portion formed in the opening of the oxide film, the N-type epitaxial layer left between the inner base and the N-type buried layer immediately below can be made deeper. As a result, the collector resistance could be reduced. From the above, it was possible to prevent the occurrence of bad phenomena such as a decrease in current amplification factor in terms of direct current and an increase in base transit time of electrons in terms of alternating current. Furthermore, since the collector resistance could be reduced, the switching time of the transistor could be improved.

Further, since the external base and the internal base are not directly connected to each other, the impurity profile of each can be optimized independently, so that the controllability of the diffusion of impurities is facilitated and the manufacturing yield is improved.

Further, when the first semiconductor region of the second conductivity type is previously formed in the opening of the oxide film having the beak-shaped end portion, the beak-shaped portion is formed by forming the groove portion in this opening. Since the unnecessary first semiconductor region other than immediately below the end of the second semiconductor region can be removed, the intermediate base to the impurity profile of the third semiconductor region of the second conductivity type, which will be an internal base formed later on the bottom surface of the groove, is formed. It was possible to almost eliminate the influence of the impurity atoms due to the ion implantation during the formation of. As a result, good device characteristics with less variation in current amplification factor were obtained.

EXAMPLE A first example in which the method of structure according to the present invention is applied to the emitter-base junction of a bipolar NPN transistor,
This will be described with reference to FIG.

As shown in FIG. 1, in the N-type epitaxial semiconductor layer 104 having the N-type buried layer 102 formed on the P-type silicon semiconductor substrate 100, the thermal oxide film 122 having a beak-shaped end portion is formed. The P-type semiconductor region 116 serving as an external base is formed under the main portion of the oxide film, the groove 142 crystallized in the opening formed by the oxide film, and the P-type semiconductor region serving as an internal base is formed in the lower portion of the groove. A semiconductor region 126 is formed. External base 116 and internal base 126
Are connected via a P-type semiconductor region 118 which is an intermediate base formed immediately below the beak-shaped end of the oxide film,
A polysilicon electrode 124 is formed on an N-type semiconductor region 128 which will be an emitter.

As an example of a method of forming such an emitter-base junction, if the polysilicon electrode 124 is used as a diffusion source for the internal base 126 and the emitter 128, the internal base depth is 150 nanometers and the emitter depth is 50 nanometers. It is possible to realize a structure with excellent properties, and since the internal base and the external base can be connected via the intermediate base having a relatively low impurity concentration, the high concentration impurities of the external base penetrate into the internal base, It was possible to prevent changing the impurity profile of and to stabilize the connectivity of the base. Further, in the structure of FIG. 1, the side surface of the groove is substantially vertical, but it may be formed in any shape as required. For example, when the beak-shaped end portion of the oxide film and the P-type semiconductor region 116 serving as an external base are considerably separated from each other, an isotropic etching method is used to form a groove portion under the beak-shaped end portion. If the groove is formed so that the side surface of the groove is submerged, the distance between the internal base and the external base can be reduced, that is, the width of the intermediate base can be reduced.
There are advantages such as reduction of parasitic base resistance.

Next, a second embodiment in which the method of the present invention is applied to a method for manufacturing a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 2A, a P-type silicon semiconductor substrate 10
After forming the N type buried layer 102 on the 0, the N type epitaxial semiconductor layer 104 was formed. P-type element isolation region 1
After forming 06, a thin thermal oxide film 108 of about 20 nanometers is formed.
Thermal oxidation was performed using the silicon nitride films 110A and 110B having a thickness of about 100 nanometers formed on the A and 108B as masks to form a thick oxide film 112 having a thickness of about 600 nanometers.

As shown in FIG. 2B, a resist pattern 114 is formed by a photomask process, and using this as a mask, a silicon nitride film pattern 110C having a width of about 1 micron is left on a portion where an emitter is to be formed. A P-type semiconductor region 11 serving as an external base is formed by ion-implanting boron with a dose amount of 2 × 10 ¹⁵ / cm ^{2 using} the pattern 114 as a mask.
Formed 6.

As shown in FIG. 2 (c), after removing the resist pattern 114, phosphorus is ion-implanted to selectively form an N-type semiconductor region 120, and further, a dose amount of 5 × 10 ¹² / c.
Boron of m ² was ion-implanted through the silicon nitride film pattern 110C so as to have a peak concentration at the silicon interface to form a P-type shallow semiconductor region 118 serving as an intermediate base.

As shown in FIG. 2D, thermal oxidation is performed using the oxidation resistant silicon nitride film pattern 110C as a mask, and the thickness is about 20.
An oxide film 122 of 0 nanometer was formed.

As shown in FIG. 2 (e), the silicon nitride film pattern 110 is formed.
After forming an opening for the emitter from which C and the oxide film 108A were removed, a resist pattern 140 was formed, and using this as a mask, a groove portion 142 was formed in the opening for the emitter. Due to the formation of this groove, most of the P-type shallow semiconductor region 118, which was the intermediate base and was formed in the emitter opening, was removed.

As shown in FIG. 2 (f), a polycrystalline silicon film is deposited on the entire surface and patterned to form polycrystalline silicon film patterns 124A and 124B, and a dose amount of 2 × 10 ¹⁴ / c.
After ion-implanting m ² boron into the polycrystalline silicon film pattern 124 A and forming a P-type semiconductor region 126 to be an active base having a depth of about 150 nanometers by heat treatment, arsenic is similarly added. Ions are implanted into the polycrystalline silicon film pattern 124A and a heat treatment is performed to form an N-type semiconductor region 128 to be an emitter having a depth of about 50 nanometers.

As shown in FIG. 2 (g), a silicon oxide film 130 is formed on the entire surface.
After depositing, the aluminum electrodes 132A, 132B, 132C and the like were formed according to a usual manufacturing method.

As described above, according to the method of the present invention, a vertical NPN transistor is formed, the base width of which is about 100 nm and an active element portion (internal base) structure excellent in high speed is obtained. Since the external base and the internal base were well connected through the thin and shallow intermediate base, it was possible to prevent the generation of the leak current between the collector and the emitter under the beak-shaped oxide film. . Furthermore, since the formation of the groove portion reduced the collector resistance, the switching characteristics were improved, and the unnecessary intermediate base formed in the internal base formation planned portion was also removed. Good characteristics with little variation were obtained.

According to the method of the present invention, when the emitter of the bipolar element is regarded as the gate and the external bases on both sides of this gate are regarded as the source and the drain, the bipolar element can function as a junction field effect transistor having the internal base as the channel portion. it can. Thus, the method of the present invention can be applied not only to bipolar devices but also to various semiconductor devices.

EFFECTS OF THE INVENTION By the structure of the present invention and the method of manufacturing the same, a semiconductor device having a structure of an active element portion excellent in speeding up and high integration and having good controllability in manufacturing the active element portion is provided. We were able to.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a bipolar NPN transistor according to the present invention, FIG. 2 is a sectional view of a series of steps showing a method for manufacturing a bipolar NPN transistor according to the method of the present invention, and FIG. 3 is a bipolar NPN according to a conventional method. 6A and 6B are cross-sectional views illustrating a structure of a transistor and a problem in manufacturing the transistor. 100 ... P-type semiconductor substrate, 102 ... N-type buried layer, 104
... N-type semiconductor layer, 106, 116, 118, 126 ... P-type semiconductor region, 120, 128 ... N-type semiconductor region, 108, 112, 122, 130
...... Silicon oxide film, 110 …… Silicon nitride film, 124 ……
Polycrystalline silicon film, 114, 140 ... Resist, 132 ... Aluminum electrode, 142 ... Groove part.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-223158 (JP, A) JP-A-60-34063 (JP, A) JP-A-54-103676 (JP, A) JP-A-60- 113968 (JP, A)

Claims (7)

[Claims] 1. An opening of an insulating film formed on a semiconductor layer of the first conductivity type and having a beak-shaped end portion in the periphery, and an opening formed at least directly under the beak-shaped end portion of the insulating film. An insulating film having a first semiconductor region of a second conductivity type, a second semiconductor region of a second conductivity type formed in a lower portion of the insulating film other than the beak-shaped end portion, and the beak-shaped end portion A groove formed in the opening, a third semiconductor region of the second conductivity type formed in the groove, and a first conductivity type formed in the third semiconductor region of the second conductivity type. A structure having a fourth semiconductor region, wherein the second semiconductor region and the third semiconductor region are connected via the first semiconductor region. 2. A first semiconductor region is used as an intermediate base, a second semiconductor region is used as an outer base, a third semiconductor region is used as an inner base, and a fourth semiconductor region is used as an emitter. The semiconductor device according to item 1. 3. The first semiconductor region according to claim 1, wherein the total number of impurity atoms per unit area is smaller than that of the second conductivity type third semiconductor region. The semiconductor device according to item 2. 4. A step of forming an oxidation-resistant mask material pattern on a semiconductor layer of the first conductivity type, and a second step on at least the surface of the semiconductor layer immediately below the oxidation-resistant mask material pattern and immediately below an end thereof. Forming a conductive type first semiconductor region, forming a second conductive type second semiconductor region around the oxidation resistant mask material pattern, and forming the oxidation resistant mask material pattern. A step of forming an oxide film having a beak-shaped end portion around the mask material pattern by a oxidization method as a mask, and removing the oxidation-resistant mask material pattern to perform oxidation having the beak-shaped end portion. Forming an opening of the film pattern, forming a groove in the opening of the oxide film pattern having the beak-shaped end,
The method further comprises the steps of forming a third semiconductor region of the second conductivity type in the groove, and forming a fourth semiconductor region of the first conductivity type in the third semiconductor region. A method of manufacturing a semiconductor device, comprising connecting a semiconductor region and the third semiconductor region via the first semiconductor region. 5. The first semiconductor region is used as an intermediate base, the second semiconductor region is used as an outer base, the third semiconductor region is used as an inner base, and the fourth semiconductor region is used as an emitter. The method for manufacturing a semiconductor device according to item 4. 6. The method according to claim 4, wherein the total number of impurity atoms per unit area of the first semiconductor region is smaller than that of the third semiconductor region of the second conductivity type. 5. A method of manufacturing a semiconductor device according to item 5. 7. A third semiconductor region of the second conductivity type and a first semiconductor region.
A fourth semiconductor region of conductivity type is formed by using the same polycrystalline semiconductor as a diffusion source.
Item 7. A method for manufacturing a semiconductor device according to any one of Items 6 to 6.